/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2016 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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**********************************************************************/
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#include <linux/netdevice.h>
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#include "liquidio_common.h"
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#include "octeon_droq.h"
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#include "octeon_iq.h"
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#include "response_manager.h"
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#include "octeon_device.h"
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#include "octeon_mem_ops.h"
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#define MEMOPS_IDX BAR1_INDEX_DYNAMIC_MAP
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#ifdef __BIG_ENDIAN_BITFIELD
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static inline void
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octeon_toggle_bar1_swapmode(struct octeon_device *oct, u32 idx)
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{
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u32 mask;
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mask = oct->fn_list.bar1_idx_read(oct, idx);
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mask = (mask & 0x2) ? (mask & ~2) : (mask | 2);
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oct->fn_list.bar1_idx_write(oct, idx, mask);
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}
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#else
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#define octeon_toggle_bar1_swapmode(oct, idx)
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#endif
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static void
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octeon_pci_fastwrite(struct octeon_device *oct, u8 __iomem *mapped_addr,
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u8 *hostbuf, u32 len)
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{
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while ((len) && ((unsigned long)mapped_addr) & 7) {
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writeb(*(hostbuf++), mapped_addr++);
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len--;
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}
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octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX);
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while (len >= 8) {
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writeq(*((u64 *)hostbuf), mapped_addr);
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mapped_addr += 8;
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hostbuf += 8;
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len -= 8;
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}
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octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX);
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while (len--)
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writeb(*(hostbuf++), mapped_addr++);
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}
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static void
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octeon_pci_fastread(struct octeon_device *oct, u8 __iomem *mapped_addr,
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u8 *hostbuf, u32 len)
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{
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while ((len) && ((unsigned long)mapped_addr) & 7) {
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*(hostbuf++) = readb(mapped_addr++);
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len--;
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}
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octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX);
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while (len >= 8) {
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*((u64 *)hostbuf) = readq(mapped_addr);
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mapped_addr += 8;
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hostbuf += 8;
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len -= 8;
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}
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octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX);
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while (len--)
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*(hostbuf++) = readb(mapped_addr++);
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}
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/* Core mem read/write with temporary bar1 settings. */
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/* op = 1 to read, op = 0 to write. */
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static void
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__octeon_pci_rw_core_mem(struct octeon_device *oct, u64 addr,
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u8 *hostbuf, u32 len, u32 op)
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{
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u32 copy_len = 0, index_reg_val = 0;
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unsigned long flags;
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u8 __iomem *mapped_addr;
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u64 static_mapping_base;
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static_mapping_base = oct->console_nb_info.dram_region_base;
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if (static_mapping_base &&
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static_mapping_base == (addr & ~(OCTEON_BAR1_ENTRY_SIZE - 1ULL))) {
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int bar1_index = oct->console_nb_info.bar1_index;
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mapped_addr = oct->mmio[1].hw_addr
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+ (bar1_index << ilog2(OCTEON_BAR1_ENTRY_SIZE))
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+ (addr & (OCTEON_BAR1_ENTRY_SIZE - 1ULL));
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if (op)
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octeon_pci_fastread(oct, mapped_addr, hostbuf, len);
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else
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octeon_pci_fastwrite(oct, mapped_addr, hostbuf, len);
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return;
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}
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spin_lock_irqsave(&oct->mem_access_lock, flags);
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/* Save the original index reg value. */
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index_reg_val = oct->fn_list.bar1_idx_read(oct, MEMOPS_IDX);
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do {
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oct->fn_list.bar1_idx_setup(oct, addr, MEMOPS_IDX, 1);
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mapped_addr = oct->mmio[1].hw_addr
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+ (MEMOPS_IDX << 22) + (addr & 0x3fffff);
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/* If operation crosses a 4MB boundary, split the transfer
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* at the 4MB
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* boundary.
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*/
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if (((addr + len - 1) & ~(0x3fffff)) != (addr & ~(0x3fffff))) {
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copy_len = (u32)(((addr & ~(0x3fffff)) +
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(MEMOPS_IDX << 22)) - addr);
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} else {
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copy_len = len;
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}
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if (op) { /* read from core */
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octeon_pci_fastread(oct, mapped_addr, hostbuf,
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copy_len);
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} else {
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octeon_pci_fastwrite(oct, mapped_addr, hostbuf,
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copy_len);
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}
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len -= copy_len;
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addr += copy_len;
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hostbuf += copy_len;
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} while (len);
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oct->fn_list.bar1_idx_write(oct, MEMOPS_IDX, index_reg_val);
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spin_unlock_irqrestore(&oct->mem_access_lock, flags);
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}
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void
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octeon_pci_read_core_mem(struct octeon_device *oct,
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u64 coreaddr,
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u8 *buf,
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u32 len)
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{
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__octeon_pci_rw_core_mem(oct, coreaddr, buf, len, 1);
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}
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void
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octeon_pci_write_core_mem(struct octeon_device *oct,
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u64 coreaddr,
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const u8 *buf,
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u32 len)
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{
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__octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)buf, len, 0);
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}
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u64 octeon_read_device_mem64(struct octeon_device *oct, u64 coreaddr)
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{
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__be64 ret;
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__octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)&ret, 8, 1);
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return be64_to_cpu(ret);
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}
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u32 octeon_read_device_mem32(struct octeon_device *oct, u64 coreaddr)
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{
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__be32 ret;
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__octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)&ret, 4, 1);
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return be32_to_cpu(ret);
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}
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void octeon_write_device_mem32(struct octeon_device *oct, u64 coreaddr,
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u32 val)
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{
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__be32 t = cpu_to_be32(val);
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__octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)&t, 4, 0);
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}
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