/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2016 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more details.
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***********************************************************************/
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/*! \file cn23xx_vf_regs.h
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* \brief Host Driver: Register Address and Register Mask values for
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* Octeon CN23XX vf functions.
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*/
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#ifndef __CN23XX_VF_REGS_H__
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#define __CN23XX_VF_REGS_H__
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#define CN23XX_CONFIG_XPANSION_BAR 0x38
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#define CN23XX_CONFIG_PCIE_CAP 0x70
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#define CN23XX_CONFIG_PCIE_DEVCAP 0x74
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#define CN23XX_CONFIG_PCIE_DEVCTL 0x78
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#define CN23XX_CONFIG_PCIE_LINKCAP 0x7C
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#define CN23XX_CONFIG_PCIE_LINKCTL 0x80
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#define CN23XX_CONFIG_PCIE_SLOTCAP 0x84
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#define CN23XX_CONFIG_PCIE_SLOTCTL 0x88
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#define CN23XX_CONFIG_PCIE_FLTMSK 0x720
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/* The input jabber is used to determine the TSO max size.
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* Due to H/W limitation, this need to be reduced to 60000
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* in order to to H/W TSO and avoid the WQE malfarmation
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* PKO_BUG_24989_WQE_LEN
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*/
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#define CN23XX_DEFAULT_INPUT_JABBER 0xEA60 /*60000*/
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/* ############## BAR0 Registers ################ */
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/* Each Input Queue register is at a 16-byte Offset in BAR0 */
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#define CN23XX_VF_IQ_OFFSET 0x20000
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/*###################### REQUEST QUEUE #########################*/
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/* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
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#define CN23XX_VF_SLI_IQ_INSTR_COUNT_START64 0x10040
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/* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
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#define CN23XX_VF_SLI_IQ_BASE_ADDR_START64 0x10010
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/* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
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#define CN23XX_VF_SLI_IQ_DOORBELL_START 0x10020
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/* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
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#define CN23XX_VF_SLI_IQ_SIZE_START 0x10030
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/* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
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* gather list fetches. SLI_PKT(0..63)_INPUT_CONTROL.
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*/
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#define CN23XX_VF_SLI_IQ_PKT_CONTROL_START64 0x10000
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/*------- Request Queue Macros ---------*/
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#define CN23XX_VF_SLI_IQ_PKT_CONTROL64(iq) \
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(CN23XX_VF_SLI_IQ_PKT_CONTROL_START64 + ((iq) * CN23XX_VF_IQ_OFFSET))
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#define CN23XX_VF_SLI_IQ_BASE_ADDR64(iq) \
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(CN23XX_VF_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN23XX_VF_IQ_OFFSET))
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#define CN23XX_VF_SLI_IQ_SIZE(iq) \
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(CN23XX_VF_SLI_IQ_SIZE_START + ((iq) * CN23XX_VF_IQ_OFFSET))
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#define CN23XX_VF_SLI_IQ_DOORBELL(iq) \
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(CN23XX_VF_SLI_IQ_DOORBELL_START + ((iq) * CN23XX_VF_IQ_OFFSET))
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#define CN23XX_VF_SLI_IQ_INSTR_COUNT64(iq) \
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(CN23XX_VF_SLI_IQ_INSTR_COUNT_START64 + ((iq) * CN23XX_VF_IQ_OFFSET))
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/*------------------ Masks ----------------*/
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#define CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32)
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#define CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29)
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/* Number of instructions to be read in one MAC read request.
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* setting to Max value(4)
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*/
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#define CN23XX_PKT_INPUT_CTL_RDSIZE (3 << 25)
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#define CN23XX_PKT_INPUT_CTL_IS_64B BIT(24)
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#define CN23XX_PKT_INPUT_CTL_RST BIT(23)
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#define CN23XX_PKT_INPUT_CTL_QUIET BIT(28)
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#define CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22)
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#define CN23XX_PKT_INPUT_CTL_DATA_NS BIT(8)
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#define CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP BIT(6)
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#define CN23XX_PKT_INPUT_CTL_DATA_RO BIT(5)
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#define CN23XX_PKT_INPUT_CTL_USE_CSR BIT(4)
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#define CN23XX_PKT_INPUT_CTL_GATHER_NS BIT(3)
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#define CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP (2)
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#define CN23XX_PKT_INPUT_CTL_GATHER_RO (1)
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/** Rings per Virtual Function [RO] **/
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#define CN23XX_PKT_INPUT_CTL_RPVF_MASK (0x3F)
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#define CN23XX_PKT_INPUT_CTL_RPVF_POS (48)
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/* These bits[47:44][RO] give the Physical function number info within the MAC*/
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#define CN23XX_PKT_INPUT_CTL_PF_NUM_MASK (0x7)
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#define CN23XX_PKT_INPUT_CTL_PF_NUM_POS (45)
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/** These bits[43:32][RO] give the virtual function number info within the PF*/
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#define CN23XX_PKT_INPUT_CTL_VF_NUM_MASK (0x1FFF)
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#define CN23XX_PKT_INPUT_CTL_VF_NUM_POS (32)
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#define CN23XX_PKT_INPUT_CTL_MAC_NUM_MASK (0x3)
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#define CN23XX_PKT_INPUT_CTL_MAC_NUM_POS (29)
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#define CN23XX_PKT_IN_DONE_WMARK_MASK (0xFFFFULL)
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#define CN23XX_PKT_IN_DONE_WMARK_BIT_POS (32)
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#define CN23XX_PKT_IN_DONE_CNT_MASK (0x00000000FFFFFFFFULL)
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#ifdef __LITTLE_ENDIAN_BITFIELD
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#define CN23XX_PKT_INPUT_CTL_MASK \
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(CN23XX_PKT_INPUT_CTL_RDSIZE \
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| CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP \
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| CN23XX_PKT_INPUT_CTL_USE_CSR)
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#else
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#define CN23XX_PKT_INPUT_CTL_MASK \
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(CN23XX_PKT_INPUT_CTL_RDSIZE \
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| CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP \
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| CN23XX_PKT_INPUT_CTL_USE_CSR \
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| CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP)
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#endif
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/** Masks for SLI_PKT_IN_DONE(0..63)_CNTS Register */
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#define CN23XX_IN_DONE_CNTS_PI_INT BIT_ULL(62)
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#define CN23XX_IN_DONE_CNTS_CINT_ENB BIT_ULL(48)
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/*############################ OUTPUT QUEUE #########################*/
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/* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */
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#define CN23XX_VF_SLI_OQ_PKT_CONTROL_START 0x10050
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/* 64 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */
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#define CN23XX_VF_SLI_OQ0_BUFF_INFO_SIZE 0x10060
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/* 64 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */
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#define CN23XX_VF_SLI_OQ_BASE_ADDR_START64 0x10070
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/* 64 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */
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#define CN23XX_VF_SLI_OQ_PKT_CREDITS_START 0x10080
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/* 64 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */
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#define CN23XX_VF_SLI_OQ_SIZE_START 0x10090
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/* 64 registers for Output Queue Packet Count - SLI_PKT0_CNTS */
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#define CN23XX_VF_SLI_OQ_PKT_SENT_START 0x100B0
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/* 64 registers for Output Queue INT Levels - SLI_PKT0_INT_LEVELS */
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#define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_START64 0x100A0
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/* Each Output Queue register is at a 16-byte Offset in BAR0 */
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#define CN23XX_VF_OQ_OFFSET 0x20000
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/*------- Output Queue Macros ---------*/
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#define CN23XX_VF_SLI_OQ_PKT_CONTROL(oq) \
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(CN23XX_VF_SLI_OQ_PKT_CONTROL_START + ((oq) * CN23XX_VF_OQ_OFFSET))
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#define CN23XX_VF_SLI_OQ_BASE_ADDR64(oq) \
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(CN23XX_VF_SLI_OQ_BASE_ADDR_START64 + ((oq) * CN23XX_VF_OQ_OFFSET))
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#define CN23XX_VF_SLI_OQ_SIZE(oq) \
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(CN23XX_VF_SLI_OQ_SIZE_START + ((oq) * CN23XX_VF_OQ_OFFSET))
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#define CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(oq) \
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(CN23XX_VF_SLI_OQ0_BUFF_INFO_SIZE + ((oq) * CN23XX_VF_OQ_OFFSET))
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#define CN23XX_VF_SLI_OQ_PKTS_SENT(oq) \
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(CN23XX_VF_SLI_OQ_PKT_SENT_START + ((oq) * CN23XX_VF_OQ_OFFSET))
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#define CN23XX_VF_SLI_OQ_PKTS_CREDIT(oq) \
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(CN23XX_VF_SLI_OQ_PKT_CREDITS_START + ((oq) * CN23XX_VF_OQ_OFFSET))
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#define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(oq) \
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(CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_START64 + ((oq) * CN23XX_VF_OQ_OFFSET))
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/* Macro's for accessing CNT and TIME separately from INT_LEVELS */
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#define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_CNT(oq) \
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(CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_START64 + ((oq) * CN23XX_VF_OQ_OFFSET))
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#define CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_TIME(oq) \
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(CN23XX_VF_SLI_OQ_PKT_INT_LEVELS_START64 + \
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((oq) * CN23XX_VF_OQ_OFFSET) + 4)
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/*------------------ Masks ----------------*/
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#define CN23XX_PKT_OUTPUT_CTL_TENB BIT(13)
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#define CN23XX_PKT_OUTPUT_CTL_CENB BIT(12)
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#define CN23XX_PKT_OUTPUT_CTL_IPTR BIT(11)
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#define CN23XX_PKT_OUTPUT_CTL_ES BIT(9)
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#define CN23XX_PKT_OUTPUT_CTL_NSR BIT(8)
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#define CN23XX_PKT_OUTPUT_CTL_ROR BIT(7)
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#define CN23XX_PKT_OUTPUT_CTL_DPTR BIT(6)
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#define CN23XX_PKT_OUTPUT_CTL_BMODE BIT(5)
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#define CN23XX_PKT_OUTPUT_CTL_ES_P BIT(3)
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#define CN23XX_PKT_OUTPUT_CTL_NSR_P BIT(2)
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#define CN23XX_PKT_OUTPUT_CTL_ROR_P BIT(1)
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#define CN23XX_PKT_OUTPUT_CTL_RING_ENB BIT(0)
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/*######################### Mailbox Reg Macros ########################*/
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#define CN23XX_VF_SLI_PKT_MBOX_INT_START 0x10210
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#define CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START 0x10200
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#define CN23XX_SLI_MBOX_OFFSET 0x20000
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#define CN23XX_SLI_MBOX_SIG_IDX_OFFSET 0x8
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#define CN23XX_VF_SLI_PKT_MBOX_INT(q) \
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(CN23XX_VF_SLI_PKT_MBOX_INT_START + ((q) * CN23XX_SLI_MBOX_OFFSET))
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#define CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q, idx) \
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(CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START + \
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((q) * CN23XX_SLI_MBOX_OFFSET + \
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(idx) * CN23XX_SLI_MBOX_SIG_IDX_OFFSET))
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/*######################## INTERRUPTS #########################*/
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#define CN23XX_VF_SLI_INT_SUM_START 0x100D0
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#define CN23XX_VF_SLI_INT_SUM(q) \
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(CN23XX_VF_SLI_INT_SUM_START + ((q) * CN23XX_VF_IQ_OFFSET))
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/*------------------ Interrupt Masks ----------------*/
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#define CN23XX_INTR_PO_INT BIT_ULL(63)
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#define CN23XX_INTR_PI_INT BIT_ULL(62)
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#define CN23XX_INTR_MBOX_INT BIT_ULL(61)
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#define CN23XX_INTR_RESEND BIT_ULL(60)
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#define CN23XX_INTR_CINT_ENB BIT_ULL(48)
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#define CN23XX_INTR_MBOX_ENB BIT(0)
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/*############################ MIO #########################*/
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#define CN23XX_MIO_PTP_CLOCK_CFG 0x0001070000000f00ULL
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#define CN23XX_MIO_PTP_CLOCK_LO 0x0001070000000f08ULL
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#define CN23XX_MIO_PTP_CLOCK_HI 0x0001070000000f10ULL
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#define CN23XX_MIO_PTP_CLOCK_COMP 0x0001070000000f18ULL
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#define CN23XX_MIO_PTP_TIMESTAMP 0x0001070000000f20ULL
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#define CN23XX_MIO_PTP_EVT_CNT 0x0001070000000f28ULL
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#define CN23XX_MIO_PTP_CKOUT_THRESH_LO 0x0001070000000f30ULL
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#define CN23XX_MIO_PTP_CKOUT_THRESH_HI 0x0001070000000f38ULL
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#define CN23XX_MIO_PTP_CKOUT_HI_INCR 0x0001070000000f40ULL
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#define CN23XX_MIO_PTP_CKOUT_LO_INCR 0x0001070000000f48ULL
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#define CN23XX_MIO_PTP_PPS_THRESH_LO 0x0001070000000f50ULL
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#define CN23XX_MIO_PTP_PPS_THRESH_HI 0x0001070000000f58ULL
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#define CN23XX_MIO_PTP_PPS_HI_INCR 0x0001070000000f60ULL
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#define CN23XX_MIO_PTP_PPS_LO_INCR 0x0001070000000f68ULL
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/*############################ RST #########################*/
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#define CN23XX_RST_BOOT 0x0001180006001600ULL
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/*######################## MSIX TABLE #########################*/
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#define CN23XX_MSIX_TABLE_ADDR_START 0x0
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#define CN23XX_MSIX_TABLE_DATA_START 0x8
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#define CN23XX_MSIX_TABLE_SIZE 0x10
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#define CN23XX_MSIX_TABLE_ENTRIES 0x41
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#define CN23XX_MSIX_ENTRY_VECTOR_CTL BIT_ULL(32)
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#define CN23XX_MSIX_TABLE_ADDR(idx) \
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(CN23XX_MSIX_TABLE_ADDR_START + ((idx) * CN23XX_MSIX_TABLE_SIZE))
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#define CN23XX_MSIX_TABLE_DATA(idx) \
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(CN23XX_MSIX_TABLE_DATA_START + ((idx) * CN23XX_MSIX_TABLE_SIZE))
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#endif
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