// SPDX-License-Identifier: GPL-2.0-or-later
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/* Applied Micro X-Gene SoC Ethernet Driver
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*
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* Copyright (c) 2015, Applied Micro Circuits Corporation
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* Author: Iyappan Subramanian <isubramanian@apm.com>
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*/
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#include "xgene_enet_main.h"
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#include "xgene_enet_hw.h"
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#include "xgene_enet_ring2.h"
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static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring)
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{
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u32 *ring_cfg = ring->state;
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u64 addr = ring->dma;
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if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU) {
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ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK);
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ring_cfg[3] |= SET_BIT(X2_DEQINTEN);
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}
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ring_cfg[0] |= SET_VAL(X2_CFGCRID, 2);
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addr >>= 8;
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ring_cfg[2] |= QCOHERENT | SET_VAL(RINGADDRL, addr);
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addr >>= 27;
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ring_cfg[3] |= SET_VAL(RINGSIZE, ring->cfgsize)
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| ACCEPTLERR
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| SET_VAL(RINGADDRH, addr);
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ring_cfg[4] |= SET_VAL(X2_SELTHRSH, 1);
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ring_cfg[5] |= SET_BIT(X2_QBASE_AM) | SET_BIT(X2_MSG_AM);
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}
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static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring)
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{
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u32 *ring_cfg = ring->state;
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bool is_bufpool;
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u32 val;
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is_bufpool = xgene_enet_is_bufpool(ring->id);
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val = (is_bufpool) ? RING_BUFPOOL : RING_REGULAR;
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ring_cfg[4] |= SET_VAL(X2_RINGTYPE, val);
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if (is_bufpool)
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ring_cfg[3] |= SET_VAL(RINGMODE, BUFPOOL_MODE);
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}
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static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring *ring)
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{
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u32 *ring_cfg = ring->state;
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ring_cfg[3] |= RECOMBBUF;
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ring_cfg[4] |= SET_VAL(X2_RECOMTIMEOUT, 0x7);
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}
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static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring *ring,
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u32 offset, u32 data)
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{
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struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
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iowrite32(data, pdata->ring_csr_addr + offset);
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}
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static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring *ring)
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{
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struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
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int i;
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xgene_enet_ring_wr32(ring, CSR_RING_CONFIG, ring->num);
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for (i = 0; i < pdata->ring_ops->num_ring_config; i++) {
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xgene_enet_ring_wr32(ring, CSR_RING_WR_BASE + (i * 4),
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ring->state[i]);
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}
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}
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static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring *ring)
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{
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memset(ring->state, 0, sizeof(ring->state));
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xgene_enet_write_ring_state(ring);
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}
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static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring)
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{
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enum xgene_ring_owner owner;
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xgene_enet_ring_set_type(ring);
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owner = xgene_enet_ring_owner(ring->id);
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if (owner == RING_OWNER_ETH0 || owner == RING_OWNER_ETH1)
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xgene_enet_ring_set_recombbuf(ring);
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xgene_enet_ring_init(ring);
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xgene_enet_write_ring_state(ring);
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}
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static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring)
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{
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u32 ring_id_val, ring_id_buf;
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bool is_bufpool;
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if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)
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return;
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is_bufpool = xgene_enet_is_bufpool(ring->id);
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ring_id_val = ring->id & GENMASK(9, 0);
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ring_id_val |= OVERWRITE;
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ring_id_buf = (ring->num << 9) & GENMASK(18, 9);
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ring_id_buf |= PREFETCH_BUF_EN;
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if (is_bufpool)
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ring_id_buf |= IS_BUFFER_POOL;
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xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id_val);
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xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, ring_id_buf);
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}
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static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring *ring)
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{
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u32 ring_id;
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ring_id = ring->id | OVERWRITE;
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xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id);
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xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, 0);
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}
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static struct xgene_enet_desc_ring *xgene_enet_setup_ring(
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struct xgene_enet_desc_ring *ring)
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{
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bool is_bufpool;
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u32 addr, i;
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xgene_enet_clr_ring_state(ring);
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xgene_enet_set_ring_state(ring);
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xgene_enet_set_ring_id(ring);
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ring->slots = xgene_enet_get_numslots(ring->id, ring->size);
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is_bufpool = xgene_enet_is_bufpool(ring->id);
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if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
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return ring;
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addr = CSR_VMID0_INTR_MBOX + (4 * (ring->id & RING_BUFNUM_MASK));
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xgene_enet_ring_wr32(ring, addr, ring->irq_mbox_dma >> 10);
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for (i = 0; i < ring->slots; i++)
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xgene_enet_mark_desc_slot_empty(&ring->raw_desc[i]);
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return ring;
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}
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static void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring)
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{
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xgene_enet_clr_desc_ring_id(ring);
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xgene_enet_clr_ring_state(ring);
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}
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static void xgene_enet_wr_cmd(struct xgene_enet_desc_ring *ring, int count)
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{
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u32 data = 0;
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if (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU) {
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data = SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK) |
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INTR_CLEAR;
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}
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data |= (count & GENMASK(16, 0));
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iowrite32(data, ring->cmd);
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}
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static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring)
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{
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u32 __iomem *cmd_base = ring->cmd_base;
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u32 ring_state, num_msgs;
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ring_state = ioread32(&cmd_base[1]);
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num_msgs = GET_VAL(X2_NUMMSGSINQ, ring_state);
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return num_msgs;
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}
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static void xgene_enet_setup_coalescing(struct xgene_enet_desc_ring *ring)
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{
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u32 data = 0x77777777;
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xgene_enet_ring_wr32(ring, CSR_PBM_COAL, 0x8e);
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xgene_enet_ring_wr32(ring, CSR_PBM_CTICK0, data);
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xgene_enet_ring_wr32(ring, CSR_PBM_CTICK1, data);
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xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data);
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xgene_enet_ring_wr32(ring, CSR_PBM_CTICK3, data);
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xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x08);
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xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x10);
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}
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struct xgene_ring_ops xgene_ring2_ops = {
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.num_ring_config = X2_NUM_RING_CONFIG,
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.num_ring_id_shift = 13,
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.setup = xgene_enet_setup_ring,
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.clear = xgene_enet_clear_ring,
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.wr_cmd = xgene_enet_wr_cmd,
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.len = xgene_enet_ring_len,
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.coalesce = xgene_enet_setup_coalescing,
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};
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