// SPDX-License-Identifier: GPL-2.0-or-later
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/* Applied Micro X-Gene SoC Ethernet Classifier structures
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*
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* Copyright (c) 2016, Applied Micro Circuits Corporation
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* Authors: Khuong Dinh <kdinh@apm.com>
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* Tanmay Inamdar <tinamdar@apm.com>
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* Iyappan Subramanian <isubramanian@apm.com>
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*/
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#include "xgene_enet_main.h"
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/* interfaces to convert structures to HW recognized bit formats */
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static void xgene_cle_sband_to_hw(u8 frag, enum xgene_cle_prot_version ver,
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enum xgene_cle_prot_type type, u32 len,
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u32 *reg)
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{
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*reg = SET_VAL(SB_IPFRAG, frag) |
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SET_VAL(SB_IPPROT, type) |
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SET_VAL(SB_IPVER, ver) |
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SET_VAL(SB_HDRLEN, len);
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}
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static void xgene_cle_idt_to_hw(struct xgene_enet_pdata *pdata,
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u32 dstqid, u32 fpsel,
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u32 nfpsel, u32 *idt_reg)
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{
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if (pdata->enet_id == XGENE_ENET1) {
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*idt_reg = SET_VAL(IDT_DSTQID, dstqid) |
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SET_VAL(IDT_FPSEL1, fpsel) |
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SET_VAL(IDT_NFPSEL1, nfpsel);
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} else {
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*idt_reg = SET_VAL(IDT_DSTQID, dstqid) |
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SET_VAL(IDT_FPSEL, fpsel) |
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SET_VAL(IDT_NFPSEL, nfpsel);
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}
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}
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static void xgene_cle_dbptr_to_hw(struct xgene_enet_pdata *pdata,
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struct xgene_cle_dbptr *dbptr, u32 *buf)
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{
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buf[0] = SET_VAL(CLE_DROP, dbptr->drop);
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buf[4] = SET_VAL(CLE_FPSEL, dbptr->fpsel) |
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SET_VAL(CLE_NFPSEL, dbptr->nxtfpsel) |
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SET_VAL(CLE_DSTQIDL, dbptr->dstqid);
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buf[5] = SET_VAL(CLE_DSTQIDH, (u32)dbptr->dstqid >> CLE_DSTQIDL_LEN) |
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SET_VAL(CLE_PRIORITY, dbptr->cle_priority);
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}
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static void xgene_cle_kn_to_hw(struct xgene_cle_ptree_kn *kn, u32 *buf)
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{
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u32 i, j = 0;
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u32 data;
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buf[j++] = SET_VAL(CLE_TYPE, kn->node_type);
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for (i = 0; i < kn->num_keys; i++) {
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struct xgene_cle_ptree_key *key = &kn->key[i];
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if (!(i % 2)) {
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buf[j] = SET_VAL(CLE_KN_PRIO, key->priority) |
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SET_VAL(CLE_KN_RPTR, key->result_pointer);
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} else {
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data = SET_VAL(CLE_KN_PRIO, key->priority) |
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SET_VAL(CLE_KN_RPTR, key->result_pointer);
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buf[j++] |= (data << 16);
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}
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}
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}
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static void xgene_cle_dn_to_hw(const struct xgene_cle_ptree_ewdn *dn,
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u32 *buf, u32 jb)
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{
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const struct xgene_cle_ptree_branch *br;
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u32 i, j = 0;
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u32 npp;
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buf[j++] = SET_VAL(CLE_DN_TYPE, dn->node_type) |
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SET_VAL(CLE_DN_LASTN, dn->last_node) |
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SET_VAL(CLE_DN_HLS, dn->hdr_len_store) |
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SET_VAL(CLE_DN_EXT, dn->hdr_extn) |
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SET_VAL(CLE_DN_BSTOR, dn->byte_store) |
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SET_VAL(CLE_DN_SBSTOR, dn->search_byte_store) |
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SET_VAL(CLE_DN_RPTR, dn->result_pointer);
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for (i = 0; i < dn->num_branches; i++) {
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br = &dn->branch[i];
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npp = br->next_packet_pointer;
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if ((br->jump_rel == JMP_ABS) && (npp < CLE_PKTRAM_SIZE))
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npp += jb;
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buf[j++] = SET_VAL(CLE_BR_VALID, br->valid) |
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SET_VAL(CLE_BR_NPPTR, npp) |
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SET_VAL(CLE_BR_JB, br->jump_bw) |
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SET_VAL(CLE_BR_JR, br->jump_rel) |
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SET_VAL(CLE_BR_OP, br->operation) |
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SET_VAL(CLE_BR_NNODE, br->next_node) |
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SET_VAL(CLE_BR_NBR, br->next_branch);
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buf[j++] = SET_VAL(CLE_BR_DATA, br->data) |
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SET_VAL(CLE_BR_MASK, br->mask);
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}
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}
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static int xgene_cle_poll_cmd_done(void __iomem *base,
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enum xgene_cle_cmd_type cmd)
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{
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u32 status, loop = 10;
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int ret = -EBUSY;
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while (loop--) {
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status = ioread32(base + INDCMD_STATUS);
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if (status & cmd) {
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ret = 0;
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break;
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}
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usleep_range(1000, 2000);
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}
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return ret;
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}
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static int xgene_cle_dram_wr(struct xgene_enet_cle *cle, u32 *data, u8 nregs,
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u32 index, enum xgene_cle_dram_type type,
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enum xgene_cle_cmd_type cmd)
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{
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enum xgene_cle_parser parser = cle->active_parser;
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void __iomem *base = cle->base;
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u32 i, j, ind_addr;
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u8 port, nparsers;
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int ret = 0;
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/* PTREE_RAM onwards, DRAM regions are common for all parsers */
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nparsers = (type >= PTREE_RAM) ? 1 : cle->parsers;
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for (i = 0; i < nparsers; i++) {
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port = i;
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if ((type < PTREE_RAM) && (parser != PARSER_ALL))
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port = parser;
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ind_addr = XGENE_CLE_DRAM(type + (port * 4)) | index;
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iowrite32(ind_addr, base + INDADDR);
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for (j = 0; j < nregs; j++)
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iowrite32(data[j], base + DATA_RAM0 + (j * 4));
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iowrite32(cmd, base + INDCMD);
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ret = xgene_cle_poll_cmd_done(base, cmd);
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if (ret)
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break;
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}
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return ret;
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}
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static void xgene_cle_enable_ptree(struct xgene_enet_pdata *pdata,
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struct xgene_enet_cle *cle)
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{
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struct xgene_cle_ptree *ptree = &cle->ptree;
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void __iomem *addr, *base = cle->base;
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u32 offset = CLE_PORT_OFFSET;
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u32 i;
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/* 1G port has to advance 4 bytes and 10G has to advance 8 bytes */
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ptree->start_pkt += cle->jump_bytes;
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for (i = 0; i < cle->parsers; i++) {
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if (cle->active_parser != PARSER_ALL)
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addr = base + cle->active_parser * offset;
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else
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addr = base + (i * offset);
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iowrite32(ptree->start_node & 0x3fff, addr + SNPTR0);
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iowrite32(ptree->start_pkt & 0x1ff, addr + SPPTR0);
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}
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}
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static int xgene_cle_setup_dbptr(struct xgene_enet_pdata *pdata,
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struct xgene_enet_cle *cle)
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{
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struct xgene_cle_ptree *ptree = &cle->ptree;
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u32 buf[CLE_DRAM_REGS];
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u32 i;
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int ret;
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memset(buf, 0, sizeof(buf));
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for (i = 0; i < ptree->num_dbptr; i++) {
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xgene_cle_dbptr_to_hw(pdata, &ptree->dbptr[i], buf);
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ret = xgene_cle_dram_wr(cle, buf, 6, i + ptree->start_dbptr,
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DB_RAM, CLE_CMD_WR);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const struct xgene_cle_ptree_ewdn xgene_init_ptree_dn[] = {
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{
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/* PKT_TYPE_NODE */
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.node_type = EWDN,
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.last_node = 0,
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.hdr_len_store = 1,
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.hdr_extn = NO_BYTE,
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.byte_store = NO_BYTE,
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.search_byte_store = NO_BYTE,
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.result_pointer = DB_RES_DROP,
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.num_branches = 2,
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.branch = {
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{
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/* IPV4 */
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.valid = 1,
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.next_packet_pointer = 22,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = PKT_PROT_NODE,
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.next_branch = 0,
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.data = 0x8,
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.mask = 0x0
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},
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{
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.valid = 0,
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.next_packet_pointer = 262,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = LAST_NODE,
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.next_branch = 0,
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.data = 0x0,
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.mask = 0xffff
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}
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},
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},
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{
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/* PKT_PROT_NODE */
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.node_type = EWDN,
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.last_node = 0,
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.hdr_len_store = 1,
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.hdr_extn = NO_BYTE,
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.byte_store = NO_BYTE,
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.search_byte_store = NO_BYTE,
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.result_pointer = DB_RES_DROP,
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.num_branches = 3,
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.branch = {
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{
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/* TCP */
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.valid = 1,
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.next_packet_pointer = 26,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_TCP_NODE,
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.next_branch = 0,
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.data = 0x0600,
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.mask = 0x00ff
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},
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{
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/* UDP */
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.valid = 1,
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.next_packet_pointer = 26,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_UDP_NODE,
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.next_branch = 0,
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.data = 0x1100,
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.mask = 0x00ff
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},
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{
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.valid = 0,
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.next_packet_pointer = 26,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_OTHERS_NODE,
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.next_branch = 0,
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.data = 0x0,
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.mask = 0xffff
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}
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}
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},
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{
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/* RSS_IPV4_TCP_NODE */
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.node_type = EWDN,
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.last_node = 0,
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.hdr_len_store = 1,
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.hdr_extn = NO_BYTE,
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.byte_store = NO_BYTE,
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.search_byte_store = BOTH_BYTES,
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.result_pointer = DB_RES_DROP,
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.num_branches = 6,
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.branch = {
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{
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/* SRC IPV4 B01 */
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.valid = 0,
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.next_packet_pointer = 28,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_TCP_NODE,
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.next_branch = 1,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* SRC IPV4 B23 */
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.valid = 0,
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.next_packet_pointer = 30,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_TCP_NODE,
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.next_branch = 2,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* DST IPV4 B01 */
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.valid = 0,
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.next_packet_pointer = 32,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_TCP_NODE,
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.next_branch = 3,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* DST IPV4 B23 */
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.valid = 0,
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.next_packet_pointer = 34,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_TCP_NODE,
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.next_branch = 4,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* TCP SRC Port */
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.valid = 0,
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.next_packet_pointer = 36,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_TCP_NODE,
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.next_branch = 5,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* TCP DST Port */
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.valid = 0,
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.next_packet_pointer = 256,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = LAST_NODE,
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.next_branch = 0,
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.data = 0x0,
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.mask = 0xffff
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}
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}
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},
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{
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/* RSS_IPV4_UDP_NODE */
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.node_type = EWDN,
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.last_node = 0,
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.hdr_len_store = 1,
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.hdr_extn = NO_BYTE,
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.byte_store = NO_BYTE,
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.search_byte_store = BOTH_BYTES,
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.result_pointer = DB_RES_DROP,
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.num_branches = 6,
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.branch = {
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{
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/* SRC IPV4 B01 */
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.valid = 0,
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.next_packet_pointer = 28,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_UDP_NODE,
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.next_branch = 1,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* SRC IPV4 B23 */
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.valid = 0,
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.next_packet_pointer = 30,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_UDP_NODE,
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.next_branch = 2,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* DST IPV4 B01 */
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.valid = 0,
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.next_packet_pointer = 32,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_UDP_NODE,
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.next_branch = 3,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* DST IPV4 B23 */
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.valid = 0,
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.next_packet_pointer = 34,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_UDP_NODE,
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.next_branch = 4,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* TCP SRC Port */
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.valid = 0,
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.next_packet_pointer = 36,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_UDP_NODE,
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.next_branch = 5,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* TCP DST Port */
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.valid = 0,
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.next_packet_pointer = 258,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = LAST_NODE,
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.next_branch = 0,
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.data = 0x0,
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.mask = 0xffff
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}
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}
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},
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{
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/* RSS_IPV4_OTHERS_NODE */
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.node_type = EWDN,
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.last_node = 0,
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.hdr_len_store = 1,
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.hdr_extn = NO_BYTE,
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.byte_store = NO_BYTE,
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.search_byte_store = BOTH_BYTES,
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.result_pointer = DB_RES_DROP,
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.num_branches = 6,
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.branch = {
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{
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/* SRC IPV4 B01 */
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.valid = 0,
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.next_packet_pointer = 28,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_OTHERS_NODE,
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.next_branch = 1,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* SRC IPV4 B23 */
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.valid = 0,
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.next_packet_pointer = 30,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_OTHERS_NODE,
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.next_branch = 2,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* DST IPV4 B01 */
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.valid = 0,
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.next_packet_pointer = 32,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_OTHERS_NODE,
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.next_branch = 3,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* DST IPV4 B23 */
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.valid = 0,
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.next_packet_pointer = 34,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_OTHERS_NODE,
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.next_branch = 4,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* TCP SRC Port */
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.valid = 0,
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.next_packet_pointer = 36,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = RSS_IPV4_OTHERS_NODE,
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.next_branch = 5,
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.data = 0x0,
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.mask = 0xffff
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},
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{
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/* TCP DST Port */
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.valid = 0,
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.next_packet_pointer = 260,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
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.operation = EQT,
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.next_node = LAST_NODE,
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.next_branch = 0,
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.data = 0x0,
|
.mask = 0xffff
|
}
|
}
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},
|
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{
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/* LAST NODE */
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.node_type = EWDN,
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.last_node = 1,
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.hdr_len_store = 1,
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.hdr_extn = NO_BYTE,
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.byte_store = NO_BYTE,
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.search_byte_store = NO_BYTE,
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.result_pointer = DB_RES_DROP,
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.num_branches = 1,
|
.branch = {
|
{
|
.valid = 0,
|
.next_packet_pointer = 0,
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.jump_bw = JMP_FW,
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.jump_rel = JMP_ABS,
|
.operation = EQT,
|
.next_node = MAX_NODES,
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.next_branch = 0,
|
.data = 0,
|
.mask = 0xffff
|
}
|
}
|
}
|
};
|
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static int xgene_cle_setup_node(struct xgene_enet_pdata *pdata,
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struct xgene_enet_cle *cle)
|
{
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struct xgene_cle_ptree *ptree = &cle->ptree;
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const struct xgene_cle_ptree_ewdn *dn = xgene_init_ptree_dn;
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int num_dn = ARRAY_SIZE(xgene_init_ptree_dn);
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struct xgene_cle_ptree_kn *kn = ptree->kn;
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u32 buf[CLE_DRAM_REGS];
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int i, j, ret;
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memset(buf, 0, sizeof(buf));
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for (i = 0; i < num_dn; i++) {
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xgene_cle_dn_to_hw(&dn[i], buf, cle->jump_bytes);
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ret = xgene_cle_dram_wr(cle, buf, 17, i + ptree->start_node,
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PTREE_RAM, CLE_CMD_WR);
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if (ret)
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return ret;
|
}
|
|
/* continue node index for key node */
|
memset(buf, 0, sizeof(buf));
|
for (j = i; j < (ptree->num_kn + num_dn); j++) {
|
xgene_cle_kn_to_hw(&kn[j - num_dn], buf);
|
ret = xgene_cle_dram_wr(cle, buf, 17, j + ptree->start_node,
|
PTREE_RAM, CLE_CMD_WR);
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if (ret)
|
return ret;
|
}
|
|
return 0;
|
}
|
|
static int xgene_cle_setup_ptree(struct xgene_enet_pdata *pdata,
|
struct xgene_enet_cle *cle)
|
{
|
int ret;
|
|
ret = xgene_cle_setup_node(pdata, cle);
|
if (ret)
|
return ret;
|
|
ret = xgene_cle_setup_dbptr(pdata, cle);
|
if (ret)
|
return ret;
|
|
xgene_cle_enable_ptree(pdata, cle);
|
|
return 0;
|
}
|
|
static void xgene_cle_setup_def_dbptr(struct xgene_enet_pdata *pdata,
|
struct xgene_enet_cle *enet_cle,
|
struct xgene_cle_dbptr *dbptr,
|
u32 index, u8 priority)
|
{
|
void __iomem *base = enet_cle->base;
|
void __iomem *base_addr;
|
u32 buf[CLE_DRAM_REGS];
|
u32 def_cls, offset;
|
u32 i, j;
|
|
memset(buf, 0, sizeof(buf));
|
xgene_cle_dbptr_to_hw(pdata, dbptr, buf);
|
|
for (i = 0; i < enet_cle->parsers; i++) {
|
if (enet_cle->active_parser != PARSER_ALL) {
|
offset = enet_cle->active_parser *
|
CLE_PORT_OFFSET;
|
} else {
|
offset = i * CLE_PORT_OFFSET;
|
}
|
|
base_addr = base + DFCLSRESDB00 + offset;
|
for (j = 0; j < 6; j++)
|
iowrite32(buf[j], base_addr + (j * 4));
|
|
def_cls = ((priority & 0x7) << 10) | (index & 0x3ff);
|
iowrite32(def_cls, base + DFCLSRESDBPTR0 + offset);
|
}
|
}
|
|
static int xgene_cle_set_rss_sband(struct xgene_enet_cle *cle)
|
{
|
u32 idx = CLE_PKTRAM_SIZE / sizeof(u32);
|
u32 mac_hdr_len = ETH_HLEN;
|
u32 sband, reg = 0;
|
u32 ipv4_ihl = 5;
|
u32 hdr_len;
|
int ret;
|
|
/* Sideband: IPV4/TCP packets */
|
hdr_len = (mac_hdr_len << 5) | ipv4_ihl;
|
xgene_cle_sband_to_hw(0, XGENE_CLE_IPV4, XGENE_CLE_TCP, hdr_len, ®);
|
sband = reg;
|
|
/* Sideband: IPv4/UDP packets */
|
hdr_len = (mac_hdr_len << 5) | ipv4_ihl;
|
xgene_cle_sband_to_hw(1, XGENE_CLE_IPV4, XGENE_CLE_UDP, hdr_len, ®);
|
sband |= (reg << 16);
|
|
ret = xgene_cle_dram_wr(cle, &sband, 1, idx, PKT_RAM, CLE_CMD_WR);
|
if (ret)
|
return ret;
|
|
/* Sideband: IPv4/RAW packets */
|
hdr_len = (mac_hdr_len << 5) | ipv4_ihl;
|
xgene_cle_sband_to_hw(0, XGENE_CLE_IPV4, XGENE_CLE_OTHER,
|
hdr_len, ®);
|
sband = reg;
|
|
/* Sideband: Ethernet II/RAW packets */
|
hdr_len = (mac_hdr_len << 5);
|
xgene_cle_sband_to_hw(0, XGENE_CLE_IPV4, XGENE_CLE_OTHER,
|
hdr_len, ®);
|
sband |= (reg << 16);
|
|
ret = xgene_cle_dram_wr(cle, &sband, 1, idx + 1, PKT_RAM, CLE_CMD_WR);
|
if (ret)
|
return ret;
|
|
return 0;
|
}
|
|
static int xgene_cle_set_rss_skeys(struct xgene_enet_cle *cle)
|
{
|
u32 secret_key_ipv4[4]; /* 16 Bytes*/
|
int ret = 0;
|
|
get_random_bytes(secret_key_ipv4, 16);
|
ret = xgene_cle_dram_wr(cle, secret_key_ipv4, 4, 0,
|
RSS_IPV4_HASH_SKEY, CLE_CMD_WR);
|
return ret;
|
}
|
|
static int xgene_cle_set_rss_idt(struct xgene_enet_pdata *pdata)
|
{
|
u32 fpsel, dstqid, nfpsel, idt_reg, idx;
|
int i, ret = 0;
|
u16 pool_id;
|
|
for (i = 0; i < XGENE_CLE_IDT_ENTRIES; i++) {
|
idx = i % pdata->rxq_cnt;
|
pool_id = pdata->rx_ring[idx]->buf_pool->id;
|
fpsel = xgene_enet_get_fpsel(pool_id);
|
dstqid = xgene_enet_dst_ring_num(pdata->rx_ring[idx]);
|
nfpsel = 0;
|
if (pdata->rx_ring[idx]->page_pool) {
|
pool_id = pdata->rx_ring[idx]->page_pool->id;
|
nfpsel = xgene_enet_get_fpsel(pool_id);
|
}
|
|
idt_reg = 0;
|
xgene_cle_idt_to_hw(pdata, dstqid, fpsel, nfpsel, &idt_reg);
|
ret = xgene_cle_dram_wr(&pdata->cle, &idt_reg, 1, i,
|
RSS_IDT, CLE_CMD_WR);
|
if (ret)
|
return ret;
|
}
|
|
ret = xgene_cle_set_rss_skeys(&pdata->cle);
|
if (ret)
|
return ret;
|
|
return 0;
|
}
|
|
static int xgene_cle_setup_rss(struct xgene_enet_pdata *pdata)
|
{
|
struct xgene_enet_cle *cle = &pdata->cle;
|
void __iomem *base = cle->base;
|
u32 offset, val = 0;
|
int i, ret = 0;
|
|
offset = CLE_PORT_OFFSET;
|
for (i = 0; i < cle->parsers; i++) {
|
if (cle->active_parser != PARSER_ALL)
|
offset = cle->active_parser * CLE_PORT_OFFSET;
|
else
|
offset = i * CLE_PORT_OFFSET;
|
|
/* enable RSS */
|
val = (RSS_IPV4_12B << 1) | 0x1;
|
writel(val, base + RSS_CTRL0 + offset);
|
}
|
|
/* setup sideband data */
|
ret = xgene_cle_set_rss_sband(cle);
|
if (ret)
|
return ret;
|
|
/* setup indirection table */
|
ret = xgene_cle_set_rss_idt(pdata);
|
if (ret)
|
return ret;
|
|
return 0;
|
}
|
|
static int xgene_enet_cle_init(struct xgene_enet_pdata *pdata)
|
{
|
struct xgene_enet_cle *enet_cle = &pdata->cle;
|
u32 def_qid, def_fpsel, def_nxtfpsel, pool_id;
|
struct xgene_cle_dbptr dbptr[DB_MAX_PTRS];
|
struct xgene_cle_ptree *ptree;
|
struct xgene_cle_ptree_kn kn;
|
int ret;
|
|
if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII)
|
return -EINVAL;
|
|
ptree = &enet_cle->ptree;
|
ptree->start_pkt = 12; /* Ethertype */
|
|
ret = xgene_cle_setup_rss(pdata);
|
if (ret) {
|
netdev_err(pdata->ndev, "RSS initialization failed\n");
|
return ret;
|
}
|
|
def_qid = xgene_enet_dst_ring_num(pdata->rx_ring[0]);
|
pool_id = pdata->rx_ring[0]->buf_pool->id;
|
def_fpsel = xgene_enet_get_fpsel(pool_id);
|
def_nxtfpsel = 0;
|
if (pdata->rx_ring[0]->page_pool) {
|
pool_id = pdata->rx_ring[0]->page_pool->id;
|
def_nxtfpsel = xgene_enet_get_fpsel(pool_id);
|
}
|
|
memset(dbptr, 0, sizeof(struct xgene_cle_dbptr) * DB_MAX_PTRS);
|
dbptr[DB_RES_ACCEPT].fpsel = def_fpsel;
|
dbptr[DB_RES_ACCEPT].nxtfpsel = def_nxtfpsel;
|
dbptr[DB_RES_ACCEPT].dstqid = def_qid;
|
dbptr[DB_RES_ACCEPT].cle_priority = 1;
|
|
dbptr[DB_RES_DEF].fpsel = def_fpsel;
|
dbptr[DB_RES_DEF].nxtfpsel = def_nxtfpsel;
|
dbptr[DB_RES_DEF].dstqid = def_qid;
|
dbptr[DB_RES_DEF].cle_priority = 7;
|
xgene_cle_setup_def_dbptr(pdata, enet_cle, &dbptr[DB_RES_DEF],
|
DB_RES_ACCEPT, 7);
|
|
dbptr[DB_RES_DROP].drop = 1;
|
|
memset(&kn, 0, sizeof(kn));
|
kn.node_type = KN;
|
kn.num_keys = 1;
|
kn.key[0].priority = 0;
|
kn.key[0].result_pointer = DB_RES_ACCEPT;
|
|
ptree->kn = &kn;
|
ptree->dbptr = dbptr;
|
ptree->num_kn = 1;
|
ptree->num_dbptr = DB_MAX_PTRS;
|
|
return xgene_cle_setup_ptree(pdata, enet_cle);
|
}
|
|
const struct xgene_cle_ops xgene_cle3in_ops = {
|
.cle_init = xgene_enet_cle_init,
|
};
|
