/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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*
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* Alchemy Au1x00 ethernet driver include file
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*
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* Author: Pete Popov <ppopov@mvista.com>
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*
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* Copyright 2001 MontaVista Software Inc.
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*/
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#define MAC_IOSIZE 0x10000
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#define NUM_RX_DMA 4 /* Au1x00 has 4 rx hardware descriptors */
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#define NUM_TX_DMA 4 /* Au1x00 has 4 tx hardware descriptors */
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#define NUM_RX_BUFFS 4
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#define NUM_TX_BUFFS 4
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#define MAX_BUF_SIZE 2048
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#define ETH_TX_TIMEOUT (HZ/4)
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#define MAC_MIN_PKT_SIZE 64
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#define MULTICAST_FILTER_LIMIT 64
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/*
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* Data Buffer Descriptor. Data buffers must be aligned on 32 byte
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* boundary for both, receive and transmit.
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*/
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struct db_dest {
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struct db_dest *pnext;
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u32 *vaddr;
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dma_addr_t dma_addr;
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};
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/*
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* The transmit and receive descriptors are memory
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* mapped registers.
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*/
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struct tx_dma {
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u32 status;
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u32 buff_stat;
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u32 len;
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u32 pad;
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};
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struct rx_dma {
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u32 status;
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u32 buff_stat;
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u32 pad[2];
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};
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/*
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* MAC control registers, memory mapped.
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*/
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struct mac_reg {
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u32 control;
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u32 mac_addr_high;
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u32 mac_addr_low;
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u32 multi_hash_high;
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u32 multi_hash_low;
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u32 mii_control;
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u32 mii_data;
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u32 flow_control;
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u32 vlan1_tag;
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u32 vlan2_tag;
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};
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struct au1000_private {
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struct db_dest *pDBfree;
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struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS];
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struct rx_dma *rx_dma_ring[NUM_RX_DMA];
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struct tx_dma *tx_dma_ring[NUM_TX_DMA];
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struct db_dest *rx_db_inuse[NUM_RX_DMA];
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struct db_dest *tx_db_inuse[NUM_TX_DMA];
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u32 rx_head;
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u32 tx_head;
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u32 tx_tail;
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u32 tx_full;
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int mac_id;
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int mac_enabled; /* whether MAC is currently enabled and running
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* (req. for mdio)
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*/
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int old_link; /* used by au1000_adjust_link */
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int old_speed;
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int old_duplex;
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struct mii_bus *mii_bus;
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/* PHY configuration */
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int phy_static_config;
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int phy_search_highest_addr;
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int phy1_search_mac0;
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int phy_addr;
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int phy_busid;
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int phy_irq;
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/* These variables are just for quick access
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* to certain regs addresses.
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*/
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struct mac_reg *mac; /* mac registers */
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u32 *enable; /* address of MAC Enable Register */
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void __iomem *macdma; /* base of MAC DMA port */
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u32 vaddr; /* virtual address of rx/tx buffers */
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dma_addr_t dma_addr; /* dma address of rx/tx buffers */
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spinlock_t lock; /* Serialise access to device */
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u32 msg_enable;
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};
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