// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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* Rockchip CAN driver
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*/
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#include <linux/module.h>
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#include <linux/uaccess.h>
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#include <linux/can.h>
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#include <linux/can/dev.h>
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#include <linux/can/error.h>
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#include <linux/can/led.h>
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#include <linux/clk.h>
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#include <linux/netdevice.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_device.h>
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#include <linux/reset.h>
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#include <linux/pm_runtime.h>
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#define DRV_NAME "rockchip_can"
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#define CAN_MODE 0x00
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#define RESET_MODE 0
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#define WORK_MODE BIT(0)
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#define SELF_TEST_EN BIT(2)
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#define MODE_AUTO_RETX BIT(10)
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#define CAN_CMD 0x04
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#define TX_REQ BIT(0)
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#define CAN_STATE 0x08
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#define RX_BUF_FULL BIT(0)
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#define TX_BUF_FULL BIT(1)
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#define RX_PERIOD BIT(2)
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#define TX_PERIOD BIT(3)
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#define ERR_WARN BIT(4)
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#define BUS_OFF BIT(5)
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#define CAN_INT 0x0C
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#define CAN_INT_MASK 0x10
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#define RX_FINISH BIT(0)
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#define TX_FINISH BIT(1)
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#define ERR_WARN_INT BIT(2)
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#define RX_BUF_OV BIT(3)
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#define PASSIVE_ERR BIT(4)
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#define TX_LOSTARB BIT(5)
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#define BUS_ERR_INT BIT(6)
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/* Bit Timing Register */
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#define CAN_BTT 0x18
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#define MODE_3_SAMPLES BIT(16)
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#define BT_SJW_SHIFT 14
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#define BT_SJW_MASK GENMASK(15, 14)
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#define BT_BRP_SHIFT 8
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#define BT_BRP_MASK GENMASK(13, 8)
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#define BT_TSEG2_SHIFT 4
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#define BT_TSEG2_MASK GENMASK(6, 4)
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#define BT_TSEG1_SHIFT 0
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#define BT_TSEG1_MASK GENMASK(3, 0)
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#define CAN_LOSTARB_CODE 0x28
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#define CAN_ERR_CODE 0x2c
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#define ERR_TYPE_MASK GENMASK(24, 22)
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#define ERR_TYPE_SHIFT 22
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#define BIT_ERR 0
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#define STUFF_ERR 1
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#define FORM_ERR 2
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#define ACK_ERR 3
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#define CRC_ERR 4
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#define ERR_DIR_RX BIT(21)
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#define ERR_LOC_MASK GENMASK(13, 0)
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#define CAN_RX_ERR_CNT 0x34
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#define CAN_TX_ERR_CNT 0x38
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#define CAN_ID 0x3c
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#define CAN_ID_MASK 0x40
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#define CAN_TX_FRM_INFO 0x50
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#define CAN_EFF BIT(7)
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#define CAN_RTR BIT(6)
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#define CAN_DLC_MASK GENMASK(3, 0)
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#define CAN_DLC(x) ((x) & GENMASK(3, 0))
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#define CAN_TX_ID 0x54
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#define CAN_TX_ID_MASK 0x1fffffff
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#define CAN_TX_DATA1 0x58
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#define CAN_TX_DATA2 0x5c
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#define CAN_RX_FRM_INFO 0x60
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#define CAN_RX_ID 0x64
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#define CAN_RX_DATA1 0x68
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#define CAN_RX_DATA2 0x6c
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#define CAN_RX_FILTER_MASK 0x1fffffff
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#define CAN_VERSION 0x70
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struct rockchip_can {
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struct can_priv can;
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void __iomem *base;
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struct device *dev;
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struct clk_bulk_data *clks;
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int num_clks;
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struct reset_control *reset;
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};
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static const struct can_bittiming_const rockchip_can_bittiming_const = {
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.name = DRV_NAME,
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.tseg1_min = 1,
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.tseg1_max = 16,
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.tseg2_min = 1,
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.tseg2_max = 8,
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.sjw_max = 4,
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.brp_min = 1,
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.brp_max = 128,
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.brp_inc = 2,
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};
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static void rockchip_can_write_cmdreg(struct rockchip_can *rcan, u8 val)
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{
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writel(val, rcan->base + CAN_CMD);
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}
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static int set_reset_mode(struct net_device *ndev)
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{
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struct rockchip_can *rcan = netdev_priv(ndev);
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reset_control_assert(rcan->reset);
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udelay(2);
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reset_control_deassert(rcan->reset);
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writel(0, rcan->base + CAN_MODE);
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return 0;
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}
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static int set_normal_mode(struct net_device *ndev)
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{
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struct rockchip_can *rcan = netdev_priv(ndev);
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u32 val;
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val = readl(rcan->base + CAN_MODE);
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val |= WORK_MODE | MODE_AUTO_RETX;
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writel(val, rcan->base + CAN_MODE);
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return 0;
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}
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/* bittiming is called in reset_mode only */
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static int rockchip_can_set_bittiming(struct net_device *ndev)
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{
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struct rockchip_can *rcan = netdev_priv(ndev);
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struct can_bittiming *bt = &rcan->can.bittiming;
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u32 cfg;
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cfg = ((bt->sjw - 1) << BT_SJW_SHIFT) |
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(((bt->brp >> 1) - 1) << BT_BRP_SHIFT) |
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((bt->phase_seg2 - 1) << BT_TSEG2_SHIFT) |
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((bt->prop_seg + bt->phase_seg1 - 1));
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if (rcan->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
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cfg |= MODE_3_SAMPLES;
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writel(cfg, rcan->base + CAN_BTT);
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netdev_dbg(ndev, "setting BITTIMING=0x%08x brp: %d bitrate:%d\n",
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cfg, bt->brp, bt->bitrate);
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return 0;
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}
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static int rockchip_can_get_berr_counter(const struct net_device *ndev,
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struct can_berr_counter *bec)
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{
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struct rockchip_can *rcan = netdev_priv(ndev);
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int err;
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err = pm_runtime_get_sync(rcan->dev);
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if (err < 0) {
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netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
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__func__, err);
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return err;
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}
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bec->rxerr = readl(rcan->base + CAN_RX_ERR_CNT);
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bec->txerr = readl(rcan->base + CAN_TX_ERR_CNT);
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pm_runtime_put(rcan->dev);
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netdev_dbg(ndev, "%s\n", __func__);
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return 0;
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}
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static int rockchip_can_start(struct net_device *ndev)
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{
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struct rockchip_can *rcan = netdev_priv(ndev);
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/* we need to enter the reset mode */
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set_reset_mode(ndev);
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writel(0, rcan->base + CAN_INT_MASK);
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/* RECEIVING FILTER, accept all */
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writel(0, rcan->base + CAN_ID);
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writel(CAN_RX_FILTER_MASK, rcan->base + CAN_ID_MASK);
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rockchip_can_set_bittiming(ndev);
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set_normal_mode(ndev);
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rcan->can.state = CAN_STATE_ERROR_ACTIVE;
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netdev_dbg(ndev, "%s\n", __func__);
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return 0;
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}
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static int rockchip_can_stop(struct net_device *ndev)
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{
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struct rockchip_can *rcan = netdev_priv(ndev);
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u32 val;
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rcan->can.state = CAN_STATE_STOPPED;
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/* we need to enter reset mode */
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set_reset_mode(ndev);
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/* disable all interrupts */
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val = RX_FINISH | TX_FINISH | ERR_WARN_INT |
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RX_BUF_OV | PASSIVE_ERR | TX_LOSTARB |
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BUS_ERR_INT;
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writel(val, rcan->base + CAN_INT_MASK);
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netdev_dbg(ndev, "%s\n", __func__);
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return 0;
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}
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static int rockchip_can_set_mode(struct net_device *ndev, enum can_mode mode)
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{
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int err;
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netdev_dbg(ndev, "can set mode: 0x%x\n", mode);
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switch (mode) {
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case CAN_MODE_START:
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err = rockchip_can_start(ndev);
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if (err) {
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netdev_err(ndev, "starting CAN controller failed!\n");
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return err;
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}
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if (netif_queue_stopped(ndev))
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netif_wake_queue(ndev);
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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/* transmit a CAN message
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* message layout in the sk_buff should be like this:
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* xx xx xx xx ff ll 00 11 22 33 44 55 66 77
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* [ can_id ] [flags] [len] [can data (up to 8 bytes]
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*/
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static int rockchip_can_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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{
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struct rockchip_can *rcan = netdev_priv(ndev);
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struct can_frame *cf = (struct can_frame *)skb->data;
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canid_t id;
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u8 dlc;
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u32 fi;
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u32 data1 = 0, data2 = 0;
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if (can_dropped_invalid_skb(ndev, skb))
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return NETDEV_TX_OK;
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netif_stop_queue(ndev);
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id = cf->can_id;
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dlc = cf->can_dlc;
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fi = dlc;
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if (id & CAN_RTR_FLAG) {
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fi |= CAN_RTR;
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fi &= ~CAN_DLC_MASK;
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}
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if (id & CAN_EFF_FLAG)
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fi |= CAN_EFF;
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rockchip_can_write_cmdreg(rcan, 0);
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writel(id & CAN_TX_ID_MASK, rcan->base + CAN_TX_ID);
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if (!(id & CAN_RTR_FLAG)) {
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data1 = le32_to_cpup((__le32 *)&cf->data[0]);
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data2 = le32_to_cpup((__le32 *)&cf->data[4]);
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writel(data1, rcan->base + CAN_TX_DATA1);
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writel(data2, rcan->base + CAN_TX_DATA2);
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}
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writel(fi, rcan->base + CAN_TX_FRM_INFO);
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can_put_echo_skb(skb, ndev, 0);
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rockchip_can_write_cmdreg(rcan, TX_REQ);
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netdev_dbg(ndev, "TX: can_id:0x%08x dlc: %d mode: 0x%08x data: 0x%08x 0x%08x\n",
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cf->can_id, cf->can_dlc, rcan->can.ctrlmode, data1, data2);
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return NETDEV_TX_OK;
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}
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static void rockchip_can_rx(struct net_device *ndev)
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{
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struct rockchip_can *rcan = netdev_priv(ndev);
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struct net_device_stats *stats = &ndev->stats;
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struct can_frame *cf;
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struct sk_buff *skb;
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canid_t id;
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u8 fi;
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u32 data1 = 0, data2 = 0;
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/* create zero'ed CAN frame buffer */
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skb = alloc_can_skb(ndev, &cf);
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if (!skb)
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return;
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fi = readl(rcan->base + CAN_RX_FRM_INFO);
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cf->can_dlc = get_can_dlc(fi & CAN_DLC_MASK);
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id = readl(rcan->base + CAN_RX_ID);
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if (fi & CAN_EFF)
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id |= CAN_EFF_FLAG;
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/* remote frame ? */
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if (fi & CAN_RTR) {
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id |= CAN_RTR_FLAG;
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} else {
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data1 = readl(rcan->base + CAN_RX_DATA1);
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data2 = readl(rcan->base + CAN_RX_DATA2);
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}
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cf->can_id = id;
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*(__le32 *)(cf->data + 0) = cpu_to_le32(data1);
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*(__le32 *)(cf->data + 4) = cpu_to_le32(data2);
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stats->rx_packets++;
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stats->rx_bytes += cf->can_dlc;
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netif_rx(skb);
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can_led_event(ndev, CAN_LED_EVENT_RX);
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netdev_dbg(ndev, "%s can_id:0x%08x fi: 0x%08x dlc: %d data: 0x%08x 0x%08x\n",
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__func__, cf->can_id, fi, cf->can_dlc,
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data1, data2);
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}
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static void rockchip_can_clean_rx_info(struct rockchip_can *rcan)
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{
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readl(rcan->base + CAN_RX_FRM_INFO);
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readl(rcan->base + CAN_RX_ID);
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readl(rcan->base + CAN_RX_DATA1);
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readl(rcan->base + CAN_RX_DATA2);
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}
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static int rockchip_can_err(struct net_device *ndev, u8 isr)
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{
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struct rockchip_can *rcan = netdev_priv(ndev);
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struct net_device_stats *stats = &ndev->stats;
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enum can_state state = rcan->can.state;
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enum can_state rx_state, tx_state;
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struct can_frame *cf;
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struct sk_buff *skb;
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unsigned int rxerr, txerr;
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u32 ecc, alc;
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u32 sta_reg;
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skb = alloc_can_err_skb(ndev, &cf);
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rxerr = readl(rcan->base + CAN_RX_ERR_CNT);
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txerr = readl(rcan->base + CAN_TX_ERR_CNT);
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sta_reg = readl(rcan->base + CAN_STATE);
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if (skb) {
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cf->data[6] = txerr;
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cf->data[7] = rxerr;
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}
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if (isr & RX_BUF_OV) {
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/* data overrun interrupt */
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netdev_dbg(ndev, "data overrun interrupt\n");
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if (likely(skb)) {
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cf->can_id |= CAN_ERR_CRTL;
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cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
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}
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stats->rx_over_errors++;
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stats->rx_errors++;
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/* reset the CAN IP by entering reset mode
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* ignoring timeout error
|
*/
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set_reset_mode(ndev);
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set_normal_mode(ndev);
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}
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if (isr & ERR_WARN_INT) {
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/* error warning interrupt */
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netdev_dbg(ndev, "error warning interrupt\n");
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if (sta_reg & BUS_OFF)
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state = CAN_STATE_BUS_OFF;
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else if (sta_reg & ERR_WARN)
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state = CAN_STATE_ERROR_WARNING;
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else
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state = CAN_STATE_ERROR_ACTIVE;
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}
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if (isr & BUS_ERR_INT) {
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/* bus error interrupt */
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netdev_dbg(ndev, "bus error interrupt\n");
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rcan->can.can_stats.bus_error++;
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stats->rx_errors++;
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if (likely(skb)) {
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ecc = readl(rcan->base + CAN_ERR_CODE);
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cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
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switch ((ecc & ERR_TYPE_MASK) >> ERR_TYPE_SHIFT) {
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case BIT_ERR:
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cf->data[2] |= CAN_ERR_PROT_BIT;
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break;
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case FORM_ERR:
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cf->data[2] |= CAN_ERR_PROT_FORM;
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break;
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case STUFF_ERR:
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cf->data[2] |= CAN_ERR_PROT_STUFF;
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break;
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default:
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cf->data[3] = ecc & ERR_LOC_MASK;
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break;
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}
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/* error occurred during transmission? */
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if ((ecc & ERR_DIR_RX) == 0)
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cf->data[2] |= CAN_ERR_PROT_TX;
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}
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}
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if (isr & PASSIVE_ERR) {
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/* error passive interrupt */
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netdev_dbg(ndev, "error passive interrupt\n");
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if (state == CAN_STATE_ERROR_PASSIVE)
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state = CAN_STATE_ERROR_WARNING;
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else
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state = CAN_STATE_ERROR_PASSIVE;
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}
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if (isr & TX_LOSTARB) {
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/* arbitration lost interrupt */
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netdev_dbg(ndev, "arbitration lost interrupt\n");
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alc = readl(rcan->base + CAN_LOSTARB_CODE);
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rcan->can.can_stats.arbitration_lost++;
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stats->tx_errors++;
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if (likely(skb)) {
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cf->can_id |= CAN_ERR_LOSTARB;
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cf->data[0] = alc;
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}
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}
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if (state != rcan->can.state) {
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tx_state = txerr >= rxerr ? state : 0;
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rx_state = txerr <= rxerr ? state : 0;
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if (likely(skb))
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can_change_state(ndev, cf, tx_state, rx_state);
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else
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rcan->can.state = state;
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if (state == CAN_STATE_BUS_OFF)
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can_bus_off(ndev);
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}
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|
if (likely(skb)) {
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stats->rx_packets++;
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stats->rx_bytes += cf->can_dlc;
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netif_rx(skb);
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} else {
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return -ENOMEM;
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}
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return 0;
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}
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static irqreturn_t rockchip_can_interrupt(int irq, void *dev_id)
|
{
|
struct net_device *ndev = (struct net_device *)dev_id;
|
struct rockchip_can *rcan = netdev_priv(ndev);
|
struct net_device_stats *stats = &ndev->stats;
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u8 err_int = ERR_WARN_INT | RX_BUF_OV | PASSIVE_ERR |
|
TX_LOSTARB | BUS_ERR_INT;
|
u8 isr;
|
|
isr = readl(rcan->base + CAN_INT);
|
if (isr & TX_FINISH) {
|
/* transmission complete interrupt */
|
stats->tx_bytes += readl(rcan->base + CAN_TX_FRM_INFO) &
|
CAN_DLC_MASK;
|
stats->tx_packets++;
|
rockchip_can_write_cmdreg(rcan, 0);
|
can_get_echo_skb(ndev, 0);
|
netif_wake_queue(ndev);
|
can_led_event(ndev, CAN_LED_EVENT_TX);
|
}
|
|
if (isr & RX_FINISH)
|
rockchip_can_rx(ndev);
|
|
if (isr & err_int) {
|
rockchip_can_clean_rx_info(rcan);
|
if (rockchip_can_err(ndev, isr))
|
netdev_err(ndev, "can't allocate buffer - clearing pending interrupts\n");
|
}
|
|
writel(isr, rcan->base + CAN_INT);
|
rockchip_can_clean_rx_info(rcan);
|
netdev_dbg(ndev, "isr: 0x%x\n", isr);
|
return IRQ_HANDLED;
|
}
|
|
static int rockchip_can_open(struct net_device *ndev)
|
{
|
struct rockchip_can *rcan = netdev_priv(ndev);
|
int err;
|
|
/* common open */
|
err = open_candev(ndev);
|
if (err)
|
return err;
|
|
err = pm_runtime_get_sync(rcan->dev);
|
if (err < 0) {
|
netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
|
__func__, err);
|
goto exit;
|
}
|
|
err = rockchip_can_start(ndev);
|
if (err) {
|
netdev_err(ndev, "could not start CAN peripheral\n");
|
goto exit_can_start;
|
}
|
|
can_led_event(ndev, CAN_LED_EVENT_OPEN);
|
netif_start_queue(ndev);
|
|
netdev_dbg(ndev, "%s\n", __func__);
|
return 0;
|
|
exit_can_start:
|
pm_runtime_put(rcan->dev);
|
exit:
|
close_candev(ndev);
|
return err;
|
}
|
|
static int rockchip_can_close(struct net_device *ndev)
|
{
|
struct rockchip_can *rcan = netdev_priv(ndev);
|
|
netif_stop_queue(ndev);
|
rockchip_can_stop(ndev);
|
close_candev(ndev);
|
can_led_event(ndev, CAN_LED_EVENT_STOP);
|
pm_runtime_put(rcan->dev);
|
|
netdev_dbg(ndev, "%s\n", __func__);
|
return 0;
|
}
|
|
static const struct net_device_ops rockchip_can_netdev_ops = {
|
.ndo_open = rockchip_can_open,
|
.ndo_stop = rockchip_can_close,
|
.ndo_start_xmit = rockchip_can_start_xmit,
|
};
|
|
/**
|
* rockchip_can_suspend - Suspend method for the driver
|
* @dev: Address of the device structure
|
*
|
* Put the driver into low power mode.
|
* Return: 0 on success and failure value on error
|
*/
|
static int __maybe_unused rockchip_can_suspend(struct device *dev)
|
{
|
struct net_device *ndev = dev_get_drvdata(dev);
|
|
if (netif_running(ndev)) {
|
netif_stop_queue(ndev);
|
netif_device_detach(ndev);
|
rockchip_can_stop(ndev);
|
}
|
|
return pm_runtime_force_suspend(dev);
|
}
|
|
/**
|
* rockchip_can_resume - Resume from suspend
|
* @dev: Address of the device structure
|
*
|
* Resume operation after suspend.
|
* Return: 0 on success and failure value on error
|
*/
|
static int __maybe_unused rockchip_can_resume(struct device *dev)
|
{
|
struct net_device *ndev = dev_get_drvdata(dev);
|
int ret;
|
|
ret = pm_runtime_force_resume(dev);
|
if (ret) {
|
dev_err(dev, "pm_runtime_force_resume failed on resume\n");
|
return ret;
|
}
|
|
if (netif_running(ndev)) {
|
ret = rockchip_can_start(ndev);
|
if (ret) {
|
dev_err(dev, "rockchip_can_chip_start failed on resume\n");
|
return ret;
|
}
|
|
netif_device_attach(ndev);
|
netif_start_queue(ndev);
|
}
|
|
return 0;
|
}
|
|
/**
|
* rockchip_can_runtime_suspend - Runtime suspend method for the driver
|
* @dev: Address of the device structure
|
*
|
* Put the driver into low power mode.
|
* Return: 0 always
|
*/
|
static int __maybe_unused rockchip_can_runtime_suspend(struct device *dev)
|
{
|
struct net_device *ndev = dev_get_drvdata(dev);
|
struct rockchip_can *rcan = netdev_priv(ndev);
|
|
clk_bulk_disable_unprepare(rcan->num_clks, rcan->clks);
|
|
return 0;
|
}
|
|
/**
|
* rockchip_can_runtime_resume - Runtime resume from suspend
|
* @dev: Address of the device structure
|
*
|
* Resume operation after suspend.
|
* Return: 0 on success and failure value on error
|
*/
|
static int __maybe_unused rockchip_can_runtime_resume(struct device *dev)
|
{
|
struct net_device *ndev = dev_get_drvdata(dev);
|
struct rockchip_can *rcan = netdev_priv(ndev);
|
int ret;
|
|
ret = clk_bulk_prepare_enable(rcan->num_clks, rcan->clks);
|
if (ret) {
|
dev_err(dev, "Cannot enable clock.\n");
|
return ret;
|
}
|
|
return 0;
|
}
|
|
static const struct dev_pm_ops rockchip_can_dev_pm_ops = {
|
SET_SYSTEM_SLEEP_PM_OPS(rockchip_can_suspend, rockchip_can_resume)
|
SET_RUNTIME_PM_OPS(rockchip_can_runtime_suspend,
|
rockchip_can_runtime_resume, NULL)
|
};
|
|
static const struct of_device_id rockchip_can_of_match[] = {
|
{.compatible = "rockchip,can-1.0"},
|
{},
|
};
|
MODULE_DEVICE_TABLE(of, rockchip_can_of_match);
|
|
static int rockchip_can_probe(struct platform_device *pdev)
|
{
|
struct net_device *ndev;
|
struct rockchip_can *rcan;
|
struct resource *res;
|
void __iomem *addr;
|
int err, irq;
|
|
irq = platform_get_irq(pdev, 0);
|
if (irq < 0) {
|
dev_err(&pdev->dev, "could not get a valid irq\n");
|
return -ENODEV;
|
}
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
addr = devm_ioremap_resource(&pdev->dev, res);
|
if (IS_ERR(addr))
|
return -EBUSY;
|
|
ndev = alloc_candev(sizeof(struct rockchip_can), 1);
|
if (!ndev) {
|
dev_err(&pdev->dev, "could not allocate memory for CAN device\n");
|
return -ENOMEM;
|
}
|
|
ndev->netdev_ops = &rockchip_can_netdev_ops;
|
ndev->irq = irq;
|
ndev->flags |= IFF_ECHO;
|
|
rcan = netdev_priv(ndev);
|
|
/* register interrupt handler */
|
err = devm_request_irq(&pdev->dev, ndev->irq, rockchip_can_interrupt,
|
0, ndev->name, ndev);
|
if (err) {
|
dev_err(&pdev->dev, "request_irq err: %d\n", err);
|
return err;
|
}
|
|
rcan->reset = devm_reset_control_array_get(&pdev->dev, false, false);
|
if (IS_ERR(rcan->reset)) {
|
if (PTR_ERR(rcan->reset) != -EPROBE_DEFER)
|
dev_err(&pdev->dev, "failed to get rcan reset lines\n");
|
return PTR_ERR(rcan->reset);
|
}
|
|
rcan->num_clks = devm_clk_bulk_get_all(&pdev->dev, &rcan->clks);
|
if (rcan->num_clks < 1) {
|
dev_err(&pdev->dev, "bus clock not found\n");
|
return -ENODEV;
|
}
|
|
rcan->dev = &pdev->dev;
|
rcan->can.clock.freq = clk_get_rate(rcan->clks[0].clk);
|
rcan->can.bittiming_const = &rockchip_can_bittiming_const;
|
rcan->can.do_set_mode = rockchip_can_set_mode;
|
rcan->can.do_get_berr_counter = rockchip_can_get_berr_counter;
|
rcan->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
|
CAN_CTRLMODE_LISTENONLY |
|
CAN_CTRLMODE_LOOPBACK |
|
CAN_CTRLMODE_3_SAMPLES;
|
rcan->base = addr;
|
platform_set_drvdata(pdev, ndev);
|
SET_NETDEV_DEV(ndev, &pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
err = pm_runtime_get_sync(&pdev->dev);
|
if (err < 0) {
|
dev_err(&pdev->dev, "%s: pm_runtime_get failed(%d)\n",
|
__func__, err);
|
goto err_pmdisable;
|
}
|
|
err = register_candev(ndev);
|
if (err) {
|
dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
|
DRV_NAME, err);
|
goto err_disableclks;
|
}
|
|
devm_can_led_init(ndev);
|
|
pm_runtime_put(&pdev->dev);
|
|
return 0;
|
|
err_disableclks:
|
pm_runtime_put(&pdev->dev);
|
err_pmdisable:
|
pm_runtime_disable(&pdev->dev);
|
free_candev(ndev);
|
|
return err;
|
}
|
|
static int rockchip_can_remove(struct platform_device *pdev)
|
{
|
struct net_device *ndev = platform_get_drvdata(pdev);
|
|
unregister_netdev(ndev);
|
pm_runtime_disable(&pdev->dev);
|
free_candev(ndev);
|
|
return 0;
|
}
|
|
static struct platform_driver rockchip_can_driver = {
|
.driver = {
|
.name = DRV_NAME,
|
.pm = &rockchip_can_dev_pm_ops,
|
.of_match_table = rockchip_can_of_match,
|
},
|
.probe = rockchip_can_probe,
|
.remove = rockchip_can_remove,
|
};
|
module_platform_driver(rockchip_can_driver);
|
|
MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
|
MODULE_LICENSE("GPL");
|
MODULE_DESCRIPTION("Rockchip CAN Drivers");
|
