// SPDX-License-Identifier: GPL-2.0+
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/* Renesas R-Car CAN device driver
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*
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* Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com>
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* Copyright (C) 2013 Renesas Solutions Corp.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/errno.h>
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#include <linux/netdevice.h>
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#include <linux/platform_device.h>
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#include <linux/can/led.h>
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#include <linux/can/dev.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#define RCAR_CAN_DRV_NAME "rcar_can"
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/* Clock Select Register settings */
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enum CLKR {
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CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */
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CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */
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CLKR_CLKEXT = 3, /* Externally input clock */
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};
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#define RCAR_SUPPORTED_CLOCKS (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \
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BIT(CLKR_CLKEXT))
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/* Mailbox configuration:
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* mailbox 60 - 63 - Rx FIFO mailboxes
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* mailbox 56 - 59 - Tx FIFO mailboxes
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* non-FIFO mailboxes are not used
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*/
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#define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */
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#define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */
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#define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */
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#define RCAR_CAN_FIFO_DEPTH 4
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/* Mailbox registers structure */
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struct rcar_can_mbox_regs {
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u32 id; /* IDE and RTR bits, SID and EID */
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u8 stub; /* Not used */
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u8 dlc; /* Data Length Code - bits [0..3] */
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u8 data[8]; /* Data Bytes */
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u8 tsh; /* Time Stamp Higher Byte */
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u8 tsl; /* Time Stamp Lower Byte */
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};
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struct rcar_can_regs {
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struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */
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u32 mkr_2_9[8]; /* Mask Registers 2-9 */
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u32 fidcr[2]; /* FIFO Received ID Compare Register */
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u32 mkivlr1; /* Mask Invalid Register 1 */
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u32 mier1; /* Mailbox Interrupt Enable Register 1 */
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u32 mkr_0_1[2]; /* Mask Registers 0-1 */
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u32 mkivlr0; /* Mask Invalid Register 0*/
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u32 mier0; /* Mailbox Interrupt Enable Register 0 */
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u8 pad_440[0x3c0];
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u8 mctl[64]; /* Message Control Registers */
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u16 ctlr; /* Control Register */
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u16 str; /* Status register */
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u8 bcr[3]; /* Bit Configuration Register */
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u8 clkr; /* Clock Select Register */
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u8 rfcr; /* Receive FIFO Control Register */
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u8 rfpcr; /* Receive FIFO Pointer Control Register */
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u8 tfcr; /* Transmit FIFO Control Register */
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u8 tfpcr; /* Transmit FIFO Pointer Control Register */
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u8 eier; /* Error Interrupt Enable Register */
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u8 eifr; /* Error Interrupt Factor Judge Register */
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u8 recr; /* Receive Error Count Register */
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u8 tecr; /* Transmit Error Count Register */
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u8 ecsr; /* Error Code Store Register */
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u8 cssr; /* Channel Search Support Register */
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u8 mssr; /* Mailbox Search Status Register */
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u8 msmr; /* Mailbox Search Mode Register */
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u16 tsr; /* Time Stamp Register */
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u8 afsr; /* Acceptance Filter Support Register */
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u8 pad_857;
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u8 tcr; /* Test Control Register */
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u8 pad_859[7];
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u8 ier; /* Interrupt Enable Register */
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u8 isr; /* Interrupt Status Register */
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u8 pad_862;
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u8 mbsmr; /* Mailbox Search Mask Register */
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};
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struct rcar_can_priv {
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struct can_priv can; /* Must be the first member! */
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struct net_device *ndev;
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struct napi_struct napi;
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struct rcar_can_regs __iomem *regs;
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struct clk *clk;
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struct clk *can_clk;
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u8 tx_dlc[RCAR_CAN_FIFO_DEPTH];
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u32 tx_head;
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u32 tx_tail;
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u8 clock_select;
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u8 ier;
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};
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static const struct can_bittiming_const rcar_can_bittiming_const = {
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.name = RCAR_CAN_DRV_NAME,
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.tseg1_min = 4,
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.tseg1_max = 16,
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.tseg2_min = 2,
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.tseg2_max = 8,
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.sjw_max = 4,
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.brp_min = 1,
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.brp_max = 1024,
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.brp_inc = 1,
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};
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/* Control Register bits */
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#define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */
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#define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */
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/* at bus-off entry */
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#define RCAR_CAN_CTLR_SLPM (1 << 10)
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#define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */
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#define RCAR_CAN_CTLR_CANM_HALT (1 << 9)
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#define RCAR_CAN_CTLR_CANM_RESET (1 << 8)
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#define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8)
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#define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */
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#define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */
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#define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */
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#define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */
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/* Status Register bits */
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#define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */
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/* FIFO Received ID Compare Registers 0 and 1 bits */
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#define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */
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#define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */
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/* Receive FIFO Control Register bits */
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#define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */
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#define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */
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/* Transmit FIFO Control Register bits */
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#define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */
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/* Number Status Bits */
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#define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */
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/* Message Number Status Bits */
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#define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */
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#define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */
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/* for Rx mailboxes 0-31 */
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#define RCAR_CAN_N_RX_MKREGS2 8
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/* Bit Configuration Register settings */
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#define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20)
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#define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8)
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#define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4)
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#define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07)
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/* Mailbox and Mask Registers bits */
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#define RCAR_CAN_IDE (1 << 31)
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#define RCAR_CAN_RTR (1 << 30)
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#define RCAR_CAN_SID_SHIFT 18
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/* Mailbox Interrupt Enable Register 1 bits */
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#define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */
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#define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */
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/* Interrupt Enable Register bits */
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#define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */
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#define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */
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/* Enable Bit */
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#define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */
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/* Enable Bit */
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/* Interrupt Status Register bits */
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#define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */
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#define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */
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/* Status Bit */
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#define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */
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/* Status Bit */
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/* Error Interrupt Enable Register bits */
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#define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */
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#define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */
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/* Interrupt Enable */
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#define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */
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#define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */
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#define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */
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#define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */
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#define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */
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#define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */
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/* Error Interrupt Factor Judge Register bits */
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#define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */
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#define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */
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/* Detect Flag */
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#define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */
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#define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */
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#define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */
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#define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */
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#define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */
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#define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */
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/* Error Code Store Register bits */
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#define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */
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#define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */
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#define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */
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#define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */
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#define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */
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#define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */
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#define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */
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#define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */
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#define RCAR_CAN_NAPI_WEIGHT 4
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#define MAX_STR_READS 0x100
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static void tx_failure_cleanup(struct net_device *ndev)
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{
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int i;
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for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++)
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can_free_echo_skb(ndev, i);
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}
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static void rcar_can_error(struct net_device *ndev)
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{
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struct rcar_can_priv *priv = netdev_priv(ndev);
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struct net_device_stats *stats = &ndev->stats;
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struct can_frame *cf;
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struct sk_buff *skb;
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u8 eifr, txerr = 0, rxerr = 0;
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/* Propagate the error condition to the CAN stack */
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skb = alloc_can_err_skb(ndev, &cf);
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eifr = readb(&priv->regs->eifr);
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if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) {
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txerr = readb(&priv->regs->tecr);
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rxerr = readb(&priv->regs->recr);
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if (skb)
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cf->can_id |= CAN_ERR_CRTL;
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}
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if (eifr & RCAR_CAN_EIFR_BEIF) {
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int rx_errors = 0, tx_errors = 0;
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u8 ecsr;
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netdev_dbg(priv->ndev, "Bus error interrupt:\n");
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if (skb)
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cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
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ecsr = readb(&priv->regs->ecsr);
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if (ecsr & RCAR_CAN_ECSR_ADEF) {
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netdev_dbg(priv->ndev, "ACK Delimiter Error\n");
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tx_errors++;
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writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr);
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if (skb)
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cf->data[3] = CAN_ERR_PROT_LOC_ACK_DEL;
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}
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if (ecsr & RCAR_CAN_ECSR_BE0F) {
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netdev_dbg(priv->ndev, "Bit Error (dominant)\n");
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tx_errors++;
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writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr);
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if (skb)
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cf->data[2] |= CAN_ERR_PROT_BIT0;
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}
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if (ecsr & RCAR_CAN_ECSR_BE1F) {
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netdev_dbg(priv->ndev, "Bit Error (recessive)\n");
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tx_errors++;
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writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr);
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if (skb)
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cf->data[2] |= CAN_ERR_PROT_BIT1;
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}
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if (ecsr & RCAR_CAN_ECSR_CEF) {
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netdev_dbg(priv->ndev, "CRC Error\n");
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rx_errors++;
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writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr);
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if (skb)
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cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
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}
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if (ecsr & RCAR_CAN_ECSR_AEF) {
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netdev_dbg(priv->ndev, "ACK Error\n");
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tx_errors++;
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writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr);
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if (skb) {
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cf->can_id |= CAN_ERR_ACK;
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cf->data[3] = CAN_ERR_PROT_LOC_ACK;
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}
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}
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if (ecsr & RCAR_CAN_ECSR_FEF) {
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netdev_dbg(priv->ndev, "Form Error\n");
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rx_errors++;
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writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr);
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if (skb)
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cf->data[2] |= CAN_ERR_PROT_FORM;
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}
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if (ecsr & RCAR_CAN_ECSR_SEF) {
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netdev_dbg(priv->ndev, "Stuff Error\n");
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rx_errors++;
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writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr);
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if (skb)
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cf->data[2] |= CAN_ERR_PROT_STUFF;
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}
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priv->can.can_stats.bus_error++;
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ndev->stats.rx_errors += rx_errors;
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ndev->stats.tx_errors += tx_errors;
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writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr);
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}
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if (eifr & RCAR_CAN_EIFR_EWIF) {
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netdev_dbg(priv->ndev, "Error warning interrupt\n");
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priv->can.state = CAN_STATE_ERROR_WARNING;
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priv->can.can_stats.error_warning++;
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/* Clear interrupt condition */
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writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr);
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if (skb)
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cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
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CAN_ERR_CRTL_RX_WARNING;
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}
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if (eifr & RCAR_CAN_EIFR_EPIF) {
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netdev_dbg(priv->ndev, "Error passive interrupt\n");
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priv->can.state = CAN_STATE_ERROR_PASSIVE;
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priv->can.can_stats.error_passive++;
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/* Clear interrupt condition */
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writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr);
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if (skb)
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cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
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CAN_ERR_CRTL_RX_PASSIVE;
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}
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if (eifr & RCAR_CAN_EIFR_BOEIF) {
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netdev_dbg(priv->ndev, "Bus-off entry interrupt\n");
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tx_failure_cleanup(ndev);
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priv->ier = RCAR_CAN_IER_ERSIE;
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writeb(priv->ier, &priv->regs->ier);
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priv->can.state = CAN_STATE_BUS_OFF;
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/* Clear interrupt condition */
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writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr);
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priv->can.can_stats.bus_off++;
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can_bus_off(ndev);
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if (skb)
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cf->can_id |= CAN_ERR_BUSOFF;
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} else if (skb) {
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cf->data[6] = txerr;
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cf->data[7] = rxerr;
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}
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if (eifr & RCAR_CAN_EIFR_ORIF) {
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netdev_dbg(priv->ndev, "Receive overrun error interrupt\n");
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ndev->stats.rx_over_errors++;
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ndev->stats.rx_errors++;
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writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr);
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if (skb) {
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cf->can_id |= CAN_ERR_CRTL;
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cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
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}
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}
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if (eifr & RCAR_CAN_EIFR_OLIF) {
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netdev_dbg(priv->ndev,
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"Overload Frame Transmission error interrupt\n");
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ndev->stats.rx_over_errors++;
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ndev->stats.rx_errors++;
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writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr);
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if (skb) {
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cf->can_id |= CAN_ERR_PROT;
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cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
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}
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}
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if (skb) {
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stats->rx_packets++;
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stats->rx_bytes += cf->can_dlc;
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netif_rx(skb);
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}
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}
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static void rcar_can_tx_done(struct net_device *ndev)
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{
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struct rcar_can_priv *priv = netdev_priv(ndev);
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struct net_device_stats *stats = &ndev->stats;
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u8 isr;
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while (1) {
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u8 unsent = readb(&priv->regs->tfcr);
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unsent = (unsent & RCAR_CAN_TFCR_TFUST) >>
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RCAR_CAN_TFCR_TFUST_SHIFT;
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if (priv->tx_head - priv->tx_tail <= unsent)
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break;
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stats->tx_packets++;
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stats->tx_bytes += priv->tx_dlc[priv->tx_tail %
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RCAR_CAN_FIFO_DEPTH];
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priv->tx_dlc[priv->tx_tail % RCAR_CAN_FIFO_DEPTH] = 0;
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can_get_echo_skb(ndev, priv->tx_tail % RCAR_CAN_FIFO_DEPTH);
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priv->tx_tail++;
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netif_wake_queue(ndev);
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}
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/* Clear interrupt */
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isr = readb(&priv->regs->isr);
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writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr);
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can_led_event(ndev, CAN_LED_EVENT_TX);
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}
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static irqreturn_t rcar_can_interrupt(int irq, void *dev_id)
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{
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struct net_device *ndev = dev_id;
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struct rcar_can_priv *priv = netdev_priv(ndev);
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u8 isr;
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isr = readb(&priv->regs->isr);
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if (!(isr & priv->ier))
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return IRQ_NONE;
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if (isr & RCAR_CAN_ISR_ERSF)
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rcar_can_error(ndev);
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if (isr & RCAR_CAN_ISR_TXFF)
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rcar_can_tx_done(ndev);
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if (isr & RCAR_CAN_ISR_RXFF) {
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if (napi_schedule_prep(&priv->napi)) {
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/* Disable Rx FIFO interrupts */
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priv->ier &= ~RCAR_CAN_IER_RXFIE;
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writeb(priv->ier, &priv->regs->ier);
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__napi_schedule(&priv->napi);
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}
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}
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return IRQ_HANDLED;
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}
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static void rcar_can_set_bittiming(struct net_device *dev)
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{
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struct rcar_can_priv *priv = netdev_priv(dev);
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struct can_bittiming *bt = &priv->can.bittiming;
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u32 bcr;
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bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) |
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RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) |
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RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1);
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/* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access.
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* All the registers are big-endian but they get byte-swapped on 32-bit
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* read/write (but not on 8-bit, contrary to the manuals)...
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*/
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writel((bcr << 8) | priv->clock_select, &priv->regs->bcr);
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}
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static void rcar_can_start(struct net_device *ndev)
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{
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struct rcar_can_priv *priv = netdev_priv(ndev);
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u16 ctlr;
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int i;
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/* Set controller to known mode:
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* - FIFO mailbox mode
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* - accept all messages
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* - overrun mode
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* CAN is in sleep mode after MCU hardware or software reset.
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*/
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ctlr = readw(&priv->regs->ctlr);
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ctlr &= ~RCAR_CAN_CTLR_SLPM;
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writew(ctlr, &priv->regs->ctlr);
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/* Go to reset mode */
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ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET;
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writew(ctlr, &priv->regs->ctlr);
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for (i = 0; i < MAX_STR_READS; i++) {
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if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)
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break;
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}
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rcar_can_set_bittiming(ndev);
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ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */
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ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */
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/* at bus-off */
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ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */
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ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */
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writew(ctlr, &priv->regs->ctlr);
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/* Accept all SID and EID */
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writel(0, &priv->regs->mkr_2_9[6]);
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writel(0, &priv->regs->mkr_2_9[7]);
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/* In FIFO mailbox mode, write "0" to bits 24 to 31 */
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writel(0, &priv->regs->mkivlr1);
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/* Accept all frames */
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writel(0, &priv->regs->fidcr[0]);
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writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]);
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/* Enable and configure FIFO mailbox interrupts */
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writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1);
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priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE |
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RCAR_CAN_IER_TXFIE;
|
writeb(priv->ier, &priv->regs->ier);
|
|
/* Accumulate error codes */
|
writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr);
|
/* Enable error interrupts */
|
writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE |
|
(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ?
|
RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE |
|
RCAR_CAN_EIER_OLIE, &priv->regs->eier);
|
priv->can.state = CAN_STATE_ERROR_ACTIVE;
|
|
/* Go to operation mode */
|
writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr);
|
for (i = 0; i < MAX_STR_READS; i++) {
|
if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST))
|
break;
|
}
|
/* Enable Rx and Tx FIFO */
|
writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr);
|
writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr);
|
}
|
|
static int rcar_can_open(struct net_device *ndev)
|
{
|
struct rcar_can_priv *priv = netdev_priv(ndev);
|
int err;
|
|
err = clk_prepare_enable(priv->clk);
|
if (err) {
|
netdev_err(ndev,
|
"failed to enable peripheral clock, error %d\n",
|
err);
|
goto out;
|
}
|
err = clk_prepare_enable(priv->can_clk);
|
if (err) {
|
netdev_err(ndev, "failed to enable CAN clock, error %d\n",
|
err);
|
goto out_clock;
|
}
|
err = open_candev(ndev);
|
if (err) {
|
netdev_err(ndev, "open_candev() failed, error %d\n", err);
|
goto out_can_clock;
|
}
|
napi_enable(&priv->napi);
|
err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev);
|
if (err) {
|
netdev_err(ndev, "request_irq(%d) failed, error %d\n",
|
ndev->irq, err);
|
goto out_close;
|
}
|
can_led_event(ndev, CAN_LED_EVENT_OPEN);
|
rcar_can_start(ndev);
|
netif_start_queue(ndev);
|
return 0;
|
out_close:
|
napi_disable(&priv->napi);
|
close_candev(ndev);
|
out_can_clock:
|
clk_disable_unprepare(priv->can_clk);
|
out_clock:
|
clk_disable_unprepare(priv->clk);
|
out:
|
return err;
|
}
|
|
static void rcar_can_stop(struct net_device *ndev)
|
{
|
struct rcar_can_priv *priv = netdev_priv(ndev);
|
u16 ctlr;
|
int i;
|
|
/* Go to (force) reset mode */
|
ctlr = readw(&priv->regs->ctlr);
|
ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET;
|
writew(ctlr, &priv->regs->ctlr);
|
for (i = 0; i < MAX_STR_READS; i++) {
|
if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)
|
break;
|
}
|
writel(0, &priv->regs->mier0);
|
writel(0, &priv->regs->mier1);
|
writeb(0, &priv->regs->ier);
|
writeb(0, &priv->regs->eier);
|
/* Go to sleep mode */
|
ctlr |= RCAR_CAN_CTLR_SLPM;
|
writew(ctlr, &priv->regs->ctlr);
|
priv->can.state = CAN_STATE_STOPPED;
|
}
|
|
static int rcar_can_close(struct net_device *ndev)
|
{
|
struct rcar_can_priv *priv = netdev_priv(ndev);
|
|
netif_stop_queue(ndev);
|
rcar_can_stop(ndev);
|
free_irq(ndev->irq, ndev);
|
napi_disable(&priv->napi);
|
clk_disable_unprepare(priv->can_clk);
|
clk_disable_unprepare(priv->clk);
|
close_candev(ndev);
|
can_led_event(ndev, CAN_LED_EVENT_STOP);
|
return 0;
|
}
|
|
static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb,
|
struct net_device *ndev)
|
{
|
struct rcar_can_priv *priv = netdev_priv(ndev);
|
struct can_frame *cf = (struct can_frame *)skb->data;
|
u32 data, i;
|
|
if (can_dropped_invalid_skb(ndev, skb))
|
return NETDEV_TX_OK;
|
|
if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
|
data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE;
|
else /* Standard frame format */
|
data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT;
|
|
if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */
|
data |= RCAR_CAN_RTR;
|
} else {
|
for (i = 0; i < cf->can_dlc; i++)
|
writeb(cf->data[i],
|
&priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]);
|
}
|
|
writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id);
|
|
writeb(cf->can_dlc, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc);
|
|
priv->tx_dlc[priv->tx_head % RCAR_CAN_FIFO_DEPTH] = cf->can_dlc;
|
can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH);
|
priv->tx_head++;
|
/* Start Tx: write 0xff to the TFPCR register to increment
|
* the CPU-side pointer for the transmit FIFO to the next
|
* mailbox location
|
*/
|
writeb(0xff, &priv->regs->tfpcr);
|
/* Stop the queue if we've filled all FIFO entries */
|
if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH)
|
netif_stop_queue(ndev);
|
|
return NETDEV_TX_OK;
|
}
|
|
static const struct net_device_ops rcar_can_netdev_ops = {
|
.ndo_open = rcar_can_open,
|
.ndo_stop = rcar_can_close,
|
.ndo_start_xmit = rcar_can_start_xmit,
|
.ndo_change_mtu = can_change_mtu,
|
};
|
|
static void rcar_can_rx_pkt(struct rcar_can_priv *priv)
|
{
|
struct net_device_stats *stats = &priv->ndev->stats;
|
struct can_frame *cf;
|
struct sk_buff *skb;
|
u32 data;
|
u8 dlc;
|
|
skb = alloc_can_skb(priv->ndev, &cf);
|
if (!skb) {
|
stats->rx_dropped++;
|
return;
|
}
|
|
data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id);
|
if (data & RCAR_CAN_IDE)
|
cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
|
else
|
cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK;
|
|
dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc);
|
cf->can_dlc = get_can_dlc(dlc);
|
if (data & RCAR_CAN_RTR) {
|
cf->can_id |= CAN_RTR_FLAG;
|
} else {
|
for (dlc = 0; dlc < cf->can_dlc; dlc++)
|
cf->data[dlc] =
|
readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]);
|
}
|
|
can_led_event(priv->ndev, CAN_LED_EVENT_RX);
|
|
stats->rx_bytes += cf->can_dlc;
|
stats->rx_packets++;
|
netif_receive_skb(skb);
|
}
|
|
static int rcar_can_rx_poll(struct napi_struct *napi, int quota)
|
{
|
struct rcar_can_priv *priv = container_of(napi,
|
struct rcar_can_priv, napi);
|
int num_pkts;
|
|
for (num_pkts = 0; num_pkts < quota; num_pkts++) {
|
u8 rfcr, isr;
|
|
isr = readb(&priv->regs->isr);
|
/* Clear interrupt bit */
|
if (isr & RCAR_CAN_ISR_RXFF)
|
writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr);
|
rfcr = readb(&priv->regs->rfcr);
|
if (rfcr & RCAR_CAN_RFCR_RFEST)
|
break;
|
rcar_can_rx_pkt(priv);
|
/* Write 0xff to the RFPCR register to increment
|
* the CPU-side pointer for the receive FIFO
|
* to the next mailbox location
|
*/
|
writeb(0xff, &priv->regs->rfpcr);
|
}
|
/* All packets processed */
|
if (num_pkts < quota) {
|
napi_complete_done(napi, num_pkts);
|
priv->ier |= RCAR_CAN_IER_RXFIE;
|
writeb(priv->ier, &priv->regs->ier);
|
}
|
return num_pkts;
|
}
|
|
static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
|
{
|
switch (mode) {
|
case CAN_MODE_START:
|
rcar_can_start(ndev);
|
netif_wake_queue(ndev);
|
return 0;
|
default:
|
return -EOPNOTSUPP;
|
}
|
}
|
|
static int rcar_can_get_berr_counter(const struct net_device *dev,
|
struct can_berr_counter *bec)
|
{
|
struct rcar_can_priv *priv = netdev_priv(dev);
|
int err;
|
|
err = clk_prepare_enable(priv->clk);
|
if (err)
|
return err;
|
bec->txerr = readb(&priv->regs->tecr);
|
bec->rxerr = readb(&priv->regs->recr);
|
clk_disable_unprepare(priv->clk);
|
return 0;
|
}
|
|
static const char * const clock_names[] = {
|
[CLKR_CLKP1] = "clkp1",
|
[CLKR_CLKP2] = "clkp2",
|
[CLKR_CLKEXT] = "can_clk",
|
};
|
|
static int rcar_can_probe(struct platform_device *pdev)
|
{
|
struct rcar_can_priv *priv;
|
struct net_device *ndev;
|
void __iomem *addr;
|
u32 clock_select = CLKR_CLKP1;
|
int err = -ENODEV;
|
int irq;
|
|
of_property_read_u32(pdev->dev.of_node, "renesas,can-clock-select",
|
&clock_select);
|
|
irq = platform_get_irq(pdev, 0);
|
if (irq < 0) {
|
err = irq;
|
goto fail;
|
}
|
|
addr = devm_platform_ioremap_resource(pdev, 0);
|
if (IS_ERR(addr)) {
|
err = PTR_ERR(addr);
|
goto fail;
|
}
|
|
ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH);
|
if (!ndev) {
|
dev_err(&pdev->dev, "alloc_candev() failed\n");
|
err = -ENOMEM;
|
goto fail;
|
}
|
|
priv = netdev_priv(ndev);
|
|
priv->clk = devm_clk_get(&pdev->dev, "clkp1");
|
if (IS_ERR(priv->clk)) {
|
err = PTR_ERR(priv->clk);
|
dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
|
err);
|
goto fail_clk;
|
}
|
|
if (!(BIT(clock_select) & RCAR_SUPPORTED_CLOCKS)) {
|
err = -EINVAL;
|
dev_err(&pdev->dev, "invalid CAN clock selected\n");
|
goto fail_clk;
|
}
|
priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]);
|
if (IS_ERR(priv->can_clk)) {
|
err = PTR_ERR(priv->can_clk);
|
dev_err(&pdev->dev, "cannot get CAN clock, error %d\n", err);
|
goto fail_clk;
|
}
|
|
ndev->netdev_ops = &rcar_can_netdev_ops;
|
ndev->irq = irq;
|
ndev->flags |= IFF_ECHO;
|
priv->ndev = ndev;
|
priv->regs = addr;
|
priv->clock_select = clock_select;
|
priv->can.clock.freq = clk_get_rate(priv->can_clk);
|
priv->can.bittiming_const = &rcar_can_bittiming_const;
|
priv->can.do_set_mode = rcar_can_do_set_mode;
|
priv->can.do_get_berr_counter = rcar_can_get_berr_counter;
|
priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
|
platform_set_drvdata(pdev, ndev);
|
SET_NETDEV_DEV(ndev, &pdev->dev);
|
|
netif_napi_add(ndev, &priv->napi, rcar_can_rx_poll,
|
RCAR_CAN_NAPI_WEIGHT);
|
err = register_candev(ndev);
|
if (err) {
|
dev_err(&pdev->dev, "register_candev() failed, error %d\n",
|
err);
|
goto fail_candev;
|
}
|
|
devm_can_led_init(ndev);
|
|
dev_info(&pdev->dev, "device registered (IRQ%d)\n", ndev->irq);
|
|
return 0;
|
fail_candev:
|
netif_napi_del(&priv->napi);
|
fail_clk:
|
free_candev(ndev);
|
fail:
|
return err;
|
}
|
|
static int rcar_can_remove(struct platform_device *pdev)
|
{
|
struct net_device *ndev = platform_get_drvdata(pdev);
|
struct rcar_can_priv *priv = netdev_priv(ndev);
|
|
unregister_candev(ndev);
|
netif_napi_del(&priv->napi);
|
free_candev(ndev);
|
return 0;
|
}
|
|
static int __maybe_unused rcar_can_suspend(struct device *dev)
|
{
|
struct net_device *ndev = dev_get_drvdata(dev);
|
struct rcar_can_priv *priv = netdev_priv(ndev);
|
u16 ctlr;
|
|
if (!netif_running(ndev))
|
return 0;
|
|
netif_stop_queue(ndev);
|
netif_device_detach(ndev);
|
|
ctlr = readw(&priv->regs->ctlr);
|
ctlr |= RCAR_CAN_CTLR_CANM_HALT;
|
writew(ctlr, &priv->regs->ctlr);
|
ctlr |= RCAR_CAN_CTLR_SLPM;
|
writew(ctlr, &priv->regs->ctlr);
|
priv->can.state = CAN_STATE_SLEEPING;
|
|
clk_disable(priv->clk);
|
return 0;
|
}
|
|
static int __maybe_unused rcar_can_resume(struct device *dev)
|
{
|
struct net_device *ndev = dev_get_drvdata(dev);
|
struct rcar_can_priv *priv = netdev_priv(ndev);
|
u16 ctlr;
|
int err;
|
|
if (!netif_running(ndev))
|
return 0;
|
|
err = clk_enable(priv->clk);
|
if (err) {
|
netdev_err(ndev, "clk_enable() failed, error %d\n", err);
|
return err;
|
}
|
|
ctlr = readw(&priv->regs->ctlr);
|
ctlr &= ~RCAR_CAN_CTLR_SLPM;
|
writew(ctlr, &priv->regs->ctlr);
|
ctlr &= ~RCAR_CAN_CTLR_CANM;
|
writew(ctlr, &priv->regs->ctlr);
|
priv->can.state = CAN_STATE_ERROR_ACTIVE;
|
|
netif_device_attach(ndev);
|
netif_start_queue(ndev);
|
|
return 0;
|
}
|
|
static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume);
|
|
static const struct of_device_id rcar_can_of_table[] __maybe_unused = {
|
{ .compatible = "renesas,can-r8a7778" },
|
{ .compatible = "renesas,can-r8a7779" },
|
{ .compatible = "renesas,can-r8a7790" },
|
{ .compatible = "renesas,can-r8a7791" },
|
{ .compatible = "renesas,rcar-gen1-can" },
|
{ .compatible = "renesas,rcar-gen2-can" },
|
{ .compatible = "renesas,rcar-gen3-can" },
|
{ }
|
};
|
MODULE_DEVICE_TABLE(of, rcar_can_of_table);
|
|
static struct platform_driver rcar_can_driver = {
|
.driver = {
|
.name = RCAR_CAN_DRV_NAME,
|
.of_match_table = of_match_ptr(rcar_can_of_table),
|
.pm = &rcar_can_pm_ops,
|
},
|
.probe = rcar_can_probe,
|
.remove = rcar_can_remove,
|
};
|
|
module_platform_driver(rcar_can_driver);
|
|
MODULE_AUTHOR("Cogent Embedded, Inc.");
|
MODULE_LICENSE("GPL");
|
MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC");
|
MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME);
|
