// SPDX-License-Identifier: GPL-2.0-or-later
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/* stk-sensor.c: Driver for ov96xx sensor (used in some Syntek webcams)
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*
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* Copyright 2007-2008 Jaime Velasco Juan <jsagarribay@gmail.com>
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*
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* Some parts derived from ov7670.c:
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* Copyright 2006 One Laptop Per Child Association, Inc. Written
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* by Jonathan Corbet with substantial inspiration from Mark
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* McClelland's ovcamchip code.
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*
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* Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
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*
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* This file may be distributed under the terms of the GNU General
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*/
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/* Controlling the sensor via the STK1125 vendor specific control interface:
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* The camera uses an OmniVision sensor and the stk1125 provides an
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* SCCB(i2c)-USB bridge which let us program the sensor.
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* In my case the sensor id is 0x9652, it can be read from sensor's register
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* 0x0A and 0x0B as follows:
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* - read register #R:
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* output #R to index 0x0208
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* output 0x0070 to index 0x0200
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* input 1 byte from index 0x0201 (some kind of status register)
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* until its value is 0x01
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* input 1 byte from index 0x0209. This is the value of #R
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* - write value V to register #R
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* output #R to index 0x0204
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* output V to index 0x0205
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* output 0x0005 to index 0x0200
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* input 1 byte from index 0x0201 until its value becomes 0x04
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*/
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/* It seems the i2c bus is controlled with these registers */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include "stk-webcam.h"
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#define STK_IIC_BASE (0x0200)
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# define STK_IIC_OP (STK_IIC_BASE)
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# define STK_IIC_OP_TX (0x05)
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# define STK_IIC_OP_RX (0x70)
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# define STK_IIC_STAT (STK_IIC_BASE+1)
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# define STK_IIC_STAT_TX_OK (0x04)
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# define STK_IIC_STAT_RX_OK (0x01)
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/* I don't know what does this register.
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* when it is 0x00 or 0x01, we cannot talk to the sensor,
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* other values work */
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# define STK_IIC_ENABLE (STK_IIC_BASE+2)
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# define STK_IIC_ENABLE_NO (0x00)
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/* This is what the driver writes in windows */
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# define STK_IIC_ENABLE_YES (0x1e)
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/*
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* Address of the slave. Seems like the binary driver look for the
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* sensor in multiple places, attempting a reset sequence.
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* We only know about the ov9650
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*/
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# define STK_IIC_ADDR (STK_IIC_BASE+3)
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# define STK_IIC_TX_INDEX (STK_IIC_BASE+4)
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# define STK_IIC_TX_VALUE (STK_IIC_BASE+5)
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# define STK_IIC_RX_INDEX (STK_IIC_BASE+8)
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# define STK_IIC_RX_VALUE (STK_IIC_BASE+9)
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#define MAX_RETRIES (50)
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#define SENSOR_ADDRESS (0x60)
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/* From ov7670.c (These registers aren't fully accurate) */
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/* Registers */
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#define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
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#define REG_BLUE 0x01 /* blue gain */
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#define REG_RED 0x02 /* red gain */
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#define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
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#define REG_COM1 0x04 /* Control 1 */
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#define COM1_CCIR656 0x40 /* CCIR656 enable */
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#define COM1_QFMT 0x20 /* QVGA/QCIF format */
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#define COM1_SKIP_0 0x00 /* Do not skip any row */
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#define COM1_SKIP_2 0x04 /* Skip 2 rows of 4 */
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#define COM1_SKIP_3 0x08 /* Skip 3 rows of 4 */
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#define REG_BAVE 0x05 /* U/B Average level */
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#define REG_GbAVE 0x06 /* Y/Gb Average level */
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#define REG_AECHH 0x07 /* AEC MS 5 bits */
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#define REG_RAVE 0x08 /* V/R Average level */
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#define REG_COM2 0x09 /* Control 2 */
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#define COM2_SSLEEP 0x10 /* Soft sleep mode */
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#define REG_PID 0x0a /* Product ID MSB */
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#define REG_VER 0x0b /* Product ID LSB */
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#define REG_COM3 0x0c /* Control 3 */
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#define COM3_SWAP 0x40 /* Byte swap */
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#define COM3_SCALEEN 0x08 /* Enable scaling */
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#define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
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#define REG_COM4 0x0d /* Control 4 */
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#define REG_COM5 0x0e /* All "reserved" */
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#define REG_COM6 0x0f /* Control 6 */
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#define REG_AECH 0x10 /* More bits of AEC value */
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#define REG_CLKRC 0x11 /* Clock control */
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#define CLK_PLL 0x80 /* Enable internal PLL */
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#define CLK_EXT 0x40 /* Use external clock directly */
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#define CLK_SCALE 0x3f /* Mask for internal clock scale */
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#define REG_COM7 0x12 /* Control 7 */
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#define COM7_RESET 0x80 /* Register reset */
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#define COM7_FMT_MASK 0x38
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#define COM7_FMT_SXGA 0x00
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#define COM7_FMT_VGA 0x40
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#define COM7_FMT_CIF 0x20 /* CIF format */
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#define COM7_FMT_QVGA 0x10 /* QVGA format */
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#define COM7_FMT_QCIF 0x08 /* QCIF format */
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#define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
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#define COM7_YUV 0x00 /* YUV */
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#define COM7_BAYER 0x01 /* Bayer format */
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#define COM7_PBAYER 0x05 /* "Processed bayer" */
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#define REG_COM8 0x13 /* Control 8 */
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#define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
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#define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
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#define COM8_BFILT 0x20 /* Band filter enable */
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#define COM8_AGC 0x04 /* Auto gain enable */
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#define COM8_AWB 0x02 /* White balance enable */
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#define COM8_AEC 0x01 /* Auto exposure enable */
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#define REG_COM9 0x14 /* Control 9 - gain ceiling */
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#define REG_COM10 0x15 /* Control 10 */
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#define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
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#define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
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#define COM10_HREF_REV 0x08 /* Reverse HREF */
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#define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
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#define COM10_VS_NEG 0x02 /* VSYNC negative */
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#define COM10_HS_NEG 0x01 /* HSYNC negative */
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#define REG_HSTART 0x17 /* Horiz start high bits */
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#define REG_HSTOP 0x18 /* Horiz stop high bits */
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#define REG_VSTART 0x19 /* Vert start high bits */
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#define REG_VSTOP 0x1a /* Vert stop high bits */
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#define REG_PSHFT 0x1b /* Pixel delay after HREF */
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#define REG_MIDH 0x1c /* Manuf. ID high */
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#define REG_MIDL 0x1d /* Manuf. ID low */
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#define REG_MVFP 0x1e /* Mirror / vflip */
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#define MVFP_MIRROR 0x20 /* Mirror image */
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#define MVFP_FLIP 0x10 /* Vertical flip */
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#define REG_AEW 0x24 /* AGC upper limit */
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#define REG_AEB 0x25 /* AGC lower limit */
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#define REG_VPT 0x26 /* AGC/AEC fast mode op region */
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#define REG_ADVFL 0x2d /* Insert dummy lines (LSB) */
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#define REG_ADVFH 0x2e /* Insert dummy lines (MSB) */
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#define REG_HSYST 0x30 /* HSYNC rising edge delay */
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#define REG_HSYEN 0x31 /* HSYNC falling edge delay */
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#define REG_HREF 0x32 /* HREF pieces */
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#define REG_TSLB 0x3a /* lots of stuff */
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#define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
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#define TSLB_BYTEORD 0x08 /* swap bytes in 16bit mode? */
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#define REG_COM11 0x3b /* Control 11 */
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#define COM11_NIGHT 0x80 /* NIght mode enable */
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#define COM11_NMFR 0x60 /* Two bit NM frame rate */
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#define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
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#define COM11_50HZ 0x08 /* Manual 50Hz select */
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#define COM11_EXP 0x02
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#define REG_COM12 0x3c /* Control 12 */
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#define COM12_HREF 0x80 /* HREF always */
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#define REG_COM13 0x3d /* Control 13 */
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#define COM13_GAMMA 0x80 /* Gamma enable */
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#define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
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#define COM13_CMATRIX 0x10 /* Enable color matrix for RGB or YUV */
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#define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
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#define REG_COM14 0x3e /* Control 14 */
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#define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
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#define REG_EDGE 0x3f /* Edge enhancement factor */
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#define REG_COM15 0x40 /* Control 15 */
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#define COM15_R10F0 0x00 /* Data range 10 to F0 */
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#define COM15_R01FE 0x80 /* 01 to FE */
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#define COM15_R00FF 0xc0 /* 00 to FF */
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#define COM15_RGB565 0x10 /* RGB565 output */
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#define COM15_RGBFIXME 0x20 /* FIXME */
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#define COM15_RGB555 0x30 /* RGB555 output */
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#define REG_COM16 0x41 /* Control 16 */
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#define COM16_AWBGAIN 0x08 /* AWB gain enable */
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#define REG_COM17 0x42 /* Control 17 */
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#define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
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#define COM17_CBAR 0x08 /* DSP Color bar */
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/*
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* This matrix defines how the colors are generated, must be
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* tweaked to adjust hue and saturation.
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*
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* Order: v-red, v-green, v-blue, u-red, u-green, u-blue
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*
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* They are nine-bit signed quantities, with the sign bit
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* stored in 0x58. Sign for v-red is bit 0, and up from there.
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*/
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#define REG_CMATRIX_BASE 0x4f
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#define CMATRIX_LEN 6
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#define REG_CMATRIX_SIGN 0x58
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#define REG_BRIGHT 0x55 /* Brightness */
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#define REG_CONTRAS 0x56 /* Contrast control */
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#define REG_GFIX 0x69 /* Fix gain control */
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#define REG_RGB444 0x8c /* RGB 444 control */
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#define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
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#define R444_RGBX 0x01 /* Empty nibble at end */
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#define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
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#define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
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#define REG_BD50MAX 0xa5 /* 50hz banding step limit */
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#define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
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#define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
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#define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
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#define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
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#define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
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#define REG_BD60MAX 0xab /* 60hz banding step limit */
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/* Returns 0 if OK */
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static int stk_sensor_outb(struct stk_camera *dev, u8 reg, u8 val)
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{
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int i = 0;
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u8 tmpval = 0;
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if (stk_camera_write_reg(dev, STK_IIC_TX_INDEX, reg))
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return 1;
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if (stk_camera_write_reg(dev, STK_IIC_TX_VALUE, val))
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return 1;
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if (stk_camera_write_reg(dev, STK_IIC_OP, STK_IIC_OP_TX))
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return 1;
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do {
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if (stk_camera_read_reg(dev, STK_IIC_STAT, &tmpval))
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return 1;
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i++;
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} while (tmpval == 0 && i < MAX_RETRIES);
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if (tmpval != STK_IIC_STAT_TX_OK) {
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if (tmpval)
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pr_err("stk_sensor_outb failed, status=0x%02x\n",
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tmpval);
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return 1;
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} else
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return 0;
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}
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static int stk_sensor_inb(struct stk_camera *dev, u8 reg, u8 *val)
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{
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int i = 0;
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u8 tmpval = 0;
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if (stk_camera_write_reg(dev, STK_IIC_RX_INDEX, reg))
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return 1;
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if (stk_camera_write_reg(dev, STK_IIC_OP, STK_IIC_OP_RX))
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return 1;
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do {
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if (stk_camera_read_reg(dev, STK_IIC_STAT, &tmpval))
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return 1;
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i++;
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} while (tmpval == 0 && i < MAX_RETRIES);
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if (tmpval != STK_IIC_STAT_RX_OK) {
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if (tmpval)
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pr_err("stk_sensor_inb failed, status=0x%02x\n",
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tmpval);
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return 1;
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}
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if (stk_camera_read_reg(dev, STK_IIC_RX_VALUE, &tmpval))
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return 1;
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*val = tmpval;
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return 0;
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}
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static int stk_sensor_write_regvals(struct stk_camera *dev,
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struct regval *rv)
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{
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int ret;
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if (rv == NULL)
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return 0;
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while (rv->reg != 0xff || rv->val != 0xff) {
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ret = stk_sensor_outb(dev, rv->reg, rv->val);
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if (ret != 0)
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return ret;
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rv++;
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}
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return 0;
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}
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int stk_sensor_sleep(struct stk_camera *dev)
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{
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u8 tmp;
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return stk_sensor_inb(dev, REG_COM2, &tmp)
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|| stk_sensor_outb(dev, REG_COM2, tmp|COM2_SSLEEP);
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}
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int stk_sensor_wakeup(struct stk_camera *dev)
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{
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u8 tmp;
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return stk_sensor_inb(dev, REG_COM2, &tmp)
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|| stk_sensor_outb(dev, REG_COM2, tmp&~COM2_SSLEEP);
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}
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static struct regval ov_initvals[] = {
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{REG_CLKRC, CLK_PLL},
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{REG_COM11, 0x01},
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{0x6a, 0x7d},
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{REG_AECH, 0x40},
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{REG_GAIN, 0x00},
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{REG_BLUE, 0x80},
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{REG_RED, 0x80},
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/* Do not enable fast AEC for now */
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/*{REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC},*/
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{REG_COM8, COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC},
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{0x39, 0x50}, {0x38, 0x93},
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{0x37, 0x00}, {0x35, 0x81},
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{REG_COM5, 0x20},
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{REG_COM1, 0x00},
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{REG_COM3, 0x00},
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{REG_COM4, 0x00},
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{REG_PSHFT, 0x00},
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{0x16, 0x07},
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{0x33, 0xe2}, {0x34, 0xbf},
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{REG_COM16, 0x00},
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{0x96, 0x04},
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/* Gamma curve values */
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/* { 0x7a, 0x20 }, { 0x7b, 0x10 },
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{ 0x7c, 0x1e }, { 0x7d, 0x35 },
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{ 0x7e, 0x5a }, { 0x7f, 0x69 },
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{ 0x80, 0x76 }, { 0x81, 0x80 },
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{ 0x82, 0x88 }, { 0x83, 0x8f },
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{ 0x84, 0x96 }, { 0x85, 0xa3 },
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{ 0x86, 0xaf }, { 0x87, 0xc4 },
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{ 0x88, 0xd7 }, { 0x89, 0xe8 },
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*/
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{REG_GFIX, 0x40},
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{0x8e, 0x00},
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{REG_COM12, 0x73},
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{0x8f, 0xdf}, {0x8b, 0x06},
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{0x8c, 0x20},
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{0x94, 0x88}, {0x95, 0x88},
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/* {REG_COM15, 0xc1}, TODO */
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{0x29, 0x3f},
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{REG_COM6, 0x42},
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{REG_BD50MAX, 0x80},
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{REG_HAECC6, 0xb8}, {REG_HAECC7, 0x92},
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{REG_BD60MAX, 0x0a},
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{0x90, 0x00}, {0x91, 0x00},
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{REG_HAECC1, 0x00}, {REG_HAECC2, 0x00},
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{REG_AEW, 0x68}, {REG_AEB, 0x5c},
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{REG_VPT, 0xc3},
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{REG_COM9, 0x2e},
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{0x2a, 0x00}, {0x2b, 0x00},
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{0xff, 0xff}, /* END MARKER */
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};
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/* Probe the I2C bus and initialise the sensor chip */
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int stk_sensor_init(struct stk_camera *dev)
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{
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u8 idl = 0;
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u8 idh = 0;
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if (stk_camera_write_reg(dev, STK_IIC_ENABLE, STK_IIC_ENABLE_YES)
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|| stk_camera_write_reg(dev, STK_IIC_ADDR, SENSOR_ADDRESS)
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|| stk_sensor_outb(dev, REG_COM7, COM7_RESET)) {
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pr_err("Sensor resetting failed\n");
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return -ENODEV;
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}
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msleep(10);
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/* Read the manufacturer ID: ov = 0x7FA2 */
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if (stk_sensor_inb(dev, REG_MIDH, &idh)
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|| stk_sensor_inb(dev, REG_MIDL, &idl)) {
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pr_err("Strange error reading sensor ID\n");
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return -ENODEV;
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}
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if (idh != 0x7f || idl != 0xa2) {
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pr_err("Huh? you don't have a sensor from ovt\n");
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return -ENODEV;
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}
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if (stk_sensor_inb(dev, REG_PID, &idh)
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|| stk_sensor_inb(dev, REG_VER, &idl)) {
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pr_err("Could not read sensor model\n");
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return -ENODEV;
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}
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stk_sensor_write_regvals(dev, ov_initvals);
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msleep(10);
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pr_info("OmniVision sensor detected, id %02X%02X at address %x\n",
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idh, idl, SENSOR_ADDRESS);
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return 0;
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}
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/* V4L2_PIX_FMT_UYVY */
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static struct regval ov_fmt_uyvy[] = {
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{REG_TSLB, TSLB_YLAST|0x08 },
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{ 0x4f, 0x80 }, /* "matrix coefficient 1" */
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{ 0x50, 0x80 }, /* "matrix coefficient 2" */
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{ 0x51, 0 }, /* vb */
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{ 0x52, 0x22 }, /* "matrix coefficient 4" */
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{ 0x53, 0x5e }, /* "matrix coefficient 5" */
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{ 0x54, 0x80 }, /* "matrix coefficient 6" */
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{REG_COM13, COM13_UVSAT|COM13_CMATRIX},
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{REG_COM15, COM15_R00FF },
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{0xff, 0xff}, /* END MARKER */
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};
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/* V4L2_PIX_FMT_YUYV */
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static struct regval ov_fmt_yuyv[] = {
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{REG_TSLB, 0 },
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{ 0x4f, 0x80 }, /* "matrix coefficient 1" */
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{ 0x50, 0x80 }, /* "matrix coefficient 2" */
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{ 0x51, 0 }, /* vb */
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{ 0x52, 0x22 }, /* "matrix coefficient 4" */
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{ 0x53, 0x5e }, /* "matrix coefficient 5" */
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{ 0x54, 0x80 }, /* "matrix coefficient 6" */
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{REG_COM13, COM13_UVSAT|COM13_CMATRIX},
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{REG_COM15, COM15_R00FF },
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{0xff, 0xff}, /* END MARKER */
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};
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/* V4L2_PIX_FMT_RGB565X rrrrrggg gggbbbbb */
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static struct regval ov_fmt_rgbr[] = {
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{ REG_RGB444, 0 }, /* No RGB444 please */
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{REG_TSLB, 0x00},
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{ REG_COM1, 0x0 },
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{ REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
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{ 0x4f, 0xb3 }, /* "matrix coefficient 1" */
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{ 0x50, 0xb3 }, /* "matrix coefficient 2" */
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{ 0x51, 0 }, /* vb */
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{ 0x52, 0x3d }, /* "matrix coefficient 4" */
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{ 0x53, 0xa7 }, /* "matrix coefficient 5" */
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{ 0x54, 0xe4 }, /* "matrix coefficient 6" */
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{ REG_COM13, COM13_GAMMA },
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{ REG_COM15, COM15_RGB565|COM15_R00FF },
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{ 0xff, 0xff },
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};
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/* V4L2_PIX_FMT_RGB565 gggbbbbb rrrrrggg */
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static struct regval ov_fmt_rgbp[] = {
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{ REG_RGB444, 0 }, /* No RGB444 please */
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{REG_TSLB, TSLB_BYTEORD },
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{ REG_COM1, 0x0 },
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{ REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
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{ 0x4f, 0xb3 }, /* "matrix coefficient 1" */
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{ 0x50, 0xb3 }, /* "matrix coefficient 2" */
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{ 0x51, 0 }, /* vb */
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{ 0x52, 0x3d }, /* "matrix coefficient 4" */
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{ 0x53, 0xa7 }, /* "matrix coefficient 5" */
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{ 0x54, 0xe4 }, /* "matrix coefficient 6" */
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{ REG_COM13, COM13_GAMMA },
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{ REG_COM15, COM15_RGB565|COM15_R00FF },
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{ 0xff, 0xff },
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};
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/* V4L2_PIX_FMT_SRGGB8 */
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static struct regval ov_fmt_bayer[] = {
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/* This changes color order */
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{REG_TSLB, 0x40}, /* BGGR */
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/* {REG_TSLB, 0x08}, */ /* BGGR with vertical image flipping */
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{REG_COM15, COM15_R00FF },
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{0xff, 0xff}, /* END MARKER */
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};
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/*
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* Store a set of start/stop values into the camera.
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*/
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static int stk_sensor_set_hw(struct stk_camera *dev,
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int hstart, int hstop, int vstart, int vstop)
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{
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int ret;
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unsigned char v;
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/*
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* Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
|
* hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
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* a mystery "edge offset" value in the top two bits of href.
|
*/
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ret = stk_sensor_outb(dev, REG_HSTART, (hstart >> 3) & 0xff);
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ret += stk_sensor_outb(dev, REG_HSTOP, (hstop >> 3) & 0xff);
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ret += stk_sensor_inb(dev, REG_HREF, &v);
|
v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
|
msleep(10);
|
ret += stk_sensor_outb(dev, REG_HREF, v);
|
/*
|
* Vertical: similar arrangement (note: this is different from ov7670.c)
|
*/
|
ret += stk_sensor_outb(dev, REG_VSTART, (vstart >> 3) & 0xff);
|
ret += stk_sensor_outb(dev, REG_VSTOP, (vstop >> 3) & 0xff);
|
ret += stk_sensor_inb(dev, REG_VREF, &v);
|
v = (v & 0xc0) | ((vstop & 0x7) << 3) | (vstart & 0x7);
|
msleep(10);
|
ret += stk_sensor_outb(dev, REG_VREF, v);
|
return ret;
|
}
|
|
|
int stk_sensor_configure(struct stk_camera *dev)
|
{
|
int com7;
|
/*
|
* We setup the sensor to output dummy lines in low-res modes,
|
* so we don't get absurdly hight framerates.
|
*/
|
unsigned dummylines;
|
int flip;
|
struct regval *rv;
|
|
switch (dev->vsettings.mode) {
|
case MODE_QCIF: com7 = COM7_FMT_QCIF;
|
dummylines = 604;
|
break;
|
case MODE_QVGA: com7 = COM7_FMT_QVGA;
|
dummylines = 267;
|
break;
|
case MODE_CIF: com7 = COM7_FMT_CIF;
|
dummylines = 412;
|
break;
|
case MODE_VGA: com7 = COM7_FMT_VGA;
|
dummylines = 11;
|
break;
|
case MODE_SXGA: com7 = COM7_FMT_SXGA;
|
dummylines = 0;
|
break;
|
default:
|
pr_err("Unsupported mode %d\n", dev->vsettings.mode);
|
return -EFAULT;
|
}
|
switch (dev->vsettings.palette) {
|
case V4L2_PIX_FMT_UYVY:
|
com7 |= COM7_YUV;
|
rv = ov_fmt_uyvy;
|
break;
|
case V4L2_PIX_FMT_YUYV:
|
com7 |= COM7_YUV;
|
rv = ov_fmt_yuyv;
|
break;
|
case V4L2_PIX_FMT_RGB565:
|
com7 |= COM7_RGB;
|
rv = ov_fmt_rgbp;
|
break;
|
case V4L2_PIX_FMT_RGB565X:
|
com7 |= COM7_RGB;
|
rv = ov_fmt_rgbr;
|
break;
|
case V4L2_PIX_FMT_SBGGR8:
|
com7 |= COM7_PBAYER;
|
rv = ov_fmt_bayer;
|
break;
|
default:
|
pr_err("Unsupported colorspace\n");
|
return -EFAULT;
|
}
|
/*FIXME sometimes the sensor go to a bad state
|
stk_sensor_write_regvals(dev, ov_initvals); */
|
stk_sensor_outb(dev, REG_COM7, com7);
|
msleep(50);
|
stk_sensor_write_regvals(dev, rv);
|
flip = (dev->vsettings.vflip?MVFP_FLIP:0)
|
| (dev->vsettings.hflip?MVFP_MIRROR:0);
|
stk_sensor_outb(dev, REG_MVFP, flip);
|
if (dev->vsettings.palette == V4L2_PIX_FMT_SBGGR8
|
&& !dev->vsettings.vflip)
|
stk_sensor_outb(dev, REG_TSLB, 0x08);
|
stk_sensor_outb(dev, REG_ADVFH, dummylines >> 8);
|
stk_sensor_outb(dev, REG_ADVFL, dummylines & 0xff);
|
msleep(50);
|
switch (dev->vsettings.mode) {
|
case MODE_VGA:
|
if (stk_sensor_set_hw(dev, 302, 1582, 6, 486))
|
pr_err("stk_sensor_set_hw failed (VGA)\n");
|
break;
|
case MODE_SXGA:
|
case MODE_CIF:
|
case MODE_QVGA:
|
case MODE_QCIF:
|
/*FIXME These settings seem ignored by the sensor
|
if (stk_sensor_set_hw(dev, 220, 1500, 10, 1034))
|
pr_err("stk_sensor_set_hw failed (SXGA)\n");
|
*/
|
break;
|
}
|
msleep(10);
|
return 0;
|
}
|
|
int stk_sensor_set_brightness(struct stk_camera *dev, int br)
|
{
|
if (br < 0 || br > 0xff)
|
return -EINVAL;
|
stk_sensor_outb(dev, REG_AEB, max(0x00, br - 6));
|
stk_sensor_outb(dev, REG_AEW, min(0xff, br + 6));
|
return 0;
|
}
|
