/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Xilinx Video IP Composite Device
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*
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* Copyright (C) 2013-2015 Ideas on Board
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* Copyright (C) 2013-2015 Xilinx, Inc.
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*
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* Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
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* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#ifndef __XILINX_VIPP_H__
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#define __XILINX_VIPP_H__
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <media/media-device.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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/**
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* struct xvip_composite_device - Xilinx Video IP device structure
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* @v4l2_dev: V4L2 device
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* @media_dev: media device
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* @dev: (OF) device
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* @notifier: V4L2 asynchronous subdevs notifier
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* @dmas: list of DMA channels at the pipeline output and input
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* @v4l2_caps: V4L2 capabilities of the whole device (see VIDIOC_QUERYCAP)
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*/
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struct xvip_composite_device {
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struct v4l2_device v4l2_dev;
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struct media_device media_dev;
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struct device *dev;
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struct v4l2_async_notifier notifier;
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struct list_head dmas;
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u32 v4l2_caps;
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};
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#endif /* __XILINX_VIPP_H__ */
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