/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Xilinx Video IP Core
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*
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* Copyright (C) 2013-2015 Ideas on Board
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* Copyright (C) 2013-2015 Xilinx, Inc.
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*
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* Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
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* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#ifndef __XILINX_VIP_H__
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#define __XILINX_VIP_H__
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <media/v4l2-subdev.h>
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struct clk;
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/*
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* Minimum and maximum width and height common to most video IP cores. IP
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* cores with different requirements must define their own values.
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*/
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#define XVIP_MIN_WIDTH 32
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#define XVIP_MAX_WIDTH 7680
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#define XVIP_MIN_HEIGHT 32
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#define XVIP_MAX_HEIGHT 7680
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/*
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* Pad IDs. IP cores with with multiple inputs or outputs should define
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* their own values.
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*/
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#define XVIP_PAD_SINK 0
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#define XVIP_PAD_SOURCE 1
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/* Xilinx Video IP Control Registers */
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#define XVIP_CTRL_CONTROL 0x0000
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#define XVIP_CTRL_CONTROL_SW_ENABLE BIT(0)
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#define XVIP_CTRL_CONTROL_REG_UPDATE BIT(1)
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#define XVIP_CTRL_CONTROL_BYPASS BIT(4)
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#define XVIP_CTRL_CONTROL_TEST_PATTERN BIT(5)
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#define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET BIT(30)
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#define XVIP_CTRL_CONTROL_SW_RESET BIT(31)
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#define XVIP_CTRL_STATUS 0x0004
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#define XVIP_CTRL_STATUS_PROC_STARTED BIT(0)
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#define XVIP_CTRL_STATUS_EOF BIT(1)
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#define XVIP_CTRL_ERROR 0x0008
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#define XVIP_CTRL_ERROR_SLAVE_EOL_EARLY BIT(0)
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#define XVIP_CTRL_ERROR_SLAVE_EOL_LATE BIT(1)
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#define XVIP_CTRL_ERROR_SLAVE_SOF_EARLY BIT(2)
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#define XVIP_CTRL_ERROR_SLAVE_SOF_LATE BIT(3)
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#define XVIP_CTRL_IRQ_ENABLE 0x000c
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#define XVIP_CTRL_IRQ_ENABLE_PROC_STARTED BIT(0)
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#define XVIP_CTRL_IRQ_EOF BIT(1)
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#define XVIP_CTRL_VERSION 0x0010
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#define XVIP_CTRL_VERSION_MAJOR_MASK (0xff << 24)
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#define XVIP_CTRL_VERSION_MAJOR_SHIFT 24
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#define XVIP_CTRL_VERSION_MINOR_MASK (0xff << 16)
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#define XVIP_CTRL_VERSION_MINOR_SHIFT 16
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#define XVIP_CTRL_VERSION_REVISION_MASK (0xf << 12)
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#define XVIP_CTRL_VERSION_REVISION_SHIFT 12
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#define XVIP_CTRL_VERSION_PATCH_MASK (0xf << 8)
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#define XVIP_CTRL_VERSION_PATCH_SHIFT 8
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#define XVIP_CTRL_VERSION_INTERNAL_MASK (0xff << 0)
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#define XVIP_CTRL_VERSION_INTERNAL_SHIFT 0
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/* Xilinx Video IP Timing Registers */
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#define XVIP_ACTIVE_SIZE 0x0020
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#define XVIP_ACTIVE_VSIZE_MASK (0x7ff << 16)
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#define XVIP_ACTIVE_VSIZE_SHIFT 16
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#define XVIP_ACTIVE_HSIZE_MASK (0x7ff << 0)
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#define XVIP_ACTIVE_HSIZE_SHIFT 0
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#define XVIP_ENCODING 0x0028
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#define XVIP_ENCODING_NBITS_8 (0 << 4)
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#define XVIP_ENCODING_NBITS_10 (1 << 4)
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#define XVIP_ENCODING_NBITS_12 (2 << 4)
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#define XVIP_ENCODING_NBITS_16 (3 << 4)
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#define XVIP_ENCODING_NBITS_MASK (3 << 4)
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#define XVIP_ENCODING_NBITS_SHIFT 4
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#define XVIP_ENCODING_VIDEO_FORMAT_YUV422 (0 << 0)
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#define XVIP_ENCODING_VIDEO_FORMAT_YUV444 (1 << 0)
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#define XVIP_ENCODING_VIDEO_FORMAT_RGB (2 << 0)
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#define XVIP_ENCODING_VIDEO_FORMAT_YUV420 (3 << 0)
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#define XVIP_ENCODING_VIDEO_FORMAT_MASK (3 << 0)
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#define XVIP_ENCODING_VIDEO_FORMAT_SHIFT 0
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/**
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* struct xvip_device - Xilinx Video IP device structure
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* @subdev: V4L2 subdevice
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* @dev: (OF) device
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* @iomem: device I/O register space remapped to kernel virtual memory
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* @clk: video core clock
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* @saved_ctrl: saved control register for resume / suspend
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*/
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struct xvip_device {
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struct v4l2_subdev subdev;
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struct device *dev;
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void __iomem *iomem;
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struct clk *clk;
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u32 saved_ctrl;
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};
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/**
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* struct xvip_video_format - Xilinx Video IP video format description
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* @vf_code: AXI4 video format code
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* @width: AXI4 format width in bits per component
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* @pattern: CFA pattern for Mono/Sensor formats
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* @code: media bus format code
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* @bpp: bytes per pixel (when stored in memory)
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* @fourcc: V4L2 pixel format FCC identifier
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*/
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struct xvip_video_format {
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unsigned int vf_code;
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unsigned int width;
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const char *pattern;
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unsigned int code;
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unsigned int bpp;
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u32 fourcc;
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};
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const struct xvip_video_format *xvip_get_format_by_code(unsigned int code);
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const struct xvip_video_format *xvip_get_format_by_fourcc(u32 fourcc);
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const struct xvip_video_format *xvip_of_get_format(struct device_node *node);
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void xvip_set_format_size(struct v4l2_mbus_framefmt *format,
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const struct v4l2_subdev_format *fmt);
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int xvip_enum_mbus_code(struct v4l2_subdev *subdev,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_mbus_code_enum *code);
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int xvip_enum_frame_size(struct v4l2_subdev *subdev,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_frame_size_enum *fse);
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static inline u32 xvip_read(struct xvip_device *xvip, u32 addr)
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{
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return ioread32(xvip->iomem + addr);
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}
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static inline void xvip_write(struct xvip_device *xvip, u32 addr, u32 value)
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{
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iowrite32(value, xvip->iomem + addr);
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}
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static inline void xvip_clr(struct xvip_device *xvip, u32 addr, u32 clr)
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{
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xvip_write(xvip, addr, xvip_read(xvip, addr) & ~clr);
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}
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static inline void xvip_set(struct xvip_device *xvip, u32 addr, u32 set)
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{
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xvip_write(xvip, addr, xvip_read(xvip, addr) | set);
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}
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void xvip_clr_or_set(struct xvip_device *xvip, u32 addr, u32 mask, bool set);
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void xvip_clr_and_set(struct xvip_device *xvip, u32 addr, u32 clr, u32 set);
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int xvip_init_resources(struct xvip_device *xvip);
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void xvip_cleanup_resources(struct xvip_device *xvip);
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static inline void xvip_reset(struct xvip_device *xvip)
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{
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xvip_write(xvip, XVIP_CTRL_CONTROL, XVIP_CTRL_CONTROL_SW_RESET);
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}
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static inline void xvip_start(struct xvip_device *xvip)
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{
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xvip_set(xvip, XVIP_CTRL_CONTROL,
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XVIP_CTRL_CONTROL_SW_ENABLE | XVIP_CTRL_CONTROL_REG_UPDATE);
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}
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static inline void xvip_stop(struct xvip_device *xvip)
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{
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xvip_clr(xvip, XVIP_CTRL_CONTROL, XVIP_CTRL_CONTROL_SW_ENABLE);
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}
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static inline void xvip_resume(struct xvip_device *xvip)
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{
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xvip_write(xvip, XVIP_CTRL_CONTROL,
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xvip->saved_ctrl | XVIP_CTRL_CONTROL_SW_ENABLE);
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}
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static inline void xvip_suspend(struct xvip_device *xvip)
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{
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xvip->saved_ctrl = xvip_read(xvip, XVIP_CTRL_CONTROL);
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xvip_write(xvip, XVIP_CTRL_CONTROL,
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xvip->saved_ctrl & ~XVIP_CTRL_CONTROL_SW_ENABLE);
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}
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static inline void xvip_set_frame_size(struct xvip_device *xvip,
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const struct v4l2_mbus_framefmt *format)
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{
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xvip_write(xvip, XVIP_ACTIVE_SIZE,
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(format->height << XVIP_ACTIVE_VSIZE_SHIFT) |
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(format->width << XVIP_ACTIVE_HSIZE_SHIFT));
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}
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static inline void xvip_get_frame_size(struct xvip_device *xvip,
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struct v4l2_mbus_framefmt *format)
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{
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u32 reg;
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reg = xvip_read(xvip, XVIP_ACTIVE_SIZE);
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format->width = (reg & XVIP_ACTIVE_HSIZE_MASK) >>
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XVIP_ACTIVE_HSIZE_SHIFT;
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format->height = (reg & XVIP_ACTIVE_VSIZE_MASK) >>
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XVIP_ACTIVE_VSIZE_SHIFT;
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}
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static inline void xvip_enable_reg_update(struct xvip_device *xvip)
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{
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xvip_set(xvip, XVIP_CTRL_CONTROL, XVIP_CTRL_CONTROL_REG_UPDATE);
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}
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static inline void xvip_disable_reg_update(struct xvip_device *xvip)
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{
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xvip_clr(xvip, XVIP_CTRL_CONTROL, XVIP_CTRL_CONTROL_REG_UPDATE);
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}
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static inline void xvip_print_version(struct xvip_device *xvip)
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{
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u32 version;
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version = xvip_read(xvip, XVIP_CTRL_VERSION);
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dev_info(xvip->dev, "device found, version %u.%02x%x\n",
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((version & XVIP_CTRL_VERSION_MAJOR_MASK) >>
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XVIP_CTRL_VERSION_MAJOR_SHIFT),
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((version & XVIP_CTRL_VERSION_MINOR_MASK) >>
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XVIP_CTRL_VERSION_MINOR_SHIFT),
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((version & XVIP_CTRL_VERSION_REVISION_MASK) >>
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XVIP_CTRL_VERSION_REVISION_SHIFT));
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}
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#endif /* __XILINX_VIP_H__ */
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