// SPDX-License-Identifier: GPL-2.0+
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/*
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* vsp1_brx.c -- R-Car VSP1 Blend ROP Unit (BRU and BRS)
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*
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* Copyright (C) 2013 Renesas Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*/
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#include <linux/device.h>
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#include <linux/gfp.h>
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#include <media/v4l2-subdev.h>
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#include "vsp1.h"
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#include "vsp1_brx.h"
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#include "vsp1_dl.h"
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#include "vsp1_pipe.h"
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#include "vsp1_rwpf.h"
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#include "vsp1_video.h"
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#define BRX_MIN_SIZE 1U
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#define BRX_MAX_SIZE 8190U
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/* -----------------------------------------------------------------------------
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* Device Access
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*/
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static inline void vsp1_brx_write(struct vsp1_brx *brx,
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struct vsp1_dl_body *dlb, u32 reg, u32 data)
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{
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vsp1_dl_body_write(dlb, brx->base + reg, data);
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}
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/* -----------------------------------------------------------------------------
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* Controls
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*/
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static int brx_s_ctrl(struct v4l2_ctrl *ctrl)
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{
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struct vsp1_brx *brx =
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container_of(ctrl->handler, struct vsp1_brx, ctrls);
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switch (ctrl->id) {
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case V4L2_CID_BG_COLOR:
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brx->bgcolor = ctrl->val;
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break;
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}
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return 0;
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}
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static const struct v4l2_ctrl_ops brx_ctrl_ops = {
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.s_ctrl = brx_s_ctrl,
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};
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/* -----------------------------------------------------------------------------
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* V4L2 Subdevice Operations
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*/
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/*
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* The BRx can't perform format conversion, all sink and source formats must be
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* identical. We pick the format on the first sink pad (pad 0) and propagate it
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* to all other pads.
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*/
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static int brx_enum_mbus_code(struct v4l2_subdev *subdev,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_mbus_code_enum *code)
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{
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static const unsigned int codes[] = {
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MEDIA_BUS_FMT_ARGB8888_1X32,
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MEDIA_BUS_FMT_AYUV8_1X32,
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};
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return vsp1_subdev_enum_mbus_code(subdev, cfg, code, codes,
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ARRAY_SIZE(codes));
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}
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static int brx_enum_frame_size(struct v4l2_subdev *subdev,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_frame_size_enum *fse)
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{
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if (fse->index)
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return -EINVAL;
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if (fse->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
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fse->code != MEDIA_BUS_FMT_AYUV8_1X32)
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return -EINVAL;
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fse->min_width = BRX_MIN_SIZE;
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fse->max_width = BRX_MAX_SIZE;
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fse->min_height = BRX_MIN_SIZE;
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fse->max_height = BRX_MAX_SIZE;
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return 0;
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}
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static struct v4l2_rect *brx_get_compose(struct vsp1_brx *brx,
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struct v4l2_subdev_pad_config *cfg,
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unsigned int pad)
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{
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return v4l2_subdev_get_try_compose(&brx->entity.subdev, cfg, pad);
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}
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static void brx_try_format(struct vsp1_brx *brx,
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struct v4l2_subdev_pad_config *config,
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unsigned int pad, struct v4l2_mbus_framefmt *fmt)
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{
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struct v4l2_mbus_framefmt *format;
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switch (pad) {
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case BRX_PAD_SINK(0):
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/* Default to YUV if the requested format is not supported. */
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if (fmt->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
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fmt->code != MEDIA_BUS_FMT_AYUV8_1X32)
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fmt->code = MEDIA_BUS_FMT_AYUV8_1X32;
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break;
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default:
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/* The BRx can't perform format conversion. */
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format = vsp1_entity_get_pad_format(&brx->entity, config,
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BRX_PAD_SINK(0));
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fmt->code = format->code;
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break;
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}
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fmt->width = clamp(fmt->width, BRX_MIN_SIZE, BRX_MAX_SIZE);
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fmt->height = clamp(fmt->height, BRX_MIN_SIZE, BRX_MAX_SIZE);
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fmt->field = V4L2_FIELD_NONE;
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fmt->colorspace = V4L2_COLORSPACE_SRGB;
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}
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static int brx_set_format(struct v4l2_subdev *subdev,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_format *fmt)
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{
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struct vsp1_brx *brx = to_brx(subdev);
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struct v4l2_subdev_pad_config *config;
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struct v4l2_mbus_framefmt *format;
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int ret = 0;
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mutex_lock(&brx->entity.lock);
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config = vsp1_entity_get_pad_config(&brx->entity, cfg, fmt->which);
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if (!config) {
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ret = -EINVAL;
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goto done;
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}
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brx_try_format(brx, config, fmt->pad, &fmt->format);
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format = vsp1_entity_get_pad_format(&brx->entity, config, fmt->pad);
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*format = fmt->format;
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/* Reset the compose rectangle. */
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if (fmt->pad != brx->entity.source_pad) {
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struct v4l2_rect *compose;
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compose = brx_get_compose(brx, config, fmt->pad);
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compose->left = 0;
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compose->top = 0;
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compose->width = format->width;
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compose->height = format->height;
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}
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/* Propagate the format code to all pads. */
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if (fmt->pad == BRX_PAD_SINK(0)) {
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unsigned int i;
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for (i = 0; i <= brx->entity.source_pad; ++i) {
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format = vsp1_entity_get_pad_format(&brx->entity,
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config, i);
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format->code = fmt->format.code;
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}
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}
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done:
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mutex_unlock(&brx->entity.lock);
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return ret;
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}
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static int brx_get_selection(struct v4l2_subdev *subdev,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_selection *sel)
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{
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struct vsp1_brx *brx = to_brx(subdev);
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struct v4l2_subdev_pad_config *config;
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if (sel->pad == brx->entity.source_pad)
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return -EINVAL;
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switch (sel->target) {
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case V4L2_SEL_TGT_COMPOSE_BOUNDS:
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sel->r.left = 0;
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sel->r.top = 0;
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sel->r.width = BRX_MAX_SIZE;
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sel->r.height = BRX_MAX_SIZE;
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return 0;
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case V4L2_SEL_TGT_COMPOSE:
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config = vsp1_entity_get_pad_config(&brx->entity, cfg,
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sel->which);
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if (!config)
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return -EINVAL;
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mutex_lock(&brx->entity.lock);
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sel->r = *brx_get_compose(brx, config, sel->pad);
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mutex_unlock(&brx->entity.lock);
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return 0;
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default:
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return -EINVAL;
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}
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}
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static int brx_set_selection(struct v4l2_subdev *subdev,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_selection *sel)
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{
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struct vsp1_brx *brx = to_brx(subdev);
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struct v4l2_subdev_pad_config *config;
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struct v4l2_mbus_framefmt *format;
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struct v4l2_rect *compose;
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int ret = 0;
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if (sel->pad == brx->entity.source_pad)
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return -EINVAL;
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if (sel->target != V4L2_SEL_TGT_COMPOSE)
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return -EINVAL;
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mutex_lock(&brx->entity.lock);
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config = vsp1_entity_get_pad_config(&brx->entity, cfg, sel->which);
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if (!config) {
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ret = -EINVAL;
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goto done;
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}
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/*
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* The compose rectangle top left corner must be inside the output
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* frame.
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*/
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format = vsp1_entity_get_pad_format(&brx->entity, config,
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brx->entity.source_pad);
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sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1);
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sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1);
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/*
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* Scaling isn't supported, the compose rectangle size must be identical
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* to the sink format size.
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*/
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format = vsp1_entity_get_pad_format(&brx->entity, config, sel->pad);
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sel->r.width = format->width;
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sel->r.height = format->height;
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compose = brx_get_compose(brx, config, sel->pad);
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*compose = sel->r;
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done:
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mutex_unlock(&brx->entity.lock);
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return ret;
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}
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static const struct v4l2_subdev_pad_ops brx_pad_ops = {
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.init_cfg = vsp1_entity_init_cfg,
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.enum_mbus_code = brx_enum_mbus_code,
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.enum_frame_size = brx_enum_frame_size,
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.get_fmt = vsp1_subdev_get_pad_format,
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.set_fmt = brx_set_format,
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.get_selection = brx_get_selection,
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.set_selection = brx_set_selection,
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};
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static const struct v4l2_subdev_ops brx_ops = {
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.pad = &brx_pad_ops,
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};
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/* -----------------------------------------------------------------------------
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* VSP1 Entity Operations
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*/
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static void brx_configure_stream(struct vsp1_entity *entity,
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struct vsp1_pipeline *pipe,
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struct vsp1_dl_list *dl,
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struct vsp1_dl_body *dlb)
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{
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struct vsp1_brx *brx = to_brx(&entity->subdev);
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struct v4l2_mbus_framefmt *format;
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unsigned int flags;
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unsigned int i;
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format = vsp1_entity_get_pad_format(&brx->entity, brx->entity.config,
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brx->entity.source_pad);
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/*
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* The hardware is extremely flexible but we have no userspace API to
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* expose all the parameters, nor is it clear whether we would have use
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* cases for all the supported modes. Let's just hardcode the parameters
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* to sane default values for now.
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*/
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/*
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* Disable dithering and enable color data normalization unless the
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* format at the pipeline output is premultiplied.
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*/
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flags = pipe->output ? pipe->output->format.flags : 0;
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vsp1_brx_write(brx, dlb, VI6_BRU_INCTRL,
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flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ?
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0 : VI6_BRU_INCTRL_NRM);
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/*
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* Set the background position to cover the whole output image and
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* configure its color.
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*/
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vsp1_brx_write(brx, dlb, VI6_BRU_VIRRPF_SIZE,
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(format->width << VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT) |
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(format->height << VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT));
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vsp1_brx_write(brx, dlb, VI6_BRU_VIRRPF_LOC, 0);
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vsp1_brx_write(brx, dlb, VI6_BRU_VIRRPF_COL, brx->bgcolor |
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(0xff << VI6_BRU_VIRRPF_COL_A_SHIFT));
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/*
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* Route BRU input 1 as SRC input to the ROP unit and configure the ROP
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* unit with a NOP operation to make BRU input 1 available as the
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* Blend/ROP unit B SRC input. Only needed for BRU, the BRS has no ROP
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* unit.
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*/
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if (entity->type == VSP1_ENTITY_BRU)
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vsp1_brx_write(brx, dlb, VI6_BRU_ROP,
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VI6_BRU_ROP_DSTSEL_BRUIN(1) |
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VI6_BRU_ROP_CROP(VI6_ROP_NOP) |
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VI6_BRU_ROP_AROP(VI6_ROP_NOP));
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for (i = 0; i < brx->entity.source_pad; ++i) {
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bool premultiplied = false;
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u32 ctrl = 0;
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/*
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* Configure all Blend/ROP units corresponding to an enabled BRx
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* input for alpha blending. Blend/ROP units corresponding to
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* disabled BRx inputs are used in ROP NOP mode to ignore the
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* SRC input.
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*/
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if (brx->inputs[i].rpf) {
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ctrl |= VI6_BRU_CTRL_RBC;
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premultiplied = brx->inputs[i].rpf->format.flags
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& V4L2_PIX_FMT_FLAG_PREMUL_ALPHA;
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} else {
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ctrl |= VI6_BRU_CTRL_CROP(VI6_ROP_NOP)
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| VI6_BRU_CTRL_AROP(VI6_ROP_NOP);
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}
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/*
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* Select the virtual RPF as the Blend/ROP unit A DST input to
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* serve as a background color.
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*/
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if (i == 0)
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ctrl |= VI6_BRU_CTRL_DSTSEL_VRPF;
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/*
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* Route inputs 0 to 3 as SRC inputs to Blend/ROP units A to D
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* in that order. In the BRU the Blend/ROP unit B SRC is
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* hardwired to the ROP unit output, the corresponding register
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* bits must be set to 0. The BRS has no ROP unit and doesn't
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* need any special processing.
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*/
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if (!(entity->type == VSP1_ENTITY_BRU && i == 1))
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ctrl |= VI6_BRU_CTRL_SRCSEL_BRUIN(i);
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vsp1_brx_write(brx, dlb, VI6_BRU_CTRL(i), ctrl);
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/*
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* Hardcode the blending formula to
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*
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* DSTc = DSTc * (1 - SRCa) + SRCc * SRCa
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* DSTa = DSTa * (1 - SRCa) + SRCa
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*
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* when the SRC input isn't premultiplied, and to
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*
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* DSTc = DSTc * (1 - SRCa) + SRCc
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* DSTa = DSTa * (1 - SRCa) + SRCa
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*
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* otherwise.
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*/
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vsp1_brx_write(brx, dlb, VI6_BRU_BLD(i),
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VI6_BRU_BLD_CCMDX_255_SRC_A |
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(premultiplied ? VI6_BRU_BLD_CCMDY_COEFY :
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VI6_BRU_BLD_CCMDY_SRC_A) |
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VI6_BRU_BLD_ACMDX_255_SRC_A |
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VI6_BRU_BLD_ACMDY_COEFY |
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(0xff << VI6_BRU_BLD_COEFY_SHIFT));
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}
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}
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static const struct vsp1_entity_operations brx_entity_ops = {
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.configure_stream = brx_configure_stream,
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};
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/* -----------------------------------------------------------------------------
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* Initialization and Cleanup
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*/
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struct vsp1_brx *vsp1_brx_create(struct vsp1_device *vsp1,
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enum vsp1_entity_type type)
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{
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struct vsp1_brx *brx;
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unsigned int num_pads;
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const char *name;
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int ret;
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brx = devm_kzalloc(vsp1->dev, sizeof(*brx), GFP_KERNEL);
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if (brx == NULL)
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return ERR_PTR(-ENOMEM);
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brx->base = type == VSP1_ENTITY_BRU ? VI6_BRU_BASE : VI6_BRS_BASE;
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brx->entity.ops = &brx_entity_ops;
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brx->entity.type = type;
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if (type == VSP1_ENTITY_BRU) {
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num_pads = vsp1->info->num_bru_inputs + 1;
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name = "bru";
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} else {
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num_pads = 3;
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name = "brs";
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}
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ret = vsp1_entity_init(vsp1, &brx->entity, name, num_pads, &brx_ops,
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MEDIA_ENT_F_PROC_VIDEO_COMPOSER);
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if (ret < 0)
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return ERR_PTR(ret);
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/* Initialize the control handler. */
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v4l2_ctrl_handler_init(&brx->ctrls, 1);
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v4l2_ctrl_new_std(&brx->ctrls, &brx_ctrl_ops, V4L2_CID_BG_COLOR,
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0, 0xffffff, 1, 0);
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brx->bgcolor = 0;
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brx->entity.subdev.ctrl_handler = &brx->ctrls;
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if (brx->ctrls.error) {
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dev_err(vsp1->dev, "%s: failed to initialize controls\n", name);
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ret = brx->ctrls.error;
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vsp1_entity_destroy(&brx->entity);
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return ERR_PTR(ret);
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}
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return brx;
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}
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