/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2013 Texas Instruments Inc.
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*
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* David Griego, <dagriego@biglakesoftware.com>
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* Dale Farnsworth, <dale@farnsworth.org>
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* Archit Taneja, <archit@ti.com>
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*/
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#ifndef __TI_VPDMA_H_
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#define __TI_VPDMA_H_
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#define VPDMA_MAX_NUM_LIST 8
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/*
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* A vpdma_buf tracks the size, DMA address and mapping status of each
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* driver DMA area.
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*/
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struct vpdma_buf {
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void *addr;
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dma_addr_t dma_addr;
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size_t size;
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bool mapped;
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};
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struct vpdma_desc_list {
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struct vpdma_buf buf;
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void *next;
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int type;
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};
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struct vpdma_data {
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void __iomem *base;
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struct platform_device *pdev;
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spinlock_t lock;
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bool hwlist_used[VPDMA_MAX_NUM_LIST];
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void *hwlist_priv[VPDMA_MAX_NUM_LIST];
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/* callback to VPE driver when the firmware is loaded */
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void (*cb)(struct platform_device *pdev);
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};
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enum vpdma_data_format_type {
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VPDMA_DATA_FMT_TYPE_YUV,
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VPDMA_DATA_FMT_TYPE_RGB,
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VPDMA_DATA_FMT_TYPE_MISC,
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};
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struct vpdma_data_format {
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enum vpdma_data_format_type type;
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int data_type;
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u8 depth;
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};
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#define VPDMA_DESC_ALIGN 16 /* 16-byte descriptor alignment */
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#define VPDMA_STRIDE_ALIGN 16 /*
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* line stride of source and dest
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* buffers should be 16 byte aligned
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*/
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#define VPDMA_MAX_STRIDE 65520 /* Max line stride 16 byte aligned */
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#define VPDMA_DTD_DESC_SIZE 32 /* 8 words */
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#define VPDMA_CFD_CTD_DESC_SIZE 16 /* 4 words */
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#define VPDMA_LIST_TYPE_NORMAL 0
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#define VPDMA_LIST_TYPE_SELF_MODIFYING 1
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#define VPDMA_LIST_TYPE_DOORBELL 2
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enum vpdma_yuv_formats {
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VPDMA_DATA_FMT_Y444 = 0,
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VPDMA_DATA_FMT_Y422,
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VPDMA_DATA_FMT_Y420,
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VPDMA_DATA_FMT_C444,
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VPDMA_DATA_FMT_C422,
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VPDMA_DATA_FMT_C420,
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VPDMA_DATA_FMT_CB420,
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VPDMA_DATA_FMT_YCR422,
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VPDMA_DATA_FMT_YC444,
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VPDMA_DATA_FMT_CRY422,
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VPDMA_DATA_FMT_CBY422,
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VPDMA_DATA_FMT_YCB422,
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};
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enum vpdma_rgb_formats {
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VPDMA_DATA_FMT_RGB565 = 0,
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VPDMA_DATA_FMT_ARGB16_1555,
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VPDMA_DATA_FMT_ARGB16,
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VPDMA_DATA_FMT_RGBA16_5551,
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VPDMA_DATA_FMT_RGBA16,
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VPDMA_DATA_FMT_ARGB24,
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VPDMA_DATA_FMT_RGB24,
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VPDMA_DATA_FMT_ARGB32,
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VPDMA_DATA_FMT_RGBA24,
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VPDMA_DATA_FMT_RGBA32,
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VPDMA_DATA_FMT_BGR565,
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VPDMA_DATA_FMT_ABGR16_1555,
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VPDMA_DATA_FMT_ABGR16,
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VPDMA_DATA_FMT_BGRA16_5551,
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VPDMA_DATA_FMT_BGRA16,
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VPDMA_DATA_FMT_ABGR24,
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VPDMA_DATA_FMT_BGR24,
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VPDMA_DATA_FMT_ABGR32,
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VPDMA_DATA_FMT_BGRA24,
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VPDMA_DATA_FMT_BGRA32,
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};
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enum vpdma_raw_formats {
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VPDMA_DATA_FMT_RAW8 = 0,
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VPDMA_DATA_FMT_RAW16,
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};
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enum vpdma_misc_formats {
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VPDMA_DATA_FMT_MV = 0,
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};
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extern const struct vpdma_data_format vpdma_yuv_fmts[];
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extern const struct vpdma_data_format vpdma_rgb_fmts[];
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extern const struct vpdma_data_format vpdma_raw_fmts[];
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extern const struct vpdma_data_format vpdma_misc_fmts[];
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enum vpdma_frame_start_event {
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VPDMA_FSEVENT_HDMI_FID = 0,
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VPDMA_FSEVENT_DVO2_FID,
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VPDMA_FSEVENT_HDCOMP_FID,
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VPDMA_FSEVENT_SD_FID,
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VPDMA_FSEVENT_LM_FID0,
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VPDMA_FSEVENT_LM_FID1,
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VPDMA_FSEVENT_LM_FID2,
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VPDMA_FSEVENT_CHANNEL_ACTIVE,
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};
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/* max width configurations */
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enum vpdma_max_width {
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MAX_OUT_WIDTH_UNLIMITED = 0,
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MAX_OUT_WIDTH_REG1,
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MAX_OUT_WIDTH_REG2,
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MAX_OUT_WIDTH_REG3,
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MAX_OUT_WIDTH_352,
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MAX_OUT_WIDTH_768,
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MAX_OUT_WIDTH_1280,
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MAX_OUT_WIDTH_1920,
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};
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/* max height configurations */
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enum vpdma_max_height {
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MAX_OUT_HEIGHT_UNLIMITED = 0,
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MAX_OUT_HEIGHT_REG1,
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MAX_OUT_HEIGHT_REG2,
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MAX_OUT_HEIGHT_REG3,
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MAX_OUT_HEIGHT_288,
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MAX_OUT_HEIGHT_576,
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MAX_OUT_HEIGHT_720,
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MAX_OUT_HEIGHT_1080,
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};
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/*
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* VPDMA channel numbers
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*/
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enum vpdma_channel {
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VPE_CHAN_LUMA1_IN,
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VPE_CHAN_CHROMA1_IN,
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VPE_CHAN_LUMA2_IN,
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VPE_CHAN_CHROMA2_IN,
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VPE_CHAN_LUMA3_IN,
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VPE_CHAN_CHROMA3_IN,
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VPE_CHAN_MV_IN,
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VPE_CHAN_MV_OUT,
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VPE_CHAN_LUMA_OUT,
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VPE_CHAN_CHROMA_OUT,
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VPE_CHAN_RGB_OUT,
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};
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#define VIP_CHAN_VIP2_OFFSET 70
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#define VIP_CHAN_MULT_PORTB_OFFSET 16
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#define VIP_CHAN_YUV_PORTB_OFFSET 2
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#define VIP_CHAN_RGB_PORTB_OFFSET 1
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#define VPDMA_MAX_CHANNELS 256
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/* flags for VPDMA data descriptors */
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#define VPDMA_DATA_ODD_LINE_SKIP (1 << 0)
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#define VPDMA_DATA_EVEN_LINE_SKIP (1 << 1)
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#define VPDMA_DATA_FRAME_1D (1 << 2)
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#define VPDMA_DATA_MODE_TILED (1 << 3)
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/*
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* client identifiers used for configuration descriptors
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*/
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#define CFD_MMR_CLIENT 0
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#define CFD_SC_CLIENT 4
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/* Address data block header format */
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struct vpdma_adb_hdr {
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u32 offset;
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u32 nwords;
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u32 reserved0;
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u32 reserved1;
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};
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/* helpers for creating ADB headers for config descriptors MMRs as client */
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#define ADB_ADDR(dma_buf, str, fld) ((dma_buf)->addr + offsetof(str, fld))
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#define MMR_ADB_ADDR(buf, str, fld) ADB_ADDR(&(buf), struct str, fld)
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#define VPDMA_SET_MMR_ADB_HDR(buf, str, hdr, regs, offset_a) \
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do { \
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struct vpdma_adb_hdr *h; \
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struct str *adb = NULL; \
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h = MMR_ADB_ADDR(buf, str, hdr); \
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h->offset = (offset_a); \
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h->nwords = sizeof(adb->regs) >> 2; \
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} while (0)
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/* vpdma descriptor buffer allocation and management */
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int vpdma_alloc_desc_buf(struct vpdma_buf *buf, size_t size);
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void vpdma_free_desc_buf(struct vpdma_buf *buf);
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int vpdma_map_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf);
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void vpdma_unmap_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf);
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/* vpdma descriptor list funcs */
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int vpdma_create_desc_list(struct vpdma_desc_list *list, size_t size, int type);
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void vpdma_reset_desc_list(struct vpdma_desc_list *list);
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void vpdma_free_desc_list(struct vpdma_desc_list *list);
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int vpdma_submit_descs(struct vpdma_data *vpdma, struct vpdma_desc_list *list,
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int list_num);
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bool vpdma_list_busy(struct vpdma_data *vpdma, int list_num);
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void vpdma_update_dma_addr(struct vpdma_data *vpdma,
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struct vpdma_desc_list *list, dma_addr_t dma_addr,
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void *write_dtd, int drop, int idx);
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/* VPDMA hardware list funcs */
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int vpdma_hwlist_alloc(struct vpdma_data *vpdma, void *priv);
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void *vpdma_hwlist_get_priv(struct vpdma_data *vpdma, int list_num);
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void *vpdma_hwlist_release(struct vpdma_data *vpdma, int list_num);
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/* helpers for creating vpdma descriptors */
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void vpdma_add_cfd_block(struct vpdma_desc_list *list, int client,
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struct vpdma_buf *blk, u32 dest_offset);
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void vpdma_add_cfd_adb(struct vpdma_desc_list *list, int client,
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struct vpdma_buf *adb);
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void vpdma_add_sync_on_channel_ctd(struct vpdma_desc_list *list,
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enum vpdma_channel chan);
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void vpdma_add_abort_channel_ctd(struct vpdma_desc_list *list,
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int chan_num);
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void vpdma_add_out_dtd(struct vpdma_desc_list *list, int width,
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int stride, const struct v4l2_rect *c_rect,
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const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
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int max_w, int max_h, enum vpdma_channel chan, u32 flags);
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void vpdma_rawchan_add_out_dtd(struct vpdma_desc_list *list, int width,
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int stride, const struct v4l2_rect *c_rect,
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const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
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int max_w, int max_h, int raw_vpdma_chan, u32 flags);
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void vpdma_add_in_dtd(struct vpdma_desc_list *list, int width,
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int stride, const struct v4l2_rect *c_rect,
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const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
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enum vpdma_channel chan, int field, u32 flags, int frame_width,
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int frame_height, int start_h, int start_v);
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int vpdma_list_cleanup(struct vpdma_data *vpdma, int list_num,
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int *channels, int size);
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/* vpdma list interrupt management */
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void vpdma_enable_list_complete_irq(struct vpdma_data *vpdma, int irq_num,
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int list_num, bool enable);
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void vpdma_clear_list_stat(struct vpdma_data *vpdma, int irq_num,
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int list_num);
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unsigned int vpdma_get_list_stat(struct vpdma_data *vpdma, int irq_num);
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unsigned int vpdma_get_list_mask(struct vpdma_data *vpdma, int irq_num);
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/* vpdma client configuration */
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void vpdma_set_line_mode(struct vpdma_data *vpdma, int line_mode,
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enum vpdma_channel chan);
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void vpdma_set_frame_start_event(struct vpdma_data *vpdma,
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enum vpdma_frame_start_event fs_event, enum vpdma_channel chan);
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void vpdma_set_max_size(struct vpdma_data *vpdma, int reg_addr,
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u32 width, u32 height);
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void vpdma_set_bg_color(struct vpdma_data *vpdma,
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struct vpdma_data_format *fmt, u32 color);
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void vpdma_dump_regs(struct vpdma_data *vpdma);
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/* initialize vpdma, passed with VPE's platform device pointer */
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int vpdma_create(struct platform_device *pdev, struct vpdma_data *vpdma,
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void (*cb)(struct platform_device *pdev));
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#endif
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