// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* linux/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/firmware.h>
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#include <linux/jiffies.h>
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#include <linux/sched.h>
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#include "s5p_mfc_cmd.h"
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#include "s5p_mfc_common.h"
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#include "s5p_mfc_debug.h"
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#include "s5p_mfc_intr.h"
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#include "s5p_mfc_opr.h"
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#include "s5p_mfc_pm.h"
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#include "s5p_mfc_ctrl.h"
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/* Allocate memory for firmware */
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int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev)
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{
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struct s5p_mfc_priv_buf *fw_buf = &dev->fw_buf;
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int err;
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fw_buf->size = dev->variant->buf_size->fw;
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if (fw_buf->virt) {
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mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n");
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return -ENOMEM;
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}
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err = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &dev->fw_buf);
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if (err) {
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mfc_err("Allocating bitprocessor buffer failed\n");
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return err;
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}
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return 0;
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}
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/* Load firmware */
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int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev)
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{
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struct firmware *fw_blob;
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int i, err = -EINVAL;
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/* Firmware has to be present as a separate file or compiled
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* into kernel. */
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mfc_debug_enter();
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if (dev->fw_get_done)
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return 0;
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for (i = MFC_FW_MAX_VERSIONS - 1; i >= 0; i--) {
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if (!dev->variant->fw_name[i])
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continue;
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err = request_firmware((const struct firmware **)&fw_blob,
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dev->variant->fw_name[i], &dev->plat_dev->dev);
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if (!err) {
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dev->fw_ver = (enum s5p_mfc_fw_ver) i;
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break;
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}
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}
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if (err != 0) {
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mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
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return -EINVAL;
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}
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if (fw_blob->size > dev->fw_buf.size) {
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mfc_err("MFC firmware is too big to be loaded\n");
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release_firmware(fw_blob);
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return -ENOMEM;
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}
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memcpy(dev->fw_buf.virt, fw_blob->data, fw_blob->size);
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wmb();
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dev->fw_get_done = true;
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release_firmware(fw_blob);
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mfc_debug_leave();
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return 0;
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}
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/* Release firmware memory */
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int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
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{
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/* Before calling this function one has to make sure
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* that MFC is no longer processing */
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s5p_mfc_release_priv_buf(dev, &dev->fw_buf);
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dev->fw_get_done = false;
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return 0;
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}
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static int s5p_mfc_bus_reset(struct s5p_mfc_dev *dev)
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{
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unsigned int status;
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unsigned long timeout;
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/* Reset */
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mfc_write(dev, 0x1, S5P_FIMV_MFC_BUS_RESET_CTRL);
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timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
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/* Check bus status */
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do {
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if (time_after(jiffies, timeout)) {
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mfc_err("Timeout while resetting MFC.\n");
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return -EIO;
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}
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status = mfc_read(dev, S5P_FIMV_MFC_BUS_RESET_CTRL);
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} while ((status & 0x2) == 0);
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return 0;
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}
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/* Reset the device */
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int s5p_mfc_reset(struct s5p_mfc_dev *dev)
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{
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unsigned int mc_status;
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unsigned long timeout;
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int i;
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mfc_debug_enter();
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if (IS_MFCV6_PLUS(dev)) {
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/* Zero Initialization of MFC registers */
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mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
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mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
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mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);
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for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT_V6; i++)
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mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));
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/* check bus reset control before reset */
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if (dev->risc_on)
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if (s5p_mfc_bus_reset(dev))
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return -EIO;
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/* Reset
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* set RISC_ON to 0 during power_on & wake_up.
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* V6 needs RISC_ON set to 0 during reset also.
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*/
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if ((!dev->risc_on) || (!IS_MFCV7_PLUS(dev)))
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mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);
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mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);
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mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);
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} else {
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/* Stop procedure */
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/* reset RISC */
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mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
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/* All reset except for MC */
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mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
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mdelay(10);
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timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
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/* Check MC status */
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do {
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if (time_after(jiffies, timeout)) {
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mfc_err("Timeout while resetting MFC\n");
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return -EIO;
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}
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mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);
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} while (mc_status & 0x3);
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mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
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mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
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}
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mfc_debug_leave();
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return 0;
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}
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static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
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{
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if (IS_MFCV6_PLUS(dev)) {
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mfc_write(dev, dev->dma_base[BANK_L_CTX],
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S5P_FIMV_RISC_BASE_ADDRESS_V6);
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mfc_debug(2, "Base Address : %pad\n",
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&dev->dma_base[BANK_L_CTX]);
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} else {
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mfc_write(dev, dev->dma_base[BANK_L_CTX],
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S5P_FIMV_MC_DRAMBASE_ADR_A);
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mfc_write(dev, dev->dma_base[BANK_R_CTX],
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S5P_FIMV_MC_DRAMBASE_ADR_B);
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mfc_debug(2, "Bank1: %pad, Bank2: %pad\n",
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&dev->dma_base[BANK_L_CTX],
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&dev->dma_base[BANK_R_CTX]);
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}
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}
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static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
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{
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if (IS_MFCV6_PLUS(dev)) {
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/* Zero initialization should be done before RESET.
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* Nothing to do here. */
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} else {
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mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
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mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
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mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
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mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
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}
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}
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/* Initialize hardware */
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int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
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{
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unsigned int ver;
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int ret;
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mfc_debug_enter();
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if (!dev->fw_buf.virt) {
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mfc_err("Firmware memory is not allocated.\n");
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return -EINVAL;
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}
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/* 0. MFC reset */
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mfc_debug(2, "MFC reset..\n");
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s5p_mfc_clock_on();
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dev->risc_on = 0;
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ret = s5p_mfc_reset(dev);
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if (ret) {
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mfc_err("Failed to reset MFC - timeout\n");
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return ret;
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}
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mfc_debug(2, "Done MFC reset..\n");
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/* 1. Set DRAM base Addr */
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s5p_mfc_init_memctrl(dev);
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/* 2. Initialize registers of channel I/F */
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s5p_mfc_clear_cmds(dev);
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/* 3. Release reset signal to the RISC */
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s5p_mfc_clean_dev_int_flags(dev);
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if (IS_MFCV6_PLUS(dev)) {
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dev->risc_on = 1;
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mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
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}
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else
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mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
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if (IS_MFCV10(dev))
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mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10);
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mfc_debug(2, "Will now wait for completion of firmware transfer\n");
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if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
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mfc_err("Failed to load firmware\n");
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s5p_mfc_reset(dev);
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s5p_mfc_clock_off();
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return -EIO;
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}
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s5p_mfc_clean_dev_int_flags(dev);
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/* 4. Initialize firmware */
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ret = s5p_mfc_hw_call(dev->mfc_cmds, sys_init_cmd, dev);
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if (ret) {
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mfc_err("Failed to send command to MFC - timeout\n");
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s5p_mfc_reset(dev);
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s5p_mfc_clock_off();
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return ret;
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}
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mfc_debug(2, "Ok, now will wait for completion of hardware init\n");
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if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SYS_INIT_RET)) {
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mfc_err("Failed to init hardware\n");
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s5p_mfc_reset(dev);
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s5p_mfc_clock_off();
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return -EIO;
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}
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dev->int_cond = 0;
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if (dev->int_err != 0 || dev->int_type !=
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S5P_MFC_R2H_CMD_SYS_INIT_RET) {
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/* Failure. */
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mfc_err("Failed to init firmware - error: %d int: %d\n",
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dev->int_err, dev->int_type);
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s5p_mfc_reset(dev);
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s5p_mfc_clock_off();
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return -EIO;
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}
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if (IS_MFCV6_PLUS(dev))
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ver = mfc_read(dev, S5P_FIMV_FW_VERSION_V6);
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else
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ver = mfc_read(dev, S5P_FIMV_FW_VERSION);
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mfc_debug(2, "MFC F/W version : %02xyy, %02xmm, %02xdd\n",
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(ver >> 16) & 0xFF, (ver >> 8) & 0xFF, ver & 0xFF);
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s5p_mfc_clock_off();
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mfc_debug_leave();
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return 0;
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}
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/* Deinitialize hardware */
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void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev)
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{
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s5p_mfc_clock_on();
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s5p_mfc_reset(dev);
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s5p_mfc_hw_call(dev->mfc_ops, release_dev_context_buffer, dev);
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s5p_mfc_clock_off();
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}
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int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
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{
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int ret;
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mfc_debug_enter();
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s5p_mfc_clock_on();
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s5p_mfc_clean_dev_int_flags(dev);
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ret = s5p_mfc_hw_call(dev->mfc_cmds, sleep_cmd, dev);
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if (ret) {
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mfc_err("Failed to send command to MFC - timeout\n");
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return ret;
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}
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if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SLEEP_RET)) {
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mfc_err("Failed to sleep\n");
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return -EIO;
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}
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s5p_mfc_clock_off();
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dev->int_cond = 0;
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if (dev->int_err != 0 || dev->int_type !=
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S5P_MFC_R2H_CMD_SLEEP_RET) {
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/* Failure. */
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mfc_err("Failed to sleep - error: %d int: %d\n", dev->int_err,
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dev->int_type);
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return -EIO;
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}
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mfc_debug_leave();
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return ret;
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}
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static int s5p_mfc_v8_wait_wakeup(struct s5p_mfc_dev *dev)
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{
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int ret;
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/* Release reset signal to the RISC */
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dev->risc_on = 1;
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mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
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if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
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mfc_err("Failed to reset MFCV8\n");
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return -EIO;
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}
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mfc_debug(2, "Write command to wakeup MFCV8\n");
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ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
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if (ret) {
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mfc_err("Failed to send command to MFCV8 - timeout\n");
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return ret;
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}
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if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
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mfc_err("Failed to wakeup MFC\n");
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return -EIO;
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}
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return ret;
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}
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static int s5p_mfc_wait_wakeup(struct s5p_mfc_dev *dev)
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{
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int ret;
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/* Send MFC wakeup command */
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ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
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if (ret) {
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mfc_err("Failed to send command to MFC - timeout\n");
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return ret;
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}
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/* Release reset signal to the RISC */
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if (IS_MFCV6_PLUS(dev)) {
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dev->risc_on = 1;
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mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
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} else {
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mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
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}
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if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
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mfc_err("Failed to wakeup MFC\n");
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return -EIO;
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}
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return ret;
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}
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int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
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{
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int ret;
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mfc_debug_enter();
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/* 0. MFC reset */
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mfc_debug(2, "MFC reset..\n");
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s5p_mfc_clock_on();
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dev->risc_on = 0;
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ret = s5p_mfc_reset(dev);
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if (ret) {
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mfc_err("Failed to reset MFC - timeout\n");
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s5p_mfc_clock_off();
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return ret;
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}
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mfc_debug(2, "Done MFC reset..\n");
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/* 1. Set DRAM base Addr */
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s5p_mfc_init_memctrl(dev);
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/* 2. Initialize registers of channel I/F */
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s5p_mfc_clear_cmds(dev);
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s5p_mfc_clean_dev_int_flags(dev);
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/* 3. Send MFC wakeup command and wait for completion*/
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if (IS_MFCV8_PLUS(dev))
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ret = s5p_mfc_v8_wait_wakeup(dev);
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else
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ret = s5p_mfc_wait_wakeup(dev);
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s5p_mfc_clock_off();
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if (ret)
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return ret;
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dev->int_cond = 0;
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if (dev->int_err != 0 || dev->int_type !=
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S5P_MFC_R2H_CMD_WAKEUP_RET) {
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/* Failure. */
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mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err,
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dev->int_type);
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return -EIO;
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}
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mfc_debug_leave();
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return 0;
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}
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int s5p_mfc_open_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
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{
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int ret = 0;
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ret = s5p_mfc_hw_call(dev->mfc_ops, alloc_instance_buffer, ctx);
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if (ret) {
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mfc_err("Failed allocating instance buffer\n");
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goto err;
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}
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if (ctx->type == MFCINST_DECODER) {
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ret = s5p_mfc_hw_call(dev->mfc_ops,
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alloc_dec_temp_buffers, ctx);
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if (ret) {
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mfc_err("Failed allocating temporary buffers\n");
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goto err_free_inst_buf;
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}
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}
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set_work_bit_irqsave(ctx);
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s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
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if (s5p_mfc_wait_for_done_ctx(ctx,
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S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET, 0)) {
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/* Error or timeout */
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mfc_err("Error getting instance from hardware\n");
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ret = -EIO;
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goto err_free_desc_buf;
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}
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mfc_debug(2, "Got instance number: %d\n", ctx->inst_no);
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return ret;
|
|
err_free_desc_buf:
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if (ctx->type == MFCINST_DECODER)
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s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx);
|
err_free_inst_buf:
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s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
|
err:
|
return ret;
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}
|
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void s5p_mfc_close_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
|
{
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ctx->state = MFCINST_RETURN_INST;
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set_work_bit_irqsave(ctx);
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s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
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/* Wait until instance is returned or timeout occurred */
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if (s5p_mfc_wait_for_done_ctx(ctx,
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S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0))
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mfc_err("Err returning instance\n");
|
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/* Free resources */
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s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
|
s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
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if (ctx->type == MFCINST_DECODER)
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s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx);
|
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ctx->inst_no = MFC_NO_INSTANCE_SET;
|
ctx->state = MFCINST_FREE;
|
}
|
