/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Samsung S5P Multi Format Codec v 5.0
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*
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* This file contains definitions of enums and structs used by the codec
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* driver.
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*
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* Copyright (C) 2011 Samsung Electronics Co., Ltd.
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* Kamil Debski, <k.debski@samsung.com>
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*/
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#ifndef S5P_MFC_COMMON_H_
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#define S5P_MFC_COMMON_H_
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#include <linux/platform_device.h>
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#include <linux/videodev2.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-ioctl.h>
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#include <media/videobuf2-v4l2.h>
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#include "regs-mfc.h"
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#include "regs-mfc-v10.h"
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#define S5P_MFC_NAME "s5p-mfc"
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/* Definitions related to MFC memory */
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/* Offset base used to differentiate between CAPTURE and OUTPUT
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* while mmaping */
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#define DST_QUEUE_OFF_BASE (1 << 30)
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#define BANK_L_CTX 0
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#define BANK_R_CTX 1
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#define BANK_CTX_NUM 2
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#define MFC_BANK1_ALIGN_ORDER 13
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#define MFC_BANK2_ALIGN_ORDER 13
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#define MFC_BASE_ALIGN_ORDER 17
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#define MFC_FW_MAX_VERSIONS 2
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#include <media/videobuf2-dma-contig.h>
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/* MFC definitions */
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#define MFC_MAX_EXTRA_DPB 5
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#define MFC_MAX_BUFFERS 32
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#define MFC_NUM_CONTEXTS 4
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/* Interrupt timeout */
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#define MFC_INT_TIMEOUT 2000
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/* Busy wait timeout */
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#define MFC_BW_TIMEOUT 500
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/* Watchdog interval */
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#define MFC_WATCHDOG_INTERVAL 1000
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/* After how many executions watchdog should assume lock up */
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#define MFC_WATCHDOG_CNT 10
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#define MFC_NO_INSTANCE_SET -1
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#define MFC_ENC_CAP_PLANE_COUNT 1
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#define MFC_ENC_OUT_PLANE_COUNT 2
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#define STUFF_BYTE 4
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#define MFC_MAX_CTRLS 128
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#define S5P_MFC_CODEC_NONE -1
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#define S5P_MFC_CODEC_H264_DEC 0
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#define S5P_MFC_CODEC_H264_MVC_DEC 1
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#define S5P_MFC_CODEC_VC1_DEC 2
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#define S5P_MFC_CODEC_MPEG4_DEC 3
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#define S5P_MFC_CODEC_MPEG2_DEC 4
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#define S5P_MFC_CODEC_H263_DEC 5
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#define S5P_MFC_CODEC_VC1RCV_DEC 6
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#define S5P_MFC_CODEC_VP8_DEC 7
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#define S5P_MFC_CODEC_HEVC_DEC 17
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#define S5P_MFC_CODEC_VP9_DEC 18
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#define S5P_MFC_CODEC_H264_ENC 20
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#define S5P_MFC_CODEC_H264_MVC_ENC 21
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#define S5P_MFC_CODEC_MPEG4_ENC 22
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#define S5P_MFC_CODEC_H263_ENC 23
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#define S5P_MFC_CODEC_VP8_ENC 24
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#define S5P_MFC_CODEC_HEVC_ENC 26
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#define S5P_MFC_R2H_CMD_EMPTY 0
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#define S5P_MFC_R2H_CMD_SYS_INIT_RET 1
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#define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2
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#define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3
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#define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4
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#define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6
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#define S5P_MFC_R2H_CMD_SLEEP_RET 7
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#define S5P_MFC_R2H_CMD_WAKEUP_RET 8
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#define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9
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#define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10
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#define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11
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#define S5P_MFC_R2H_CMD_FW_STATUS_RET 12
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#define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13
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#define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14
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#define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15
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#define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16
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#define S5P_MFC_R2H_CMD_ERR_RET 32
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#define MFC_MAX_CLOCKS 4
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#define mfc_read(dev, offset) readl(dev->regs_base + (offset))
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#define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
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(offset))
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/**
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* enum s5p_mfc_fmt_type - type of the pixelformat
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*/
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enum s5p_mfc_fmt_type {
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MFC_FMT_DEC,
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MFC_FMT_ENC,
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MFC_FMT_RAW,
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};
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/**
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* enum s5p_mfc_inst_type - The type of an MFC instance.
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*/
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enum s5p_mfc_inst_type {
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MFCINST_INVALID,
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MFCINST_DECODER,
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MFCINST_ENCODER,
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};
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/**
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* enum s5p_mfc_inst_state - The state of an MFC instance.
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*/
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enum s5p_mfc_inst_state {
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MFCINST_FREE = 0,
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MFCINST_INIT = 100,
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MFCINST_GOT_INST,
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MFCINST_HEAD_PARSED,
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MFCINST_HEAD_PRODUCED,
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MFCINST_BUFS_SET,
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MFCINST_RUNNING,
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MFCINST_FINISHING,
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MFCINST_FINISHED,
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MFCINST_RETURN_INST,
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MFCINST_ERROR,
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MFCINST_ABORT,
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MFCINST_FLUSH,
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MFCINST_RES_CHANGE_INIT,
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MFCINST_RES_CHANGE_FLUSH,
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MFCINST_RES_CHANGE_END,
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};
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/**
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* enum s5p_mfc_queue_state - The state of buffer queue.
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*/
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enum s5p_mfc_queue_state {
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QUEUE_FREE,
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QUEUE_BUFS_REQUESTED,
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QUEUE_BUFS_QUERIED,
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QUEUE_BUFS_MMAPED,
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};
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/**
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* enum s5p_mfc_decode_arg - type of frame decoding
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*/
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enum s5p_mfc_decode_arg {
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MFC_DEC_FRAME,
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MFC_DEC_LAST_FRAME,
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MFC_DEC_RES_CHANGE,
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};
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enum s5p_mfc_fw_ver {
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MFC_FW_V1,
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MFC_FW_V2,
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};
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#define MFC_BUF_FLAG_USED (1 << 0)
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#define MFC_BUF_FLAG_EOS (1 << 1)
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struct s5p_mfc_ctx;
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/**
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* struct s5p_mfc_buf - MFC buffer
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*/
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struct s5p_mfc_buf {
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struct vb2_v4l2_buffer *b;
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struct list_head list;
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union {
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struct {
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size_t luma;
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size_t chroma;
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} raw;
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size_t stream;
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} cookie;
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int flags;
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};
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/**
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* struct s5p_mfc_pm - power management data structure
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*/
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struct s5p_mfc_pm {
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struct clk *clock_gate;
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const char * const *clk_names;
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struct clk *clocks[MFC_MAX_CLOCKS];
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int num_clocks;
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bool use_clock_gating;
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struct device *device;
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};
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struct s5p_mfc_buf_size_v5 {
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unsigned int h264_ctx;
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unsigned int non_h264_ctx;
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unsigned int dsc;
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unsigned int shm;
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};
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struct s5p_mfc_buf_size_v6 {
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unsigned int dev_ctx;
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unsigned int h264_dec_ctx;
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unsigned int other_dec_ctx;
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unsigned int h264_enc_ctx;
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unsigned int hevc_enc_ctx;
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unsigned int other_enc_ctx;
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};
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struct s5p_mfc_buf_size {
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unsigned int fw;
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unsigned int cpb;
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void *priv;
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};
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struct s5p_mfc_variant {
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unsigned int version;
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unsigned int port_num;
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u32 version_bit;
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struct s5p_mfc_buf_size *buf_size;
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char *fw_name[MFC_FW_MAX_VERSIONS];
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const char *clk_names[MFC_MAX_CLOCKS];
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int num_clocks;
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bool use_clock_gating;
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};
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/**
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* struct s5p_mfc_priv_buf - represents internal used buffer
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* @ofs: offset of each buffer, will be used for MFC
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* @virt: kernel virtual address, only valid when the
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* buffer accessed by driver
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* @dma: DMA address, only valid when kernel DMA API used
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* @size: size of the buffer
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* @ctx: memory context (bank) used for this allocation
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*/
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struct s5p_mfc_priv_buf {
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unsigned long ofs;
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void *virt;
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dma_addr_t dma;
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size_t size;
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unsigned int ctx;
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};
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/**
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* struct s5p_mfc_dev - The struct containing driver internal parameters.
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*
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* @v4l2_dev: v4l2_device
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* @vfd_dec: video device for decoding
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* @vfd_enc: video device for encoding
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* @plat_dev: platform device
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* @mem_dev[]: child devices of the memory banks
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* @regs_base: base address of the MFC hw registers
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* @irq: irq resource
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* @dec_ctrl_handler: control framework handler for decoding
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* @enc_ctrl_handler: control framework handler for encoding
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* @pm: power management control
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* @variant: MFC hardware variant information
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* @num_inst: counter of active MFC instances
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* @irqlock: lock for operations on videobuf2 queues
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* @condlock: lock for changing/checking if a context is ready to be
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* processed
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* @mfc_mutex: lock for video_device
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* @int_cond: variable used by the waitqueue
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* @int_type: type of last interrupt
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* @int_err: error number for last interrupt
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* @queue: waitqueue for waiting for completion of device commands
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* @fw_size: size of firmware
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* @fw_virt_addr: virtual firmware address
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* @dma_base[]: address of the beginning of memory banks
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* @hw_lock: used for hardware locking
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* @ctx: array of driver contexts
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* @curr_ctx: number of the currently running context
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* @ctx_work_bits: used to mark which contexts are waiting for hardware
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* @watchdog_cnt: counter for the watchdog
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* @watchdog_workqueue: workqueue for the watchdog
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* @watchdog_work: worker for the watchdog
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* @enter_suspend: flag set when entering suspend
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* @ctx_buf: common context memory (MFCv6)
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* @warn_start: hardware error code from which warnings start
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* @mfc_ops: ops structure holding HW operation function pointers
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* @mfc_cmds: cmd structure holding HW commands function pointers
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* @mfc_regs: structure holding MFC registers
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* @fw_ver: loaded firmware sub-version
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* @fw_get_done flag set when request_firmware() is complete and
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* copied into fw_buf
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* risc_on: flag indicates RISC is on or off
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*
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*/
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struct s5p_mfc_dev {
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struct v4l2_device v4l2_dev;
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struct video_device *vfd_dec;
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struct video_device *vfd_enc;
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struct platform_device *plat_dev;
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struct device *mem_dev[BANK_CTX_NUM];
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void __iomem *regs_base;
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int irq;
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struct v4l2_ctrl_handler dec_ctrl_handler;
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struct v4l2_ctrl_handler enc_ctrl_handler;
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struct s5p_mfc_pm pm;
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const struct s5p_mfc_variant *variant;
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int num_inst;
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spinlock_t irqlock; /* lock when operating on context */
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spinlock_t condlock; /* lock when changing/checking if a context is
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ready to be processed */
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struct mutex mfc_mutex; /* video_device lock */
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int int_cond;
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int int_type;
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unsigned int int_err;
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wait_queue_head_t queue;
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struct s5p_mfc_priv_buf fw_buf;
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size_t mem_size;
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dma_addr_t mem_base;
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unsigned long *mem_bitmap;
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void *mem_virt;
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dma_addr_t dma_base[BANK_CTX_NUM];
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unsigned long hw_lock;
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struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
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int curr_ctx;
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unsigned long ctx_work_bits;
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atomic_t watchdog_cnt;
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struct timer_list watchdog_timer;
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struct workqueue_struct *watchdog_workqueue;
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struct work_struct watchdog_work;
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unsigned long enter_suspend;
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struct s5p_mfc_priv_buf ctx_buf;
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int warn_start;
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struct s5p_mfc_hw_ops *mfc_ops;
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struct s5p_mfc_hw_cmds *mfc_cmds;
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const struct s5p_mfc_regs *mfc_regs;
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enum s5p_mfc_fw_ver fw_ver;
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bool fw_get_done;
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bool risc_on; /* indicates if RISC is on or off */
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};
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/**
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* struct s5p_mfc_h264_enc_params - encoding parameters for h264
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*/
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struct s5p_mfc_h264_enc_params {
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enum v4l2_mpeg_video_h264_profile profile;
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enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
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s8 loop_filter_alpha;
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s8 loop_filter_beta;
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enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
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u8 max_ref_pic;
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u8 num_ref_pic_4p;
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int _8x8_transform;
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int rc_mb_dark;
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int rc_mb_smooth;
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int rc_mb_static;
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int rc_mb_activity;
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int vui_sar;
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u8 vui_sar_idc;
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u16 vui_ext_sar_width;
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u16 vui_ext_sar_height;
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int open_gop;
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u16 open_gop_size;
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u8 rc_frame_qp;
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u8 rc_min_qp;
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u8 rc_max_qp;
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u8 rc_p_frame_qp;
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u8 rc_b_frame_qp;
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enum v4l2_mpeg_video_h264_level level_v4l2;
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int level;
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u16 cpb_size;
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int interlace;
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u8 hier_qp;
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u8 hier_qp_type;
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u8 hier_qp_layer;
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u8 hier_qp_layer_qp[7];
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u8 sei_frame_packing;
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u8 sei_fp_curr_frame_0;
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u8 sei_fp_arrangement_type;
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u8 fmo;
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u8 fmo_map_type;
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u8 fmo_slice_grp;
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u8 fmo_chg_dir;
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u32 fmo_chg_rate;
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u32 fmo_run_len[4];
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u8 aso;
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u32 aso_slice_order[8];
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};
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/**
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* struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
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*/
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struct s5p_mfc_mpeg4_enc_params {
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/* MPEG4 Only */
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enum v4l2_mpeg_video_mpeg4_profile profile;
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int quarter_pixel;
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/* Common for MPEG4, H263 */
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u16 vop_time_res;
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u16 vop_frm_delta;
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u8 rc_frame_qp;
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u8 rc_min_qp;
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u8 rc_max_qp;
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u8 rc_p_frame_qp;
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u8 rc_b_frame_qp;
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enum v4l2_mpeg_video_mpeg4_level level_v4l2;
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int level;
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};
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/**
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* struct s5p_mfc_vp8_enc_params - encoding parameters for vp8
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*/
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struct s5p_mfc_vp8_enc_params {
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u8 imd_4x4;
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enum v4l2_vp8_num_partitions num_partitions;
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enum v4l2_vp8_num_ref_frames num_ref;
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u8 filter_level;
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u8 filter_sharpness;
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u32 golden_frame_ref_period;
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enum v4l2_vp8_golden_frame_sel golden_frame_sel;
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u8 hier_layer;
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u8 hier_layer_qp[3];
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u8 rc_min_qp;
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u8 rc_max_qp;
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u8 rc_frame_qp;
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u8 rc_p_frame_qp;
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u8 profile;
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};
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struct s5p_mfc_hevc_enc_params {
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enum v4l2_mpeg_video_hevc_profile profile;
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int level;
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enum v4l2_mpeg_video_h264_level level_v4l2;
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u8 tier;
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u32 rc_framerate;
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u8 rc_min_qp;
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u8 rc_max_qp;
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u8 rc_lcu_dark;
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u8 rc_lcu_smooth;
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u8 rc_lcu_static;
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u8 rc_lcu_activity;
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u8 rc_frame_qp;
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u8 rc_p_frame_qp;
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u8 rc_b_frame_qp;
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u8 max_partition_depth;
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u8 num_refs_for_p;
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u8 refreshtype;
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u16 refreshperiod;
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s32 lf_beta_offset_div2;
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s32 lf_tc_offset_div2;
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u8 loopfilter;
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u8 loopfilter_disable;
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u8 loopfilter_across;
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u8 nal_control_length_filed;
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u8 nal_control_user_ref;
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u8 nal_control_store_ref;
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u8 const_intra_period_enable;
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u8 lossless_cu_enable;
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u8 wavefront_enable;
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u8 enable_ltr;
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u8 hier_qp_enable;
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enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type;
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u8 num_hier_layer;
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u8 hier_qp_layer[7];
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u32 hier_bit_layer[7];
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u8 sign_data_hiding;
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u8 general_pb_enable;
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u8 temporal_id_enable;
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u8 strong_intra_smooth;
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u8 intra_pu_split_disable;
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u8 tmv_prediction_disable;
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u8 max_num_merge_mv;
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u8 eco_mode_enable;
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u8 encoding_nostartcode_enable;
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u8 size_of_length_field;
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u8 prepend_sps_pps_to_idr;
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};
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/**
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* struct s5p_mfc_enc_params - general encoding parameters
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*/
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struct s5p_mfc_enc_params {
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u16 width;
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u16 height;
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u32 mv_h_range;
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u32 mv_v_range;
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u16 gop_size;
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enum v4l2_mpeg_video_multi_slice_mode slice_mode;
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u16 slice_mb;
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u32 slice_bit;
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u16 intra_refresh_mb;
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int pad;
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u8 pad_luma;
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u8 pad_cb;
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u8 pad_cr;
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int rc_frame;
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int rc_mb;
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u32 rc_bitrate;
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u16 rc_reaction_coeff;
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u16 vbv_size;
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u32 vbv_delay;
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enum v4l2_mpeg_video_header_mode seq_hdr_mode;
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enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
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int fixed_target_bit;
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u8 num_b_frame;
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u32 rc_framerate_num;
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u32 rc_framerate_denom;
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struct {
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struct s5p_mfc_h264_enc_params h264;
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struct s5p_mfc_mpeg4_enc_params mpeg4;
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struct s5p_mfc_vp8_enc_params vp8;
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struct s5p_mfc_hevc_enc_params hevc;
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} codec;
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};
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/**
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* struct s5p_mfc_codec_ops - codec ops, used by encoding
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*/
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struct s5p_mfc_codec_ops {
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/* initialization routines */
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int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
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int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
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/* execution routines */
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int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
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int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
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};
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#define call_cop(c, op, args...) \
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(((c)->c_ops->op) ? \
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((c)->c_ops->op(args)) : 0)
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/**
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* struct s5p_mfc_ctx - This struct contains the instance context
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*
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* @dev: pointer to the s5p_mfc_dev of the device
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* @fh: struct v4l2_fh
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* @num: number of the context that this structure describes
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* @int_cond: variable used by the waitqueue
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* @int_type: type of the last interrupt
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* @int_err: error number received from MFC hw in the interrupt
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* @queue: waitqueue that can be used to wait for this context to
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* finish
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* @src_fmt: source pixelformat information
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* @dst_fmt: destination pixelformat information
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* @vq_src: vb2 queue for source buffers
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* @vq_dst: vb2 queue for destination buffers
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* @src_queue: driver internal queue for source buffers
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* @dst_queue: driver internal queue for destination buffers
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* @src_queue_cnt: number of buffers queued on the source internal queue
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* @dst_queue_cnt: number of buffers queued on the dest internal queue
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* @type: type of the instance - decoder or encoder
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* @state: state of the context
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* @inst_no: number of hw instance associated with the context
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* @img_width: width of the image that is decoded or encoded
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* @img_height: height of the image that is decoded or encoded
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* @buf_width: width of the buffer for processed image
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* @buf_height: height of the buffer for processed image
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* @luma_size: size of a luma plane
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* @chroma_size: size of a chroma plane
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* @mv_size: size of a motion vectors buffer
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* @consumed_stream: number of bytes that have been used so far from the
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* decoding buffer
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* @dpb_flush_flag: flag used to indicate that a DPB buffers are being
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* flushed
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* @head_processed: flag mentioning whether the header data is processed
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* completely or not
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* @bank1: handle to memory allocated for temporary buffers from
|
* memory bank 1
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* @bank2: handle to memory allocated for temporary buffers from
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* memory bank 2
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* @capture_state: state of the capture buffers queue
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* @output_state: state of the output buffers queue
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* @src_bufs: information on allocated source buffers
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* @dst_bufs: information on allocated destination buffers
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* @sequence: counter for the sequence number for v4l2
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* @dec_dst_flag: flags for buffers queued in the hardware
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* @dec_src_buf_size: size of the buffer for source buffers in decoding
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* @codec_mode: number of codec mode used by MFC hw
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* @slice_interface: slice interface flag
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* @loop_filter_mpeg4: loop filter for MPEG4 flag
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* @display_delay: value of the display delay for H264
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* @display_delay_enable: display delay for H264 enable flag
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* @after_packed_pb: flag used to track buffer when stream is in
|
* Packed PB format
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* @sei_fp_parse: enable/disable parsing of frame packing SEI information
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* @dpb_count: count of the DPB buffers required by MFC hw
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* @total_dpb_count: count of DPB buffers with additional buffers
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* requested by the application
|
* @ctx: context buffer information
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* @dsc: descriptor buffer information
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* @shm: shared memory buffer information
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* @mv_count: number of MV buffers allocated for decoding
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* @enc_params: encoding parameters for MFC
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* @enc_dst_buf_size: size of the buffers for encoder output
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* @luma_dpb_size: dpb buffer size for luma
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* @chroma_dpb_size: dpb buffer size for chroma
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* @me_buffer_size: size of the motion estimation buffer
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* @tmv_buffer_size: size of temporal predictor motion vector buffer
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* @frame_type: used to force the type of the next encoded frame
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* @ref_queue: list of the reference buffers for encoding
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* @ref_queue_cnt: number of the buffers in the reference list
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* @c_ops: ops for encoding
|
* @ctrls: array of controls, used when adding controls to the
|
* v4l2 control framework
|
* @ctrl_handler: handler for v4l2 framework
|
*/
|
struct s5p_mfc_ctx {
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struct s5p_mfc_dev *dev;
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struct v4l2_fh fh;
|
|
int num;
|
|
int int_cond;
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int int_type;
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unsigned int int_err;
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wait_queue_head_t queue;
|
|
struct s5p_mfc_fmt *src_fmt;
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struct s5p_mfc_fmt *dst_fmt;
|
|
struct vb2_queue vq_src;
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struct vb2_queue vq_dst;
|
|
struct list_head src_queue;
|
struct list_head dst_queue;
|
|
unsigned int src_queue_cnt;
|
unsigned int dst_queue_cnt;
|
|
enum s5p_mfc_inst_type type;
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enum s5p_mfc_inst_state state;
|
int inst_no;
|
|
/* Image parameters */
|
int img_width;
|
int img_height;
|
int buf_width;
|
int buf_height;
|
|
int luma_size;
|
int chroma_size;
|
int mv_size;
|
|
unsigned long consumed_stream;
|
|
unsigned int dpb_flush_flag;
|
unsigned int head_processed;
|
|
struct s5p_mfc_priv_buf bank1;
|
struct s5p_mfc_priv_buf bank2;
|
|
enum s5p_mfc_queue_state capture_state;
|
enum s5p_mfc_queue_state output_state;
|
|
struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
|
int src_bufs_cnt;
|
struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
|
int dst_bufs_cnt;
|
|
unsigned int sequence;
|
unsigned long dec_dst_flag;
|
size_t dec_src_buf_size;
|
|
/* Control values */
|
int codec_mode;
|
int slice_interface;
|
int loop_filter_mpeg4;
|
int display_delay;
|
int display_delay_enable;
|
int after_packed_pb;
|
int sei_fp_parse;
|
|
int pb_count;
|
int total_dpb_count;
|
int mv_count;
|
/* Buffers */
|
struct s5p_mfc_priv_buf ctx;
|
struct s5p_mfc_priv_buf dsc;
|
struct s5p_mfc_priv_buf shm;
|
|
struct s5p_mfc_enc_params enc_params;
|
|
size_t enc_dst_buf_size;
|
size_t luma_dpb_size;
|
size_t chroma_dpb_size;
|
size_t me_buffer_size;
|
size_t tmv_buffer_size;
|
|
enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
|
|
struct list_head ref_queue;
|
unsigned int ref_queue_cnt;
|
|
enum v4l2_mpeg_video_multi_slice_mode slice_mode;
|
union {
|
unsigned int mb;
|
unsigned int bits;
|
} slice_size;
|
|
const struct s5p_mfc_codec_ops *c_ops;
|
|
struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
|
struct v4l2_ctrl_handler ctrl_handler;
|
unsigned int frame_tag;
|
size_t scratch_buf_size;
|
};
|
|
/*
|
* struct s5p_mfc_fmt - structure used to store information about pixelformats
|
* used by the MFC
|
*/
|
struct s5p_mfc_fmt {
|
u32 fourcc;
|
u32 codec_mode;
|
enum s5p_mfc_fmt_type type;
|
u32 num_planes;
|
u32 versions;
|
};
|
|
/**
|
* struct mfc_control - structure used to store information about MFC controls
|
* it is used to initialize the control framework.
|
*/
|
struct mfc_control {
|
__u32 id;
|
enum v4l2_ctrl_type type;
|
__u8 name[32]; /* Whatever */
|
__s32 minimum; /* Note signedness */
|
__s32 maximum;
|
__s32 step;
|
__u32 menu_skip_mask;
|
__s32 default_value;
|
__u32 flags;
|
__u32 reserved[2];
|
__u8 is_volatile;
|
};
|
|
/* Macro for making hardware specific calls */
|
#define s5p_mfc_hw_call(f, op, args...) \
|
((f && f->op) ? f->op(args) : (typeof(f->op(args)))(-ENODEV))
|
|
#define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
|
#define ctrl_to_ctx(__ctrl) \
|
container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
|
|
void clear_work_bit(struct s5p_mfc_ctx *ctx);
|
void set_work_bit(struct s5p_mfc_ctx *ctx);
|
void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
|
void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
|
int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev);
|
void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
|
|
#define HAS_PORTNUM(dev) (dev ? (dev->variant ? \
|
(dev->variant->port_num ? 1 : 0) : 0) : 0)
|
#define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0)
|
#define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0)
|
#define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70 ? 1 : 0)
|
#define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80 ? 1 : 0)
|
#define IS_MFCV10(dev) (dev->variant->version >= 0xA0 ? 1 : 0)
|
#define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10(dev))
|
|
#define MFC_V5_BIT BIT(0)
|
#define MFC_V6_BIT BIT(1)
|
#define MFC_V7_BIT BIT(2)
|
#define MFC_V8_BIT BIT(3)
|
#define MFC_V10_BIT BIT(5)
|
|
#define MFC_V5PLUS_BITS (MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | \
|
MFC_V8_BIT | MFC_V10_BIT)
|
#define MFC_V6PLUS_BITS (MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT | \
|
MFC_V10_BIT)
|
#define MFC_V7PLUS_BITS (MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT)
|
|
#endif /* S5P_MFC_COMMON_H_ */
|
