/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Register definition file for s3c24xx/s3c64xx SoC CAMIF driver
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*
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* Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
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* Copyright (C) 2012 Tomasz Figa <tomasz.figa@gmail.com>
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*/
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#ifndef CAMIF_REGS_H_
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#define CAMIF_REGS_H_
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#include <linux/bitops.h>
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#include "camif-core.h"
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#include <media/drv-intf/s3c_camif.h>
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/*
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* The id argument indicates the processing path:
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* id = 0 - codec (FIMC C), 1 - preview (FIMC P).
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*/
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/* Camera input format */
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#define S3C_CAMIF_REG_CISRCFMT 0x00
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#define CISRCFMT_ITU601_8BIT BIT(31)
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#define CISRCFMT_ITU656_8BIT (0 << 31)
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#define CISRCFMT_ORDER422_YCBYCR (0 << 14)
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#define CISRCFMT_ORDER422_YCRYCB (1 << 14)
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#define CISRCFMT_ORDER422_CBYCRY (2 << 14)
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#define CISRCFMT_ORDER422_CRYCBY (3 << 14)
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#define CISRCFMT_ORDER422_MASK (3 << 14)
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#define CISRCFMT_SIZE_CAM_MASK (0x1fff << 16 | 0x1fff)
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/* Window offset */
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#define S3C_CAMIF_REG_CIWDOFST 0x04
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#define CIWDOFST_WINOFSEN BIT(31)
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#define CIWDOFST_CLROVCOFIY BIT(30)
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#define CIWDOFST_CLROVRLB_PR BIT(28)
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/* #define CIWDOFST_CLROVPRFIY BIT(27) */
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#define CIWDOFST_CLROVCOFICB BIT(15)
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#define CIWDOFST_CLROVCOFICR BIT(14)
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#define CIWDOFST_CLROVPRFICB BIT(13)
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#define CIWDOFST_CLROVPRFICR BIT(12)
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#define CIWDOFST_OFST_MASK (0x7ff << 16 | 0x7ff)
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/* Window offset 2 */
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#define S3C_CAMIF_REG_CIWDOFST2 0x14
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#define CIWDOFST2_OFST2_MASK (0xfff << 16 | 0xfff)
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/* Global control */
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#define S3C_CAMIF_REG_CIGCTRL 0x08
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#define CIGCTRL_SWRST BIT(31)
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#define CIGCTRL_CAMRST BIT(30)
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#define CIGCTRL_TESTPATTERN_NORMAL (0 << 27)
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#define CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27)
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#define CIGCTRL_TESTPATTERN_HOR_INC (2 << 27)
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#define CIGCTRL_TESTPATTERN_VER_INC (3 << 27)
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#define CIGCTRL_TESTPATTERN_MASK (3 << 27)
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#define CIGCTRL_INVPOLPCLK BIT(26)
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#define CIGCTRL_INVPOLVSYNC BIT(25)
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#define CIGCTRL_INVPOLHREF BIT(24)
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#define CIGCTRL_IRQ_OVFEN BIT(22)
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#define CIGCTRL_HREF_MASK BIT(21)
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#define CIGCTRL_IRQ_LEVEL BIT(20)
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/* IRQ_CLR_C, IRQ_CLR_P */
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#define CIGCTRL_IRQ_CLR(id) BIT(19 - (id))
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#define CIGCTRL_FIELDMODE BIT(2)
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#define CIGCTRL_INVPOLFIELD BIT(1)
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#define CIGCTRL_CAM_INTERLACE BIT(0)
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/* Y DMA output frame start address. n = 0..3. */
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#define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4)
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/* Cb plane output DMA start address. n = 0..3. Only codec path. */
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#define S3C_CAMIF_REG_CICBSA(id, n) (0x28 + (id) * 0x54 + (n) * 4)
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/* Cr plane output DMA start address. n = 0..3. Only codec path. */
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#define S3C_CAMIF_REG_CICRSA(id, n) (0x38 + (id) * 0x54 + (n) * 4)
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/* CICOTRGFMT, CIPRTRGFMT - Target format */
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#define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs)))
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#define CITRGFMT_IN422 BIT(31) /* only for s3c24xx */
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#define CITRGFMT_OUT422 BIT(30) /* only for s3c24xx */
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#define CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) /* only for s3c6410 */
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#define CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) /* only for s3c6410 */
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#define CITRGFMT_OUTFORMAT_YCBCR422I (2 << 29) /* only for s3c6410 */
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#define CITRGFMT_OUTFORMAT_RGB (3 << 29) /* only for s3c6410 */
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#define CITRGFMT_OUTFORMAT_MASK (3 << 29) /* only for s3c6410 */
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#define CITRGFMT_TARGETHSIZE(x) ((x) << 16)
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#define CITRGFMT_FLIP_NORMAL (0 << 14)
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#define CITRGFMT_FLIP_X_MIRROR (1 << 14)
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#define CITRGFMT_FLIP_Y_MIRROR (2 << 14)
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#define CITRGFMT_FLIP_180 (3 << 14)
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#define CITRGFMT_FLIP_MASK (3 << 14)
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/* Preview path only */
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#define CITRGFMT_ROT90_PR BIT(13)
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#define CITRGFMT_TARGETVSIZE(x) ((x) << 0)
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#define CITRGFMT_TARGETSIZE_MASK ((0x1fff << 16) | 0x1fff)
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/* CICOCTRL, CIPRCTRL. Output DMA control. */
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#define S3C_CAMIF_REG_CICTRL(id, _offs) (0x4c + (id) * (0x34 + (_offs)))
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#define CICTRL_BURST_MASK (0xfffff << 4)
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/* xBURSTn - 5-bits width */
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#define CICTRL_YBURST1(x) ((x) << 19)
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#define CICTRL_YBURST2(x) ((x) << 14)
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#define CICTRL_RGBBURST1(x) ((x) << 19)
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#define CICTRL_RGBBURST2(x) ((x) << 14)
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#define CICTRL_CBURST1(x) ((x) << 9)
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#define CICTRL_CBURST2(x) ((x) << 4)
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#define CICTRL_LASTIRQ_ENABLE BIT(2)
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#define CICTRL_ORDER422_MASK (3 << 0)
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/* CICOSCPRERATIO, CIPRSCPRERATIO. Pre-scaler control 1. */
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#define S3C_CAMIF_REG_CISCPRERATIO(id, _offs) (0x50 + (id) * (0x34 + (_offs)))
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/* CICOSCPREDST, CIPRSCPREDST. Pre-scaler control 2. */
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#define S3C_CAMIF_REG_CISCPREDST(id, _offs) (0x54 + (id) * (0x34 + (_offs)))
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/* CICOSCCTRL, CIPRSCCTRL. Main scaler control. */
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#define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs)))
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#define CISCCTRL_SCALERBYPASS BIT(31)
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/* s3c244x preview path only, s3c64xx both */
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#define CIPRSCCTRL_SAMPLE BIT(31)
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/* 0 - 16-bit RGB, 1 - 24-bit RGB */
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#define CIPRSCCTRL_RGB_FORMAT_24BIT BIT(30) /* only for s3c244x */
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#define CIPRSCCTRL_SCALEUP_H BIT(29) /* only for s3c244x */
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#define CIPRSCCTRL_SCALEUP_V BIT(28) /* only for s3c244x */
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/* s3c64xx */
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#define CISCCTRL_SCALEUP_H BIT(30)
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#define CISCCTRL_SCALEUP_V BIT(29)
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#define CISCCTRL_SCALEUP_MASK (0x3 << 29)
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#define CISCCTRL_CSCR2Y_WIDE BIT(28)
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#define CISCCTRL_CSCY2R_WIDE BIT(27)
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#define CISCCTRL_LCDPATHEN_FIFO BIT(26)
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#define CISCCTRL_INTERLACE BIT(25)
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#define CISCCTRL_SCALERSTART BIT(15)
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#define CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
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#define CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
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#define CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
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#define CISCCTRL_INRGB_FMT_MASK (3 << 13)
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#define CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
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#define CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
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#define CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
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#define CISCCTRL_OUTRGB_FMT_MASK (3 << 11)
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#define CISCCTRL_EXTRGB_EXTENSION BIT(10)
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#define CISCCTRL_ONE2ONE BIT(9)
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#define CISCCTRL_MAIN_RATIO_MASK (0x1ff << 16 | 0x1ff)
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/* CICOTAREA, CIPRTAREA. Target area for DMA (Hsize x Vsize). */
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#define S3C_CAMIF_REG_CITAREA(id, _offs) (0x5c + (id) * (0x34 + (_offs)))
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#define CITAREA_MASK 0xfffffff
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/* Codec (id = 0) or preview (id = 1) path status. */
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#define S3C_CAMIF_REG_CISTATUS(id, _offs) (0x64 + (id) * (0x34 + (_offs)))
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#define CISTATUS_OVFIY_STATUS BIT(31)
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#define CISTATUS_OVFICB_STATUS BIT(30)
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#define CISTATUS_OVFICR_STATUS BIT(29)
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#define CISTATUS_OVF_MASK (0x7 << 29)
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#define CIPRSTATUS_OVF_MASK (0x3 << 30)
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#define CISTATUS_VSYNC_STATUS BIT(28)
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#define CISTATUS_FRAMECNT_MASK (3 << 26)
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#define CISTATUS_FRAMECNT(__reg) (((__reg) >> 26) & 0x3)
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#define CISTATUS_WINOFSTEN_STATUS BIT(25)
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#define CISTATUS_IMGCPTEN_STATUS BIT(22)
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#define CISTATUS_IMGCPTENSC_STATUS BIT(21)
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#define CISTATUS_VSYNC_A_STATUS BIT(20)
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#define CISTATUS_FRAMEEND_STATUS BIT(19) /* 17 on s3c64xx */
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/* Image capture enable */
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#define S3C_CAMIF_REG_CIIMGCPT(_offs) (0xa0 + (_offs))
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#define CIIMGCPT_IMGCPTEN BIT(31)
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#define CIIMGCPT_IMGCPTEN_SC(id) BIT(30 - (id))
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/* Frame control: 1 - one-shot, 0 - free run */
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#define CIIMGCPT_CPT_FREN_ENABLE(id) BIT(25 - (id))
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#define CIIMGCPT_CPT_FRMOD_ENABLE (0 << 18)
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#define CIIMGCPT_CPT_FRMOD_CNT BIT(18)
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/* Capture sequence */
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#define S3C_CAMIF_REG_CICPTSEQ 0xc4
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/* Image effects */
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#define S3C_CAMIF_REG_CIIMGEFF(_offs) (0xb0 + (_offs))
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#define CIIMGEFF_IE_ENABLE(id) BIT(30 + (id))
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#define CIIMGEFF_IE_ENABLE_MASK (3 << 30)
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/* Image effect: 1 - after scaler, 0 - before scaler */
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#define CIIMGEFF_IE_AFTER_SC BIT(29)
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#define CIIMGEFF_FIN_MASK (7 << 26)
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#define CIIMGEFF_FIN_BYPASS (0 << 26)
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#define CIIMGEFF_FIN_ARBITRARY (1 << 26)
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#define CIIMGEFF_FIN_NEGATIVE (2 << 26)
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#define CIIMGEFF_FIN_ARTFREEZE (3 << 26)
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#define CIIMGEFF_FIN_EMBOSSING (4 << 26)
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#define CIIMGEFF_FIN_SILHOUETTE (5 << 26)
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#define CIIMGEFF_PAT_CBCR_MASK ((0xff << 13) | 0xff)
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#define CIIMGEFF_PAT_CB(x) ((x) << 13)
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#define CIIMGEFF_PAT_CR(x) (x)
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/* MSCOY0SA, MSPRY0SA. Y/Cb/Cr frame start address for input DMA. */
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#define S3C_CAMIF_REG_MSY0SA(id) (0xd4 + ((id) * 0x2c))
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#define S3C_CAMIF_REG_MSCB0SA(id) (0xd8 + ((id) * 0x2c))
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#define S3C_CAMIF_REG_MSCR0SA(id) (0xdc + ((id) * 0x2c))
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/* MSCOY0END, MSCOY0END. Y/Cb/Cr frame end address for input DMA. */
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#define S3C_CAMIF_REG_MSY0END(id) (0xe0 + ((id) * 0x2c))
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#define S3C_CAMIF_REG_MSCB0END(id) (0xe4 + ((id) * 0x2c))
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#define S3C_CAMIF_REG_MSCR0END(id) (0xe8 + ((id) * 0x2c))
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/* MSPRYOFF, MSPRYOFF. Y/Cb/Cr offset. n: 0 - codec, 1 - preview. */
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#define S3C_CAMIF_REG_MSYOFF(id) (0x118 + ((id) * 0x2c))
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#define S3C_CAMIF_REG_MSCBOFF(id) (0x11c + ((id) * 0x2c))
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#define S3C_CAMIF_REG_MSCROFF(id) (0x120 + ((id) * 0x2c))
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/* Real input DMA data size. n = 0 - codec, 1 - preview. */
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#define S3C_CAMIF_REG_MSWIDTH(id) (0xf8 + (id) * 0x2c)
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#define AUTOLOAD_ENABLE BIT(31)
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#define ADDR_CH_DIS BIT(30)
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#define MSHEIGHT(x) (((x) & 0x3ff) << 16)
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#define MSWIDTH(x) ((x) & 0x3ff)
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/* Input DMA control. n = 0 - codec, 1 - preview */
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#define S3C_CAMIF_REG_MSCTRL(id) (0xfc + (id) * 0x2c)
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#define MSCTRL_ORDER422_M_YCBYCR (0 << 4)
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#define MSCTRL_ORDER422_M_YCRYCB (1 << 4)
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#define MSCTRL_ORDER422_M_CBYCRY (2 << 4)
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#define MSCTRL_ORDER422_M_CRYCBY (3 << 4)
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/* 0 - camera, 1 - DMA */
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#define MSCTRL_SEL_DMA_CAM BIT(3)
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#define MSCTRL_INFORMAT_M_YCBCR420 (0 << 1)
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#define MSCTRL_INFORMAT_M_YCBCR422 (1 << 1)
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#define MSCTRL_INFORMAT_M_YCBCR422I (2 << 1)
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#define MSCTRL_INFORMAT_M_RGB (3 << 1)
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#define MSCTRL_ENVID_M BIT(0)
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/* CICOSCOSY, CIPRSCOSY. Scan line Y/Cb/Cr offset. */
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#define S3C_CAMIF_REG_CISSY(id) (0x12c + (id) * 0x0c)
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#define S3C_CAMIF_REG_CISSCB(id) (0x130 + (id) * 0x0c)
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#define S3C_CAMIF_REG_CISSCR(id) (0x134 + (id) * 0x0c)
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#define S3C_CISS_OFFS_INITIAL(x) ((x) << 16)
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#define S3C_CISS_OFFS_LINE(x) ((x) << 0)
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/* ------------------------------------------------------------------ */
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void camif_hw_reset(struct camif_dev *camif);
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void camif_hw_clear_pending_irq(struct camif_vp *vp);
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void camif_hw_clear_fifo_overflow(struct camif_vp *vp);
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void camif_hw_set_lastirq(struct camif_vp *vp, int enable);
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void camif_hw_set_input_path(struct camif_vp *vp);
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void camif_hw_enable_scaler(struct camif_vp *vp, bool on);
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void camif_hw_enable_capture(struct camif_vp *vp);
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void camif_hw_disable_capture(struct camif_vp *vp);
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void camif_hw_set_camera_bus(struct camif_dev *camif);
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void camif_hw_set_source_format(struct camif_dev *camif);
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void camif_hw_set_camera_crop(struct camif_dev *camif);
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void camif_hw_set_scaler(struct camif_vp *vp);
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void camif_hw_set_flip(struct camif_vp *vp);
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void camif_hw_set_output_dma(struct camif_vp *vp);
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void camif_hw_set_target_format(struct camif_vp *vp);
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void camif_hw_set_test_pattern(struct camif_dev *camif, unsigned int pattern);
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void camif_hw_set_effect(struct camif_dev *camif, unsigned int effect,
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unsigned int cr, unsigned int cb);
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void camif_hw_set_output_addr(struct camif_vp *vp, struct camif_addr *paddr,
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int index);
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void camif_hw_dump_regs(struct camif_dev *camif, const char *label);
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static inline u32 camif_hw_get_status(struct camif_vp *vp)
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{
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return readl(vp->camif->io_base + S3C_CAMIF_REG_CISTATUS(vp->id,
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vp->offset));
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}
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#endif /* CAMIF_REGS_H_ */
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