/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* ispcsi2.h
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*
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* TI OMAP3 ISP - CSI2 module
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*
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* Copyright (C) 2010 Nokia Corporation
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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* Sakari Ailus <sakari.ailus@iki.fi>
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*/
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#ifndef OMAP3_ISP_CSI2_H
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#define OMAP3_ISP_CSI2_H
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#include <linux/types.h>
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#include <linux/videodev2.h>
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struct isp_csiphy;
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/* This is not an exhaustive list */
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enum isp_csi2_pix_formats {
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CSI2_PIX_FMT_OTHERS = 0,
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CSI2_PIX_FMT_YUV422_8BIT = 0x1e,
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CSI2_PIX_FMT_YUV422_8BIT_VP = 0x9e,
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CSI2_PIX_FMT_RAW10_EXP16 = 0xab,
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CSI2_PIX_FMT_RAW10_EXP16_VP = 0x12f,
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CSI2_PIX_FMT_RAW8 = 0x2a,
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CSI2_PIX_FMT_RAW8_DPCM10_EXP16 = 0x2aa,
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CSI2_PIX_FMT_RAW8_DPCM10_VP = 0x32a,
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CSI2_PIX_FMT_RAW8_VP = 0x12a,
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CSI2_USERDEF_8BIT_DATA1_DPCM10_VP = 0x340,
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CSI2_USERDEF_8BIT_DATA1_DPCM10 = 0x2c0,
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CSI2_USERDEF_8BIT_DATA1 = 0x40,
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};
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enum isp_csi2_irqevents {
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OCP_ERR_IRQ = 0x4000,
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SHORT_PACKET_IRQ = 0x2000,
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ECC_CORRECTION_IRQ = 0x1000,
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ECC_NO_CORRECTION_IRQ = 0x800,
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COMPLEXIO2_ERR_IRQ = 0x400,
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COMPLEXIO1_ERR_IRQ = 0x200,
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FIFO_OVF_IRQ = 0x100,
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CONTEXT7 = 0x80,
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CONTEXT6 = 0x40,
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CONTEXT5 = 0x20,
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CONTEXT4 = 0x10,
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CONTEXT3 = 0x8,
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CONTEXT2 = 0x4,
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CONTEXT1 = 0x2,
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CONTEXT0 = 0x1,
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};
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enum isp_csi2_ctx_irqevents {
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CTX_ECC_CORRECTION = 0x100,
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CTX_LINE_NUMBER = 0x80,
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CTX_FRAME_NUMBER = 0x40,
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CTX_CS = 0x20,
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CTX_LE = 0x8,
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CTX_LS = 0x4,
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CTX_FE = 0x2,
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CTX_FS = 0x1,
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};
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enum isp_csi2_frame_mode {
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ISP_CSI2_FRAME_IMMEDIATE,
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ISP_CSI2_FRAME_AFTERFEC,
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};
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#define ISP_CSI2_MAX_CTX_NUM 7
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struct isp_csi2_ctx_cfg {
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u8 ctxnum; /* context number 0 - 7 */
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u8 dpcm_decompress;
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/* Fields in CSI2_CTx_CTRL2 - locked by CSI2_CTx_CTRL1.CTX_EN */
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u8 virtual_id;
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u16 format_id; /* as in CSI2_CTx_CTRL2[9:0] */
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u8 dpcm_predictor; /* 1: simple, 0: advanced */
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/* Fields in CSI2_CTx_CTRL1/3 - Shadowed */
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u16 alpha;
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u16 data_offset;
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u32 ping_addr;
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u32 pong_addr;
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u8 eof_enabled;
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u8 eol_enabled;
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u8 checksum_enabled;
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u8 enabled;
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};
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struct isp_csi2_timing_cfg {
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u8 ionum; /* IO1 or IO2 as in CSI2_TIMING */
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unsigned force_rx_mode:1;
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unsigned stop_state_16x:1;
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unsigned stop_state_4x:1;
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u16 stop_state_counter;
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};
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struct isp_csi2_ctrl_cfg {
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bool vp_clk_enable;
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bool vp_only_enable;
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u8 vp_out_ctrl;
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enum isp_csi2_frame_mode frame_mode;
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bool ecc_enable;
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bool if_enable;
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};
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#define CSI2_PAD_SINK 0
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#define CSI2_PAD_SOURCE 1
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#define CSI2_PADS_NUM 2
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#define CSI2_OUTPUT_CCDC (1 << 0)
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#define CSI2_OUTPUT_MEMORY (1 << 1)
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struct isp_csi2_device {
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struct v4l2_subdev subdev;
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struct media_pad pads[CSI2_PADS_NUM];
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struct v4l2_mbus_framefmt formats[CSI2_PADS_NUM];
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struct isp_video video_out;
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struct isp_device *isp;
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u8 available; /* Is the IP present on the silicon? */
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/* mem resources - enums as defined in enum isp_mem_resources */
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u8 regs1;
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u8 regs2;
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u32 output; /* output to CCDC, memory or both? */
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bool dpcm_decompress;
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unsigned int frame_skip;
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struct isp_csiphy *phy;
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struct isp_csi2_ctx_cfg contexts[ISP_CSI2_MAX_CTX_NUM + 1];
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struct isp_csi2_timing_cfg timing[2];
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struct isp_csi2_ctrl_cfg ctrl;
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enum isp_pipeline_stream_state state;
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wait_queue_head_t wait;
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atomic_t stopping;
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};
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void omap3isp_csi2_isr(struct isp_csi2_device *csi2);
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int omap3isp_csi2_reset(struct isp_csi2_device *csi2);
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int omap3isp_csi2_init(struct isp_device *isp);
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void omap3isp_csi2_cleanup(struct isp_device *isp);
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void omap3isp_csi2_unregister_entities(struct isp_csi2_device *csi2);
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int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2,
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struct v4l2_device *vdev);
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#endif /* OMAP3_ISP_CSI2_H */
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