/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* isp.h
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*
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* TI OMAP3 ISP - Core
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*
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* Copyright (C) 2009-2010 Nokia Corporation
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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* Sakari Ailus <sakari.ailus@iki.fi>
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*/
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#ifndef OMAP3_ISP_CORE_H
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#define OMAP3_ISP_CORE_H
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#include <media/media-entity.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-device.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/wait.h>
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#include "omap3isp.h"
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#include "ispstat.h"
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#include "ispccdc.h"
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#include "ispreg.h"
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#include "ispresizer.h"
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#include "isppreview.h"
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#include "ispcsiphy.h"
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#include "ispcsi2.h"
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#include "ispccp2.h"
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#define ISP_TOK_TERM 0xFFFFFFFF /*
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* terminating token for ISP
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* modules reg list
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*/
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#define to_isp_device(ptr_module) \
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container_of(ptr_module, struct isp_device, isp_##ptr_module)
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#define to_device(ptr_module) \
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(to_isp_device(ptr_module)->dev)
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enum isp_mem_resources {
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OMAP3_ISP_IOMEM_MAIN,
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OMAP3_ISP_IOMEM_CCP2,
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OMAP3_ISP_IOMEM_CCDC,
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OMAP3_ISP_IOMEM_HIST,
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OMAP3_ISP_IOMEM_H3A,
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OMAP3_ISP_IOMEM_PREV,
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OMAP3_ISP_IOMEM_RESZ,
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OMAP3_ISP_IOMEM_SBL,
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OMAP3_ISP_IOMEM_CSI2A_REGS1,
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OMAP3_ISP_IOMEM_CSIPHY2,
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OMAP3_ISP_IOMEM_CSI2A_REGS2,
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OMAP3_ISP_IOMEM_CSI2C_REGS1,
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OMAP3_ISP_IOMEM_CSIPHY1,
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OMAP3_ISP_IOMEM_CSI2C_REGS2,
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OMAP3_ISP_IOMEM_LAST
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};
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enum isp_sbl_resource {
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OMAP3_ISP_SBL_CSI1_READ = 0x1,
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OMAP3_ISP_SBL_CSI1_WRITE = 0x2,
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OMAP3_ISP_SBL_CSI2A_WRITE = 0x4,
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OMAP3_ISP_SBL_CSI2C_WRITE = 0x8,
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OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10,
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OMAP3_ISP_SBL_CCDC_WRITE = 0x20,
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OMAP3_ISP_SBL_PREVIEW_READ = 0x40,
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OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80,
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OMAP3_ISP_SBL_RESIZER_READ = 0x100,
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OMAP3_ISP_SBL_RESIZER_WRITE = 0x200,
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};
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enum isp_subclk_resource {
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OMAP3_ISP_SUBCLK_CCDC = (1 << 0),
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OMAP3_ISP_SUBCLK_AEWB = (1 << 1),
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OMAP3_ISP_SUBCLK_AF = (1 << 2),
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OMAP3_ISP_SUBCLK_HIST = (1 << 3),
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OMAP3_ISP_SUBCLK_PREVIEW = (1 << 4),
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OMAP3_ISP_SUBCLK_RESIZER = (1 << 5),
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};
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/* ISP: OMAP 34xx ES 1.0 */
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#define ISP_REVISION_1_0 0x10
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/* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
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#define ISP_REVISION_2_0 0x20
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/* ISP2P: OMAP 36xx */
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#define ISP_REVISION_15_0 0xF0
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#define ISP_PHY_TYPE_3430 0
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#define ISP_PHY_TYPE_3630 1
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struct regmap;
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/*
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* struct isp_res_mapping - Map ISP io resources to ISP revision.
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* @isp_rev: ISP_REVISION_x_x
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* @offset: register offsets of various ISP sub-blocks
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* @phy_type: ISP_PHY_TYPE_{3430,3630}
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*/
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struct isp_res_mapping {
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u32 isp_rev;
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u32 offset[OMAP3_ISP_IOMEM_LAST];
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u32 phy_type;
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};
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/*
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* struct isp_reg - Structure for ISP register values.
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* @reg: 32-bit Register address.
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* @val: 32-bit Register value.
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*/
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struct isp_reg {
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enum isp_mem_resources mmio_range;
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u32 reg;
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u32 val;
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};
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enum isp_xclk_id {
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ISP_XCLK_A,
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ISP_XCLK_B,
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};
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struct isp_xclk {
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struct isp_device *isp;
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struct clk_hw hw;
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struct clk *clk;
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enum isp_xclk_id id;
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spinlock_t lock; /* Protects enabled and divider */
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bool enabled;
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unsigned int divider;
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};
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/*
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* struct isp_device - ISP device structure.
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* @dev: Device pointer specific to the OMAP3 ISP.
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* @revision: Stores current ISP module revision.
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* @irq_num: Currently used IRQ number.
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* @mmio_base: Array with kernel base addresses for ioremapped ISP register
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* regions.
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* @mmio_hist_base_phys: Physical L4 bus address for ISP hist block register
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* region.
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* @syscon: Regmap for the syscon register space
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* @syscon_offset: Offset of the CSIPHY control register in syscon
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* @phy_type: ISP_PHY_TYPE_{3430,3630}
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* @mapping: IOMMU mapping
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* @stat_lock: Spinlock for handling statistics
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* @isp_mutex: Mutex for serializing requests to ISP.
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* @stop_failure: Indicates that an entity failed to stop.
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* @crashed: Crashed ent_enum
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* @has_context: Context has been saved at least once and can be restored.
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* @ref_count: Reference count for handling multiple ISP requests.
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* @cam_ick: Pointer to camera interface clock structure.
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* @cam_mclk: Pointer to camera functional clock structure.
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* @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
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* @l3_ick: Pointer to OMAP3 L3 bus interface clock.
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* @xclks: External clocks provided by the ISP
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* @irq: Currently attached ISP ISR callbacks information structure.
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* @isp_af: Pointer to current settings for ISP AutoFocus SCM.
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* @isp_hist: Pointer to current settings for ISP Histogram SCM.
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* @isp_h3a: Pointer to current settings for ISP Auto Exposure and
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* White Balance SCM.
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* @isp_res: Pointer to current settings for ISP Resizer.
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* @isp_prev: Pointer to current settings for ISP Preview.
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* @isp_ccdc: Pointer to current settings for ISP CCDC.
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* @platform_cb: ISP driver callback function pointers for platform code
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*
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* This structure is used to store the OMAP ISP Information.
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*/
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struct isp_device {
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struct v4l2_device v4l2_dev;
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struct v4l2_async_notifier notifier;
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struct media_device media_dev;
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struct device *dev;
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u32 revision;
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/* platform HW resources */
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unsigned int irq_num;
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void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
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unsigned long mmio_hist_base_phys;
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struct regmap *syscon;
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u32 syscon_offset;
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u32 phy_type;
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struct dma_iommu_mapping *mapping;
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/* ISP Obj */
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spinlock_t stat_lock; /* common lock for statistic drivers */
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struct mutex isp_mutex; /* For handling ref_count field */
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bool stop_failure;
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struct media_entity_enum crashed;
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int has_context;
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int ref_count;
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unsigned int autoidle;
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#define ISP_CLK_CAM_ICK 0
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#define ISP_CLK_CAM_MCLK 1
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#define ISP_CLK_CSI2_FCK 2
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#define ISP_CLK_L3_ICK 3
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struct clk *clock[4];
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struct isp_xclk xclks[2];
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/* ISP modules */
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struct ispstat isp_af;
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struct ispstat isp_aewb;
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struct ispstat isp_hist;
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struct isp_res_device isp_res;
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struct isp_prev_device isp_prev;
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struct isp_ccdc_device isp_ccdc;
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struct isp_csi2_device isp_csi2a;
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struct isp_csi2_device isp_csi2c;
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struct isp_ccp2_device isp_ccp2;
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struct isp_csiphy isp_csiphy1;
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struct isp_csiphy isp_csiphy2;
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unsigned int sbl_resources;
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unsigned int subclk_resources;
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};
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struct isp_async_subdev {
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struct v4l2_async_subdev asd;
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struct isp_bus_cfg bus;
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};
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#define v4l2_subdev_to_bus_cfg(sd) \
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(&container_of((sd)->asd, struct isp_async_subdev, asd)->bus)
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#define v4l2_dev_to_isp_device(dev) \
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container_of(dev, struct isp_device, v4l2_dev)
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void omap3isp_hist_dma_done(struct isp_device *isp);
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void omap3isp_flush(struct isp_device *isp);
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int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
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atomic_t *stopping);
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int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
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atomic_t *stopping);
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int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
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enum isp_pipeline_stream_state state);
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void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe);
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void omap3isp_configure_bridge(struct isp_device *isp,
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enum ccdc_input_entity input,
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const struct isp_parallel_cfg *buscfg,
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unsigned int shift, unsigned int bridge);
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struct isp_device *omap3isp_get(struct isp_device *isp);
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void omap3isp_put(struct isp_device *isp);
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void omap3isp_print_status(struct isp_device *isp);
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void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
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void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
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void omap3isp_subclk_enable(struct isp_device *isp,
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enum isp_subclk_resource res);
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void omap3isp_subclk_disable(struct isp_device *isp,
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enum isp_subclk_resource res);
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int omap3isp_register_entities(struct platform_device *pdev,
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struct v4l2_device *v4l2_dev);
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void omap3isp_unregister_entities(struct platform_device *pdev);
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/*
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* isp_reg_readl - Read value of an OMAP3 ISP register
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* @isp: Device pointer specific to the OMAP3 ISP.
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* @isp_mmio_range: Range to which the register offset refers to.
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* @reg_offset: Register offset to read from.
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*
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* Returns an unsigned 32 bit value with the required register contents.
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*/
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static inline
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u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
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u32 reg_offset)
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{
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return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
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}
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/*
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* isp_reg_writel - Write value to an OMAP3 ISP register
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* @isp: Device pointer specific to the OMAP3 ISP.
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* @reg_value: 32 bit value to write to the register.
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* @isp_mmio_range: Range to which the register offset refers to.
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* @reg_offset: Register offset to write into.
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*/
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static inline
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void isp_reg_writel(struct isp_device *isp, u32 reg_value,
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enum isp_mem_resources isp_mmio_range, u32 reg_offset)
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{
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__raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
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}
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/*
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* isp_reg_clr - Clear individual bits in an OMAP3 ISP register
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* @isp: Device pointer specific to the OMAP3 ISP.
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* @mmio_range: Range to which the register offset refers to.
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* @reg: Register offset to work on.
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* @clr_bits: 32 bit value which would be cleared in the register.
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*/
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static inline
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void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
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u32 reg, u32 clr_bits)
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{
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u32 v = isp_reg_readl(isp, mmio_range, reg);
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isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
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}
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/*
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* isp_reg_set - Set individual bits in an OMAP3 ISP register
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* @isp: Device pointer specific to the OMAP3 ISP.
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* @mmio_range: Range to which the register offset refers to.
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* @reg: Register offset to work on.
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* @set_bits: 32 bit value which would be set in the register.
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*/
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static inline
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void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
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u32 reg, u32 set_bits)
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{
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u32 v = isp_reg_readl(isp, mmio_range, reg);
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isp_reg_writel(isp, v | set_bits, mmio_range, reg);
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}
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/*
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* isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
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* @isp: Device pointer specific to the OMAP3 ISP.
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* @mmio_range: Range to which the register offset refers to.
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* @reg: Register offset to work on.
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* @clr_bits: 32 bit value which would be cleared in the register.
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* @set_bits: 32 bit value which would be set in the register.
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*
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* The clear operation is done first, and then the set operation.
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*/
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static inline
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void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
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u32 reg, u32 clr_bits, u32 set_bits)
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{
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u32 v = isp_reg_readl(isp, mmio_range, reg);
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isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
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}
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static inline enum v4l2_buf_type
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isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
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{
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if (pad >= subdev->entity.num_pads)
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return 0;
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if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
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return V4L2_BUF_TYPE_VIDEO_OUTPUT;
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else
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return V4L2_BUF_TYPE_VIDEO_CAPTURE;
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}
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#endif /* OMAP3_ISP_CORE_H */
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