// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: Daniel Hsiao <daniel.hsiao@mediatek.com>
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* PoChun Lin <pochun.lin@mediatek.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include "../mtk_vcodec_drv.h"
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#include "../mtk_vcodec_util.h"
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#include "../mtk_vcodec_intr.h"
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#include "../mtk_vcodec_enc.h"
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#include "../mtk_vcodec_enc_pm.h"
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#include "../venc_drv_base.h"
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#include "../venc_ipi_msg.h"
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#include "../venc_vpu_if.h"
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#define VENC_BITSTREAM_FRAME_SIZE 0x0098
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#define VENC_BITSTREAM_HEADER_LEN 0x00e8
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/* This ac_tag is vp8 frame tag. */
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#define MAX_AC_TAG_SIZE 10
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/*
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* enum venc_vp8_vpu_work_buf - vp8 encoder buffer index
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*/
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enum venc_vp8_vpu_work_buf {
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VENC_VP8_VPU_WORK_BUF_LUMA,
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VENC_VP8_VPU_WORK_BUF_LUMA2,
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VENC_VP8_VPU_WORK_BUF_LUMA3,
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VENC_VP8_VPU_WORK_BUF_CHROMA,
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VENC_VP8_VPU_WORK_BUF_CHROMA2,
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VENC_VP8_VPU_WORK_BUF_CHROMA3,
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VENC_VP8_VPU_WORK_BUF_MV_INFO,
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VENC_VP8_VPU_WORK_BUF_BS_HEADER,
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VENC_VP8_VPU_WORK_BUF_PROB_BUF,
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VENC_VP8_VPU_WORK_BUF_RC_INFO,
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VENC_VP8_VPU_WORK_BUF_RC_CODE,
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VENC_VP8_VPU_WORK_BUF_RC_CODE2,
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VENC_VP8_VPU_WORK_BUF_RC_CODE3,
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VENC_VP8_VPU_WORK_BUF_MAX,
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};
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/*
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* struct venc_vp8_vpu_config - Structure for vp8 encoder configuration
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* AP-W/R : AP is writer/reader on this item
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* VPU-W/R: VPU is write/reader on this item
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* @input_fourcc: input fourcc
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* @bitrate: target bitrate (in bps)
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* @pic_w: picture width. Picture size is visible stream resolution, in pixels,
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* to be used for display purposes; must be smaller or equal to buffer
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* size.
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* @pic_h: picture height
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* @buf_w: buffer width (with 16 alignment). Buffer size is stream resolution
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* in pixels aligned to hardware requirements.
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* @buf_h: buffer height (with 16 alignment)
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* @gop_size: group of picture size (key frame)
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* @framerate: frame rate in fps
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* @ts_mode: temporal scalability mode (0: disable, 1: enable)
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* support three temporal layers - 0: 7.5fps 1: 7.5fps 2: 15fps.
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*/
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struct venc_vp8_vpu_config {
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u32 input_fourcc;
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u32 bitrate;
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u32 pic_w;
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u32 pic_h;
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u32 buf_w;
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u32 buf_h;
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u32 gop_size;
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u32 framerate;
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u32 ts_mode;
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};
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/*
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* struct venc_vp8_vpu_buf - Structure for buffer information
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* AP-W/R : AP is writer/reader on this item
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* VPU-W/R: VPU is write/reader on this item
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* @iova: IO virtual address
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* @vpua: VPU side memory addr which is used by RC_CODE
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* @size: buffer size (in bytes)
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*/
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struct venc_vp8_vpu_buf {
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u32 iova;
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u32 vpua;
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u32 size;
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};
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/*
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* struct venc_vp8_vsi - Structure for VPU driver control and info share
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* AP-W/R : AP is writer/reader on this item
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* VPU-W/R: VPU is write/reader on this item
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* This structure is allocated in VPU side and shared to AP side.
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* @config: vp8 encoder configuration
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* @work_bufs: working buffer information in VPU side
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* The work_bufs here is for storing the 'size' info shared to AP side.
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* The similar item in struct venc_vp8_inst is for memory allocation
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* in AP side. The AP driver will copy the 'size' from here to the one in
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* struct mtk_vcodec_mem, then invoke mtk_vcodec_mem_alloc to allocate
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* the buffer. After that, bypass the 'dma_addr' to the 'iova' field here for
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* register setting in VPU side.
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*/
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struct venc_vp8_vsi {
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struct venc_vp8_vpu_config config;
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struct venc_vp8_vpu_buf work_bufs[VENC_VP8_VPU_WORK_BUF_MAX];
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};
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/*
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* struct venc_vp8_inst - vp8 encoder AP driver instance
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* @hw_base: vp8 encoder hardware register base
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* @work_bufs: working buffer
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* @work_buf_allocated: working buffer allocated flag
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* @frm_cnt: encoded frame count, it's used for I-frame judgement and
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* reset when force intra cmd received.
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* @ts_mode: temporal scalability mode (0: disable, 1: enable)
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* support three temporal layers - 0: 7.5fps 1: 7.5fps 2: 15fps.
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* @vpu_inst: VPU instance to exchange information between AP and VPU
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* @vsi: driver structure allocated by VPU side and shared to AP side for
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* control and info share
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* @ctx: context for v4l2 layer integration
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*/
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struct venc_vp8_inst {
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void __iomem *hw_base;
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struct mtk_vcodec_mem work_bufs[VENC_VP8_VPU_WORK_BUF_MAX];
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bool work_buf_allocated;
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unsigned int frm_cnt;
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unsigned int ts_mode;
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struct venc_vpu_inst vpu_inst;
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struct venc_vp8_vsi *vsi;
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struct mtk_vcodec_ctx *ctx;
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};
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static inline u32 vp8_enc_read_reg(struct venc_vp8_inst *inst, u32 addr)
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{
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return readl(inst->hw_base + addr);
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}
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static void vp8_enc_free_work_buf(struct venc_vp8_inst *inst)
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{
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int i;
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mtk_vcodec_debug_enter(inst);
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/* Buffers need to be freed by AP. */
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for (i = 0; i < VENC_VP8_VPU_WORK_BUF_MAX; i++) {
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if (inst->work_bufs[i].size == 0)
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continue;
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mtk_vcodec_mem_free(inst->ctx, &inst->work_bufs[i]);
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}
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mtk_vcodec_debug_leave(inst);
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}
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static int vp8_enc_alloc_work_buf(struct venc_vp8_inst *inst)
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{
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int i;
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int ret = 0;
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struct venc_vp8_vpu_buf *wb = inst->vsi->work_bufs;
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mtk_vcodec_debug_enter(inst);
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for (i = 0; i < VENC_VP8_VPU_WORK_BUF_MAX; i++) {
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if (wb[i].size == 0)
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continue;
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/*
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* This 'wb' structure is set by VPU side and shared to AP for
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* buffer allocation and IO virtual addr mapping. For most of
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* the buffers, AP will allocate the buffer according to 'size'
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* field and store the IO virtual addr in 'iova' field. For the
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* RC_CODEx buffers, they are pre-allocated in the VPU side
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* because they are inside VPU SRAM, and save the VPU addr in
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* the 'vpua' field. The AP will translate the VPU addr to the
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* corresponding IO virtual addr and store in 'iova' field.
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*/
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inst->work_bufs[i].size = wb[i].size;
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ret = mtk_vcodec_mem_alloc(inst->ctx, &inst->work_bufs[i]);
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if (ret) {
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mtk_vcodec_err(inst,
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"cannot alloc work_bufs[%d]", i);
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goto err_alloc;
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}
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/*
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* This RC_CODEx is pre-allocated by VPU and saved in VPU addr.
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* So we need use memcpy to copy RC_CODEx from VPU addr into IO
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* virtual addr in 'iova' field for reg setting in VPU side.
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*/
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if (i == VENC_VP8_VPU_WORK_BUF_RC_CODE ||
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i == VENC_VP8_VPU_WORK_BUF_RC_CODE2 ||
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i == VENC_VP8_VPU_WORK_BUF_RC_CODE3) {
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struct mtk_vcodec_fw *handler;
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void *tmp_va;
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handler = inst->vpu_inst.ctx->dev->fw_handler;
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tmp_va = mtk_vcodec_fw_map_dm_addr(handler,
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wb[i].vpua);
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memcpy(inst->work_bufs[i].va, tmp_va, wb[i].size);
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}
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wb[i].iova = inst->work_bufs[i].dma_addr;
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mtk_vcodec_debug(inst,
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"work_bufs[%d] va=0x%p,iova=%pad,size=%zu",
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i, inst->work_bufs[i].va,
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&inst->work_bufs[i].dma_addr,
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inst->work_bufs[i].size);
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}
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mtk_vcodec_debug_leave(inst);
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return ret;
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err_alloc:
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vp8_enc_free_work_buf(inst);
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return ret;
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}
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static unsigned int vp8_enc_wait_venc_done(struct venc_vp8_inst *inst)
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{
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unsigned int irq_status = 0;
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struct mtk_vcodec_ctx *ctx = (struct mtk_vcodec_ctx *)inst->ctx;
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if (!mtk_vcodec_wait_for_done_ctx(ctx, MTK_INST_IRQ_RECEIVED,
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WAIT_INTR_TIMEOUT_MS)) {
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irq_status = ctx->irq_status;
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mtk_vcodec_debug(inst, "isr return %x", irq_status);
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}
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return irq_status;
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}
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/*
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* Compose ac_tag, bitstream header and bitstream payload into
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* one bitstream buffer.
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*/
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static int vp8_enc_compose_one_frame(struct venc_vp8_inst *inst,
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struct mtk_vcodec_mem *bs_buf,
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unsigned int *bs_size)
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{
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unsigned int not_key;
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u32 bs_frm_size;
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u32 bs_hdr_len;
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unsigned int ac_tag_size;
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u8 ac_tag[MAX_AC_TAG_SIZE];
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u32 tag;
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bs_frm_size = vp8_enc_read_reg(inst, VENC_BITSTREAM_FRAME_SIZE);
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bs_hdr_len = vp8_enc_read_reg(inst, VENC_BITSTREAM_HEADER_LEN);
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/* if a frame is key frame, not_key is 0 */
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not_key = !inst->vpu_inst.is_key_frm;
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tag = (bs_hdr_len << 5) | 0x10 | not_key;
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ac_tag[0] = tag & 0xff;
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ac_tag[1] = (tag >> 8) & 0xff;
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ac_tag[2] = (tag >> 16) & 0xff;
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/* key frame */
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if (not_key == 0) {
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ac_tag_size = MAX_AC_TAG_SIZE;
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ac_tag[3] = 0x9d;
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ac_tag[4] = 0x01;
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ac_tag[5] = 0x2a;
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ac_tag[6] = inst->vsi->config.pic_w;
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ac_tag[7] = inst->vsi->config.pic_w >> 8;
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ac_tag[8] = inst->vsi->config.pic_h;
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ac_tag[9] = inst->vsi->config.pic_h >> 8;
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} else {
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ac_tag_size = 3;
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}
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if (bs_buf->size < bs_hdr_len + bs_frm_size + ac_tag_size) {
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mtk_vcodec_err(inst, "bitstream buf size is too small(%zu)",
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bs_buf->size);
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return -EINVAL;
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}
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/*
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* (1) The vp8 bitstream header and body are generated by the HW vp8
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* encoder separately at the same time. We cannot know the bitstream
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* header length in advance.
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* (2) From the vp8 spec, there is no stuffing byte allowed between the
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* ac tag, bitstream header and bitstream body.
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*/
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memmove(bs_buf->va + bs_hdr_len + ac_tag_size,
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bs_buf->va, bs_frm_size);
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memcpy(bs_buf->va + ac_tag_size,
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inst->work_bufs[VENC_VP8_VPU_WORK_BUF_BS_HEADER].va,
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bs_hdr_len);
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memcpy(bs_buf->va, ac_tag, ac_tag_size);
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*bs_size = bs_frm_size + bs_hdr_len + ac_tag_size;
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return 0;
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}
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static int vp8_enc_encode_frame(struct venc_vp8_inst *inst,
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struct venc_frm_buf *frm_buf,
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struct mtk_vcodec_mem *bs_buf,
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unsigned int *bs_size)
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{
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int ret = 0;
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unsigned int irq_status;
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mtk_vcodec_debug(inst, "->frm_cnt=%d", inst->frm_cnt);
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ret = vpu_enc_encode(&inst->vpu_inst, 0, frm_buf, bs_buf, bs_size,
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NULL);
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if (ret)
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return ret;
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irq_status = vp8_enc_wait_venc_done(inst);
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if (irq_status != MTK_VENC_IRQ_STATUS_FRM) {
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mtk_vcodec_err(inst, "irq_status=%d failed", irq_status);
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return -EIO;
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}
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if (vp8_enc_compose_one_frame(inst, bs_buf, bs_size)) {
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mtk_vcodec_err(inst, "vp8_enc_compose_one_frame failed");
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return -EINVAL;
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}
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inst->frm_cnt++;
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mtk_vcodec_debug(inst, "<-size=%d key_frm=%d", *bs_size,
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inst->vpu_inst.is_key_frm);
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return ret;
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}
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static int vp8_enc_init(struct mtk_vcodec_ctx *ctx)
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{
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int ret = 0;
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struct venc_vp8_inst *inst;
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inst = kzalloc(sizeof(*inst), GFP_KERNEL);
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if (!inst)
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return -ENOMEM;
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inst->ctx = ctx;
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inst->vpu_inst.ctx = ctx;
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inst->vpu_inst.id = IPI_VENC_VP8;
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inst->hw_base = mtk_vcodec_get_reg_addr(inst->ctx, VENC_LT_SYS);
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mtk_vcodec_debug_enter(inst);
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ret = vpu_enc_init(&inst->vpu_inst);
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inst->vsi = (struct venc_vp8_vsi *)inst->vpu_inst.vsi;
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mtk_vcodec_debug_leave(inst);
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if (ret)
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kfree(inst);
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else
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ctx->drv_handle = inst;
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return ret;
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}
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static int vp8_enc_encode(void *handle,
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enum venc_start_opt opt,
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struct venc_frm_buf *frm_buf,
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struct mtk_vcodec_mem *bs_buf,
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struct venc_done_result *result)
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{
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int ret = 0;
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struct venc_vp8_inst *inst = (struct venc_vp8_inst *)handle;
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struct mtk_vcodec_ctx *ctx = inst->ctx;
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mtk_vcodec_debug_enter(inst);
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enable_irq(ctx->dev->enc_lt_irq);
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switch (opt) {
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case VENC_START_OPT_ENCODE_FRAME:
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ret = vp8_enc_encode_frame(inst, frm_buf, bs_buf,
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&result->bs_size);
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if (ret)
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goto encode_err;
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result->is_key_frm = inst->vpu_inst.is_key_frm;
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break;
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default:
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mtk_vcodec_err(inst, "opt not support:%d", opt);
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ret = -EINVAL;
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break;
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}
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encode_err:
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disable_irq(ctx->dev->enc_lt_irq);
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mtk_vcodec_debug_leave(inst);
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return ret;
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}
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static int vp8_enc_set_param(void *handle,
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enum venc_set_param_type type,
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struct venc_enc_param *enc_prm)
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{
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int ret = 0;
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struct venc_vp8_inst *inst = (struct venc_vp8_inst *)handle;
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mtk_vcodec_debug(inst, "->type=%d", type);
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switch (type) {
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case VENC_SET_PARAM_ENC:
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inst->vsi->config.input_fourcc = enc_prm->input_yuv_fmt;
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inst->vsi->config.bitrate = enc_prm->bitrate;
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inst->vsi->config.pic_w = enc_prm->width;
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inst->vsi->config.pic_h = enc_prm->height;
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inst->vsi->config.buf_w = enc_prm->buf_width;
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inst->vsi->config.buf_h = enc_prm->buf_height;
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inst->vsi->config.gop_size = enc_prm->gop_size;
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inst->vsi->config.framerate = enc_prm->frm_rate;
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inst->vsi->config.ts_mode = inst->ts_mode;
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ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
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if (ret)
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break;
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if (inst->work_buf_allocated) {
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vp8_enc_free_work_buf(inst);
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inst->work_buf_allocated = false;
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}
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ret = vp8_enc_alloc_work_buf(inst);
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if (ret)
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break;
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inst->work_buf_allocated = true;
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break;
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/*
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* VENC_SET_PARAM_TS_MODE must be called before VENC_SET_PARAM_ENC
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*/
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case VENC_SET_PARAM_TS_MODE:
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inst->ts_mode = 1;
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mtk_vcodec_debug(inst, "set ts_mode");
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break;
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default:
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ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
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break;
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}
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mtk_vcodec_debug_leave(inst);
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return ret;
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}
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static int vp8_enc_deinit(void *handle)
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{
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int ret = 0;
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struct venc_vp8_inst *inst = (struct venc_vp8_inst *)handle;
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mtk_vcodec_debug_enter(inst);
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ret = vpu_enc_deinit(&inst->vpu_inst);
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if (inst->work_buf_allocated)
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vp8_enc_free_work_buf(inst);
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mtk_vcodec_debug_leave(inst);
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kfree(inst);
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return ret;
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}
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const struct venc_common_if venc_vp8_if = {
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.init = vp8_enc_init,
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.encode = vp8_enc_encode,
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.set_param = vp8_enc_set_param,
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.deinit = vp8_enc_deinit,
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};
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