/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
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* Rick Chang <rick.chang@mediatek.com>
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*/
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#ifndef _MTK_JPEG_REG_H
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#define _MTK_JPEG_REG_H
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#define MTK_JPEG_BLOCK_MAX 10
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#define MTK_JPEG_DCTSIZE 8
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#define BIT_INQST_MASK_ERROR_BS 0x20
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#define BIT_INQST_MASK_PAUSE 0x10
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#define BIT_INQST_MASK_OVERFLOW 0x04
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#define BIT_INQST_MASK_UNDERFLOW 0x02
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#define BIT_INQST_MASK_EOF 0x01
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#define BIT_INQST_MASK_ALLIRQ 0x37
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#define JPGDEC_REG_RESET 0x0090
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#define JPGDEC_REG_BRZ_FACTOR 0x00f8
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#define JPGDEC_REG_DU_NUM 0x00fc
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#define JPGDEC_REG_DEST_ADDR0_Y 0x0140
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#define JPGDEC_REG_DEST_ADDR0_U 0x0144
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#define JPGDEC_REG_DEST_ADDR0_V 0x0148
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#define JPGDEC_REG_DEST_ADDR1_Y 0x014c
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#define JPGDEC_REG_DEST_ADDR1_U 0x0150
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#define JPGDEC_REG_DEST_ADDR1_V 0x0154
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#define JPGDEC_REG_STRIDE_Y 0x0158
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#define JPGDEC_REG_STRIDE_UV 0x015c
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#define JPGDEC_REG_IMG_STRIDE_Y 0x0160
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#define JPGDEC_REG_IMG_STRIDE_UV 0x0164
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#define JPGDEC_REG_WDMA_CTRL 0x016c
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#define JPGDEC_REG_PAUSE_MCU_NUM 0x0170
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#define JPGDEC_REG_OPERATION_MODE 0x017c
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#define JPGDEC_REG_FILE_ADDR 0x0200
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#define JPGDEC_REG_COMP_ID 0x020c
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#define JPGDEC_REG_TOTAL_MCU_NUM 0x0210
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#define JPGDEC_REG_COMP0_DATA_UNIT_NUM 0x0224
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#define JPGDEC_REG_DU_CTRL 0x023c
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#define JPGDEC_REG_TRIG 0x0240
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#define JPGDEC_REG_FILE_BRP 0x0248
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#define JPGDEC_REG_FILE_TOTAL_SIZE 0x024c
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#define JPGDEC_REG_QT_ID 0x0270
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#define JPGDEC_REG_INTERRUPT_STATUS 0x0274
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#define JPGDEC_REG_STATUS 0x0278
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#endif /* _MTK_JPEG_REG_H */
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