// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Register interface file for Samsung Camera Interface (FIMC) driver
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*
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* Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
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* Sylwester Nawrocki <s.nawrocki@samsung.com>
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/regmap.h>
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#include <media/drv-intf/exynos-fimc.h>
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#include "media-dev.h"
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#include "fimc-reg.h"
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#include "fimc-core.h"
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void fimc_hw_reset(struct fimc_dev *dev)
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{
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u32 cfg;
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cfg = readl(dev->regs + FIMC_REG_CISRCFMT);
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cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
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writel(cfg, dev->regs + FIMC_REG_CISRCFMT);
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/* Software reset. */
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cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
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cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL);
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writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
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udelay(10);
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cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
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cfg &= ~FIMC_REG_CIGCTRL_SWRST;
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writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
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if (dev->drv_data->out_buf_count > 4)
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fimc_hw_set_dma_seq(dev, 0xF);
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}
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static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx)
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{
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u32 flip = FIMC_REG_MSCTRL_FLIP_NORMAL;
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if (ctx->hflip)
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flip = FIMC_REG_MSCTRL_FLIP_Y_MIRROR;
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if (ctx->vflip)
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flip = FIMC_REG_MSCTRL_FLIP_X_MIRROR;
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if (ctx->rotation <= 90)
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return flip;
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return (flip ^ FIMC_REG_MSCTRL_FLIP_180) & FIMC_REG_MSCTRL_FLIP_180;
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}
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static u32 fimc_hw_get_target_flip(struct fimc_ctx *ctx)
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{
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u32 flip = FIMC_REG_CITRGFMT_FLIP_NORMAL;
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if (ctx->hflip)
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flip |= FIMC_REG_CITRGFMT_FLIP_Y_MIRROR;
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if (ctx->vflip)
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flip |= FIMC_REG_CITRGFMT_FLIP_X_MIRROR;
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if (ctx->rotation <= 90)
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return flip;
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return (flip ^ FIMC_REG_CITRGFMT_FLIP_180) & FIMC_REG_CITRGFMT_FLIP_180;
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}
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void fimc_hw_set_rotation(struct fimc_ctx *ctx)
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{
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u32 cfg, flip;
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struct fimc_dev *dev = ctx->fimc_dev;
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cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
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cfg &= ~(FIMC_REG_CITRGFMT_INROT90 | FIMC_REG_CITRGFMT_OUTROT90 |
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FIMC_REG_CITRGFMT_FLIP_180);
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/*
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* The input and output rotator cannot work simultaneously.
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* Use the output rotator in output DMA mode or the input rotator
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* in direct fifo output mode.
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*/
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if (ctx->rotation == 90 || ctx->rotation == 270) {
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if (ctx->out_path == FIMC_IO_LCDFIFO)
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cfg |= FIMC_REG_CITRGFMT_INROT90;
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else
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cfg |= FIMC_REG_CITRGFMT_OUTROT90;
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}
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if (ctx->out_path == FIMC_IO_DMA) {
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cfg |= fimc_hw_get_target_flip(ctx);
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writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
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} else {
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/* LCD FIFO path */
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flip = readl(dev->regs + FIMC_REG_MSCTRL);
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flip &= ~FIMC_REG_MSCTRL_FLIP_MASK;
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flip |= fimc_hw_get_in_flip(ctx);
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writel(flip, dev->regs + FIMC_REG_MSCTRL);
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}
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}
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void fimc_hw_set_target_format(struct fimc_ctx *ctx)
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{
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u32 cfg;
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_frame *frame = &ctx->d_frame;
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dbg("w= %d, h= %d color: %d", frame->width,
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frame->height, frame->fmt->color);
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cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
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cfg &= ~(FIMC_REG_CITRGFMT_FMT_MASK | FIMC_REG_CITRGFMT_HSIZE_MASK |
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FIMC_REG_CITRGFMT_VSIZE_MASK);
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switch (frame->fmt->color) {
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case FIMC_FMT_RGB444...FIMC_FMT_RGB888:
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cfg |= FIMC_REG_CITRGFMT_RGB;
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break;
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case FIMC_FMT_YCBCR420:
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cfg |= FIMC_REG_CITRGFMT_YCBCR420;
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break;
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case FIMC_FMT_YCBYCR422...FIMC_FMT_CRYCBY422:
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if (frame->fmt->colplanes == 1)
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cfg |= FIMC_REG_CITRGFMT_YCBCR422_1P;
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else
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cfg |= FIMC_REG_CITRGFMT_YCBCR422;
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break;
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default:
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break;
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}
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if (ctx->rotation == 90 || ctx->rotation == 270)
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cfg |= (frame->height << 16) | frame->width;
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else
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cfg |= (frame->width << 16) | frame->height;
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writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
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cfg = readl(dev->regs + FIMC_REG_CITAREA);
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cfg &= ~FIMC_REG_CITAREA_MASK;
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cfg |= (frame->width * frame->height);
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writel(cfg, dev->regs + FIMC_REG_CITAREA);
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}
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static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_frame *frame = &ctx->d_frame;
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u32 cfg;
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cfg = (frame->f_height << 16) | frame->f_width;
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writel(cfg, dev->regs + FIMC_REG_ORGOSIZE);
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/* Select color space conversion equation (HD/SD size).*/
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cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
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if (frame->f_width >= 1280) /* HD */
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cfg |= FIMC_REG_CIGCTRL_CSC_ITU601_709;
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else /* SD */
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cfg &= ~FIMC_REG_CIGCTRL_CSC_ITU601_709;
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writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
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}
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void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_frame *frame = &ctx->d_frame;
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struct fimc_dma_offset *offset = &frame->dma_offset;
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struct fimc_fmt *fmt = frame->fmt;
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u32 cfg;
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/* Set the input dma offsets. */
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cfg = (offset->y_v << 16) | offset->y_h;
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writel(cfg, dev->regs + FIMC_REG_CIOYOFF);
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cfg = (offset->cb_v << 16) | offset->cb_h;
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writel(cfg, dev->regs + FIMC_REG_CIOCBOFF);
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cfg = (offset->cr_v << 16) | offset->cr_h;
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writel(cfg, dev->regs + FIMC_REG_CIOCROFF);
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fimc_hw_set_out_dma_size(ctx);
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/* Configure chroma components order. */
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cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
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cfg &= ~(FIMC_REG_CIOCTRL_ORDER2P_MASK |
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FIMC_REG_CIOCTRL_ORDER422_MASK |
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FIMC_REG_CIOCTRL_YCBCR_PLANE_MASK |
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FIMC_REG_CIOCTRL_RGB16FMT_MASK);
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if (fmt->colplanes == 1)
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cfg |= ctx->out_order_1p;
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else if (fmt->colplanes == 2)
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cfg |= ctx->out_order_2p | FIMC_REG_CIOCTRL_YCBCR_2PLANE;
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else if (fmt->colplanes == 3)
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cfg |= FIMC_REG_CIOCTRL_YCBCR_3PLANE;
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if (fmt->color == FIMC_FMT_RGB565)
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cfg |= FIMC_REG_CIOCTRL_RGB565;
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else if (fmt->color == FIMC_FMT_RGB555)
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cfg |= FIMC_REG_CIOCTRL_ARGB1555;
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else if (fmt->color == FIMC_FMT_RGB444)
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cfg |= FIMC_REG_CIOCTRL_ARGB4444;
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writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
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}
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static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
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{
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u32 cfg = readl(dev->regs + FIMC_REG_ORGISIZE);
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if (enable)
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cfg |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
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else
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cfg &= ~FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
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writel(cfg, dev->regs + FIMC_REG_ORGISIZE);
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}
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void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
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{
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u32 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
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if (enable)
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cfg |= FIMC_REG_CIOCTRL_LASTIRQ_ENABLE;
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else
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cfg &= ~FIMC_REG_CIOCTRL_LASTIRQ_ENABLE;
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writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
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}
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void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_scaler *sc = &ctx->scaler;
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u32 cfg, shfactor;
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shfactor = 10 - (sc->hfactor + sc->vfactor);
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cfg = shfactor << 28;
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cfg |= (sc->pre_hratio << 16) | sc->pre_vratio;
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writel(cfg, dev->regs + FIMC_REG_CISCPRERATIO);
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cfg = (sc->pre_dst_width << 16) | sc->pre_dst_height;
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writel(cfg, dev->regs + FIMC_REG_CISCPREDST);
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}
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static void fimc_hw_set_scaler(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_scaler *sc = &ctx->scaler;
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struct fimc_frame *src_frame = &ctx->s_frame;
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struct fimc_frame *dst_frame = &ctx->d_frame;
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u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
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cfg &= ~(FIMC_REG_CISCCTRL_CSCR2Y_WIDE | FIMC_REG_CISCCTRL_CSCY2R_WIDE |
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FIMC_REG_CISCCTRL_SCALEUP_H | FIMC_REG_CISCCTRL_SCALEUP_V |
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FIMC_REG_CISCCTRL_SCALERBYPASS | FIMC_REG_CISCCTRL_ONE2ONE |
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FIMC_REG_CISCCTRL_INRGB_FMT_MASK | FIMC_REG_CISCCTRL_OUTRGB_FMT_MASK |
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FIMC_REG_CISCCTRL_INTERLACE | FIMC_REG_CISCCTRL_RGB_EXT);
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if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
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cfg |= (FIMC_REG_CISCCTRL_CSCR2Y_WIDE |
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FIMC_REG_CISCCTRL_CSCY2R_WIDE);
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if (!sc->enabled)
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cfg |= FIMC_REG_CISCCTRL_SCALERBYPASS;
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if (sc->scaleup_h)
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cfg |= FIMC_REG_CISCCTRL_SCALEUP_H;
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if (sc->scaleup_v)
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cfg |= FIMC_REG_CISCCTRL_SCALEUP_V;
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if (sc->copy_mode)
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cfg |= FIMC_REG_CISCCTRL_ONE2ONE;
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if (ctx->in_path == FIMC_IO_DMA) {
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switch (src_frame->fmt->color) {
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case FIMC_FMT_RGB565:
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cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB565;
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break;
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case FIMC_FMT_RGB666:
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cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB666;
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break;
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case FIMC_FMT_RGB888:
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cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB888;
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break;
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}
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}
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if (ctx->out_path == FIMC_IO_DMA) {
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u32 color = dst_frame->fmt->color;
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if (color >= FIMC_FMT_RGB444 && color <= FIMC_FMT_RGB565)
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cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565;
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else if (color == FIMC_FMT_RGB666)
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cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666;
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else if (color == FIMC_FMT_RGB888)
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cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
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} else {
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cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
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if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
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cfg |= FIMC_REG_CISCCTRL_INTERLACE;
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}
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writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
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}
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void fimc_hw_set_mainscaler(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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const struct fimc_variant *variant = dev->variant;
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struct fimc_scaler *sc = &ctx->scaler;
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u32 cfg;
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dbg("main_hratio= 0x%X main_vratio= 0x%X",
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sc->main_hratio, sc->main_vratio);
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fimc_hw_set_scaler(ctx);
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cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
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cfg &= ~(FIMC_REG_CISCCTRL_MHRATIO_MASK |
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FIMC_REG_CISCCTRL_MVRATIO_MASK);
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if (variant->has_mainscaler_ext) {
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cfg |= FIMC_REG_CISCCTRL_MHRATIO_EXT(sc->main_hratio);
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cfg |= FIMC_REG_CISCCTRL_MVRATIO_EXT(sc->main_vratio);
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writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
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cfg = readl(dev->regs + FIMC_REG_CIEXTEN);
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cfg &= ~(FIMC_REG_CIEXTEN_MVRATIO_EXT_MASK |
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FIMC_REG_CIEXTEN_MHRATIO_EXT_MASK);
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cfg |= FIMC_REG_CIEXTEN_MHRATIO_EXT(sc->main_hratio);
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cfg |= FIMC_REG_CIEXTEN_MVRATIO_EXT(sc->main_vratio);
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writel(cfg, dev->regs + FIMC_REG_CIEXTEN);
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} else {
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cfg |= FIMC_REG_CISCCTRL_MHRATIO(sc->main_hratio);
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cfg |= FIMC_REG_CISCCTRL_MVRATIO(sc->main_vratio);
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writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
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}
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}
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void fimc_hw_enable_capture(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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u32 cfg;
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cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);
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cfg |= FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE;
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if (ctx->scaler.enabled)
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cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN_SC;
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else
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cfg &= FIMC_REG_CIIMGCPT_IMGCPTEN_SC;
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cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN;
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writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
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}
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void fimc_hw_disable_capture(struct fimc_dev *dev)
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{
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u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);
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cfg &= ~(FIMC_REG_CIIMGCPT_IMGCPTEN |
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FIMC_REG_CIIMGCPT_IMGCPTEN_SC);
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writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
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}
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void fimc_hw_set_effect(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_effect *effect = &ctx->effect;
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u32 cfg = 0;
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if (effect->type != FIMC_REG_CIIMGEFF_FIN_BYPASS) {
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cfg |= FIMC_REG_CIIMGEFF_IE_SC_AFTER |
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FIMC_REG_CIIMGEFF_IE_ENABLE;
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cfg |= effect->type;
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if (effect->type == FIMC_REG_CIIMGEFF_FIN_ARBITRARY)
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cfg |= (effect->pat_cb << 13) | effect->pat_cr;
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}
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writel(cfg, dev->regs + FIMC_REG_CIIMGEFF);
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}
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void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_frame *frame = &ctx->d_frame;
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u32 cfg;
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if (!(frame->fmt->flags & FMT_HAS_ALPHA))
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return;
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cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
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cfg &= ~FIMC_REG_CIOCTRL_ALPHA_OUT_MASK;
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cfg |= (frame->alpha << 4);
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writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
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}
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static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_frame *frame = &ctx->s_frame;
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u32 cfg_o = 0;
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u32 cfg_r = 0;
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if (FIMC_IO_LCDFIFO == ctx->out_path)
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cfg_r |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
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cfg_o |= (frame->f_height << 16) | frame->f_width;
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cfg_r |= (frame->height << 16) | frame->width;
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writel(cfg_o, dev->regs + FIMC_REG_ORGISIZE);
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writel(cfg_r, dev->regs + FIMC_REG_CIREAL_ISIZE);
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}
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void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
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struct fimc_frame *frame = &ctx->s_frame;
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struct fimc_dma_offset *offset = &frame->dma_offset;
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u32 cfg;
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/* Set the pixel offsets. */
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cfg = (offset->y_v << 16) | offset->y_h;
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writel(cfg, dev->regs + FIMC_REG_CIIYOFF);
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cfg = (offset->cb_v << 16) | offset->cb_h;
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writel(cfg, dev->regs + FIMC_REG_CIICBOFF);
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cfg = (offset->cr_v << 16) | offset->cr_h;
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writel(cfg, dev->regs + FIMC_REG_CIICROFF);
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/* Input original and real size. */
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fimc_hw_set_in_dma_size(ctx);
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/* Use DMA autoload only in FIFO mode. */
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fimc_hw_en_autoload(dev, ctx->out_path == FIMC_IO_LCDFIFO);
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/* Set the input DMA to process single frame only. */
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cfg = readl(dev->regs + FIMC_REG_MSCTRL);
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cfg &= ~(FIMC_REG_MSCTRL_INFORMAT_MASK
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| FIMC_REG_MSCTRL_IN_BURST_COUNT_MASK
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| FIMC_REG_MSCTRL_INPUT_MASK
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| FIMC_REG_MSCTRL_C_INT_IN_MASK
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| FIMC_REG_MSCTRL_2P_IN_ORDER_MASK
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| FIMC_REG_MSCTRL_ORDER422_MASK);
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cfg |= (FIMC_REG_MSCTRL_IN_BURST_COUNT(4)
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| FIMC_REG_MSCTRL_INPUT_MEMORY
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| FIMC_REG_MSCTRL_FIFO_CTRL_FULL);
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switch (frame->fmt->color) {
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case FIMC_FMT_RGB565...FIMC_FMT_RGB888:
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cfg |= FIMC_REG_MSCTRL_INFORMAT_RGB;
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break;
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case FIMC_FMT_YCBCR420:
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cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR420;
|
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if (frame->fmt->colplanes == 2)
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cfg |= ctx->in_order_2p | FIMC_REG_MSCTRL_C_INT_IN_2PLANE;
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else
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cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE;
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break;
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case FIMC_FMT_YCBYCR422...FIMC_FMT_CRYCBY422:
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if (frame->fmt->colplanes == 1) {
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cfg |= ctx->in_order_1p
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| FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P;
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} else {
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cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR422;
|
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if (frame->fmt->colplanes == 2)
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cfg |= ctx->in_order_2p
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| FIMC_REG_MSCTRL_C_INT_IN_2PLANE;
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else
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cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE;
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}
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break;
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default:
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break;
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}
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writel(cfg, dev->regs + FIMC_REG_MSCTRL);
|
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/* Input/output DMA linear/tiled mode. */
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cfg = readl(dev->regs + FIMC_REG_CIDMAPARAM);
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cfg &= ~FIMC_REG_CIDMAPARAM_TILE_MASK;
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if (tiled_fmt(ctx->s_frame.fmt))
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cfg |= FIMC_REG_CIDMAPARAM_R_64X32;
|
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if (tiled_fmt(ctx->d_frame.fmt))
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cfg |= FIMC_REG_CIDMAPARAM_W_64X32;
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writel(cfg, dev->regs + FIMC_REG_CIDMAPARAM);
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}
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|
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void fimc_hw_set_input_path(struct fimc_ctx *ctx)
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{
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struct fimc_dev *dev = ctx->fimc_dev;
|
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u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
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cfg &= ~FIMC_REG_MSCTRL_INPUT_MASK;
|
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if (ctx->in_path == FIMC_IO_DMA)
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cfg |= FIMC_REG_MSCTRL_INPUT_MEMORY;
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else
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cfg |= FIMC_REG_MSCTRL_INPUT_EXTCAM;
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writel(cfg, dev->regs + FIMC_REG_MSCTRL);
|
}
|
|
void fimc_hw_set_output_path(struct fimc_ctx *ctx)
|
{
|
struct fimc_dev *dev = ctx->fimc_dev;
|
|
u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
|
cfg &= ~FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
|
if (ctx->out_path == FIMC_IO_LCDFIFO)
|
cfg |= FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
|
writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
|
}
|
|
void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
|
{
|
u32 cfg = readl(dev->regs + FIMC_REG_CIREAL_ISIZE);
|
cfg |= FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
|
writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
|
|
writel(paddr->y, dev->regs + FIMC_REG_CIIYSA(0));
|
writel(paddr->cb, dev->regs + FIMC_REG_CIICBSA(0));
|
writel(paddr->cr, dev->regs + FIMC_REG_CIICRSA(0));
|
|
cfg &= ~FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
|
writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
|
}
|
|
void fimc_hw_set_output_addr(struct fimc_dev *dev,
|
struct fimc_addr *paddr, int index)
|
{
|
int i = (index == -1) ? 0 : index;
|
do {
|
writel(paddr->y, dev->regs + FIMC_REG_CIOYSA(i));
|
writel(paddr->cb, dev->regs + FIMC_REG_CIOCBSA(i));
|
writel(paddr->cr, dev->regs + FIMC_REG_CIOCRSA(i));
|
dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
|
i, paddr->y, paddr->cb, paddr->cr);
|
} while (index == -1 && ++i < FIMC_MAX_OUT_BUFS);
|
}
|
|
int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
|
struct fimc_source_info *cam)
|
{
|
u32 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);
|
|
cfg &= ~(FIMC_REG_CIGCTRL_INVPOLPCLK | FIMC_REG_CIGCTRL_INVPOLVSYNC |
|
FIMC_REG_CIGCTRL_INVPOLHREF | FIMC_REG_CIGCTRL_INVPOLHSYNC |
|
FIMC_REG_CIGCTRL_INVPOLFIELD);
|
|
if (cam->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
|
cfg |= FIMC_REG_CIGCTRL_INVPOLPCLK;
|
|
if (cam->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
|
cfg |= FIMC_REG_CIGCTRL_INVPOLVSYNC;
|
|
if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
|
cfg |= FIMC_REG_CIGCTRL_INVPOLHREF;
|
|
if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
|
cfg |= FIMC_REG_CIGCTRL_INVPOLHSYNC;
|
|
if (cam->flags & V4L2_MBUS_FIELD_EVEN_LOW)
|
cfg |= FIMC_REG_CIGCTRL_INVPOLFIELD;
|
|
writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
|
|
return 0;
|
}
|
|
struct mbus_pixfmt_desc {
|
u32 pixelcode;
|
u32 cisrcfmt;
|
u16 bus_width;
|
};
|
|
static const struct mbus_pixfmt_desc pix_desc[] = {
|
{ MEDIA_BUS_FMT_YUYV8_2X8, FIMC_REG_CISRCFMT_ORDER422_YCBYCR, 8 },
|
{ MEDIA_BUS_FMT_YVYU8_2X8, FIMC_REG_CISRCFMT_ORDER422_YCRYCB, 8 },
|
{ MEDIA_BUS_FMT_VYUY8_2X8, FIMC_REG_CISRCFMT_ORDER422_CRYCBY, 8 },
|
{ MEDIA_BUS_FMT_UYVY8_2X8, FIMC_REG_CISRCFMT_ORDER422_CBYCRY, 8 },
|
};
|
|
int fimc_hw_set_camera_source(struct fimc_dev *fimc,
|
struct fimc_source_info *source)
|
{
|
struct fimc_vid_cap *vc = &fimc->vid_cap;
|
struct fimc_frame *f = &vc->ctx->s_frame;
|
u32 bus_width, cfg = 0;
|
int i;
|
|
switch (source->fimc_bus_type) {
|
case FIMC_BUS_TYPE_ITU_601:
|
case FIMC_BUS_TYPE_ITU_656:
|
if (fimc_fmt_is_user_defined(f->fmt->color)) {
|
cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
|
break;
|
}
|
|
for (i = 0; i < ARRAY_SIZE(pix_desc); i++) {
|
if (vc->ci_fmt.code == pix_desc[i].pixelcode) {
|
cfg = pix_desc[i].cisrcfmt;
|
bus_width = pix_desc[i].bus_width;
|
break;
|
}
|
}
|
|
if (i == ARRAY_SIZE(pix_desc)) {
|
v4l2_err(&vc->ve.vdev,
|
"Camera color format not supported: %d\n",
|
vc->ci_fmt.code);
|
return -EINVAL;
|
}
|
|
if (source->fimc_bus_type == FIMC_BUS_TYPE_ITU_601) {
|
if (bus_width == 8)
|
cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
|
else if (bus_width == 16)
|
cfg |= FIMC_REG_CISRCFMT_ITU601_16BIT;
|
} /* else defaults to ITU-R BT.656 8-bit */
|
break;
|
case FIMC_BUS_TYPE_MIPI_CSI2:
|
if (fimc_fmt_is_user_defined(f->fmt->color))
|
cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
|
break;
|
default:
|
case FIMC_BUS_TYPE_ISP_WRITEBACK:
|
/* Anything to do here ? */
|
break;
|
}
|
|
cfg |= (f->o_width << 16) | f->o_height;
|
writel(cfg, fimc->regs + FIMC_REG_CISRCFMT);
|
return 0;
|
}
|
|
void fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f)
|
{
|
u32 hoff2, voff2;
|
|
u32 cfg = readl(fimc->regs + FIMC_REG_CIWDOFST);
|
|
cfg &= ~(FIMC_REG_CIWDOFST_HOROFF_MASK | FIMC_REG_CIWDOFST_VEROFF_MASK);
|
cfg |= FIMC_REG_CIWDOFST_OFF_EN |
|
(f->offs_h << 16) | f->offs_v;
|
|
writel(cfg, fimc->regs + FIMC_REG_CIWDOFST);
|
|
/* See CIWDOFSTn register description in the datasheet for details. */
|
hoff2 = f->o_width - f->width - f->offs_h;
|
voff2 = f->o_height - f->height - f->offs_v;
|
cfg = (hoff2 << 16) | voff2;
|
writel(cfg, fimc->regs + FIMC_REG_CIWDOFST2);
|
}
|
|
int fimc_hw_set_camera_type(struct fimc_dev *fimc,
|
struct fimc_source_info *source)
|
{
|
struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
|
u32 csis_data_alignment = 32;
|
u32 cfg, tmp;
|
|
cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);
|
|
/* Select ITU B interface, disable Writeback path and test pattern. */
|
cfg &= ~(FIMC_REG_CIGCTRL_TESTPAT_MASK | FIMC_REG_CIGCTRL_SELCAM_ITU_A |
|
FIMC_REG_CIGCTRL_SELCAM_MIPI | FIMC_REG_CIGCTRL_CAMIF_SELWB |
|
FIMC_REG_CIGCTRL_SELCAM_MIPI_A | FIMC_REG_CIGCTRL_CAM_JPEG |
|
FIMC_REG_CIGCTRL_SELWB_A);
|
|
switch (source->fimc_bus_type) {
|
case FIMC_BUS_TYPE_MIPI_CSI2:
|
cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI;
|
|
if (source->mux_id == 0)
|
cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI_A;
|
|
/* TODO: add remaining supported formats. */
|
switch (vid_cap->ci_fmt.code) {
|
case MEDIA_BUS_FMT_VYUY8_2X8:
|
tmp = FIMC_REG_CSIIMGFMT_YCBCR422_8BIT;
|
break;
|
case MEDIA_BUS_FMT_JPEG_1X8:
|
case MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8:
|
tmp = FIMC_REG_CSIIMGFMT_USER(1);
|
cfg |= FIMC_REG_CIGCTRL_CAM_JPEG;
|
break;
|
default:
|
v4l2_err(&vid_cap->ve.vdev,
|
"Not supported camera pixel format: %#x\n",
|
vid_cap->ci_fmt.code);
|
return -EINVAL;
|
}
|
tmp |= (csis_data_alignment == 32) << 8;
|
|
writel(tmp, fimc->regs + FIMC_REG_CSIIMGFMT);
|
break;
|
case FIMC_BUS_TYPE_ITU_601...FIMC_BUS_TYPE_ITU_656:
|
if (source->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */
|
cfg |= FIMC_REG_CIGCTRL_SELCAM_ITU_A;
|
if (vid_cap->ci_fmt.code == MEDIA_BUS_FMT_JPEG_1X8)
|
cfg |= FIMC_REG_CIGCTRL_CAM_JPEG;
|
break;
|
case FIMC_BUS_TYPE_LCD_WRITEBACK_A:
|
cfg |= FIMC_REG_CIGCTRL_CAMIF_SELWB;
|
fallthrough;
|
case FIMC_BUS_TYPE_ISP_WRITEBACK:
|
if (fimc->variant->has_isp_wb)
|
cfg |= FIMC_REG_CIGCTRL_CAMIF_SELWB;
|
else
|
WARN_ONCE(1, "ISP Writeback input is not supported\n");
|
break;
|
default:
|
v4l2_err(&vid_cap->ve.vdev,
|
"Invalid FIMC bus type selected: %d\n",
|
source->fimc_bus_type);
|
return -EINVAL;
|
}
|
writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
|
|
return 0;
|
}
|
|
void fimc_hw_clear_irq(struct fimc_dev *dev)
|
{
|
u32 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
|
cfg |= FIMC_REG_CIGCTRL_IRQ_CLR;
|
writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
|
}
|
|
void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
|
{
|
u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
|
if (on)
|
cfg |= FIMC_REG_CISCCTRL_SCALERSTART;
|
else
|
cfg &= ~FIMC_REG_CISCCTRL_SCALERSTART;
|
writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
|
}
|
|
void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
|
{
|
u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
|
if (on)
|
cfg |= FIMC_REG_MSCTRL_ENVID;
|
else
|
cfg &= ~FIMC_REG_MSCTRL_ENVID;
|
writel(cfg, dev->regs + FIMC_REG_MSCTRL);
|
}
|
|
/* Return an index to the buffer actually being written. */
|
s32 fimc_hw_get_frame_index(struct fimc_dev *dev)
|
{
|
s32 reg;
|
|
if (dev->drv_data->cistatus2) {
|
reg = readl(dev->regs + FIMC_REG_CISTATUS2) & 0x3f;
|
return reg - 1;
|
}
|
|
reg = readl(dev->regs + FIMC_REG_CISTATUS);
|
|
return (reg & FIMC_REG_CISTATUS_FRAMECNT_MASK) >>
|
FIMC_REG_CISTATUS_FRAMECNT_SHIFT;
|
}
|
|
/* Return an index to the buffer being written previously. */
|
s32 fimc_hw_get_prev_frame_index(struct fimc_dev *dev)
|
{
|
s32 reg;
|
|
if (!dev->drv_data->cistatus2)
|
return -1;
|
|
reg = readl(dev->regs + FIMC_REG_CISTATUS2);
|
return ((reg >> 7) & 0x3f) - 1;
|
}
|
|
/* Locking: the caller holds fimc->slock */
|
void fimc_activate_capture(struct fimc_ctx *ctx)
|
{
|
fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
|
fimc_hw_enable_capture(ctx);
|
}
|
|
void fimc_deactivate_capture(struct fimc_dev *fimc)
|
{
|
fimc_hw_en_lastirq(fimc, true);
|
fimc_hw_disable_capture(fimc);
|
fimc_hw_enable_scaler(fimc, false);
|
fimc_hw_en_lastirq(fimc, false);
|
}
|
|
int fimc_hw_camblk_cfg_writeback(struct fimc_dev *fimc)
|
{
|
struct regmap *map = fimc->sysreg;
|
unsigned int mask, val, camblk_cfg;
|
int ret;
|
|
if (map == NULL)
|
return 0;
|
|
ret = regmap_read(map, SYSREG_CAMBLK, &camblk_cfg);
|
if (ret < 0 || ((camblk_cfg & 0x00700000) >> 20 != 0x3))
|
return ret;
|
|
if (!WARN(fimc->id >= 3, "not supported id: %d\n", fimc->id))
|
val = 0x1 << (fimc->id + 20);
|
else
|
val = 0;
|
|
mask = SYSREG_CAMBLK_FIFORST_ISP | SYSREG_CAMBLK_ISPWB_FULL_EN;
|
ret = regmap_update_bits(map, SYSREG_CAMBLK, mask, val);
|
if (ret < 0)
|
return ret;
|
|
usleep_range(1000, 2000);
|
|
val |= SYSREG_CAMBLK_FIFORST_ISP;
|
ret = regmap_update_bits(map, SYSREG_CAMBLK, mask, val);
|
if (ret < 0)
|
return ret;
|
|
mask = SYSREG_ISPBLK_FIFORST_CAM_BLK;
|
ret = regmap_update_bits(map, SYSREG_ISPBLK, mask, ~mask);
|
if (ret < 0)
|
return ret;
|
|
usleep_range(1000, 2000);
|
|
return regmap_update_bits(map, SYSREG_ISPBLK, mask, mask);
|
}
|
