// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
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*
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* Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd.
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*
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* Authors: Younghwan Joo <yhwan.joo@samsung.com>
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* Sylwester Nawrocki <s.nawrocki@samsung.com>
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*/
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#include <linux/delay.h>
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#include "fimc-is.h"
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#include "fimc-is-command.h"
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#include "fimc-is-regs.h"
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#include "fimc-is-sensor.h"
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void fimc_is_fw_clear_irq1(struct fimc_is *is, unsigned int nr)
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{
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mcuctl_write(1UL << nr, is, MCUCTL_REG_INTCR1);
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}
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void fimc_is_fw_clear_irq2(struct fimc_is *is)
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{
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u32 cfg = mcuctl_read(is, MCUCTL_REG_INTSR2);
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mcuctl_write(cfg, is, MCUCTL_REG_INTCR2);
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}
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void fimc_is_hw_set_intgr0_gd0(struct fimc_is *is)
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{
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mcuctl_write(INTGR0_INTGD(0), is, MCUCTL_REG_INTGR0);
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}
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int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is)
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{
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unsigned int timeout = 2000;
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u32 cfg, status;
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do {
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cfg = mcuctl_read(is, MCUCTL_REG_INTMSR0);
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status = INTMSR0_GET_INTMSD(0, cfg);
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if (--timeout == 0) {
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dev_warn(&is->pdev->dev, "%s timeout\n",
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__func__);
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return -ETIMEDOUT;
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}
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udelay(1);
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} while (status != 0);
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return 0;
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}
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int fimc_is_hw_set_param(struct fimc_is *is)
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{
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struct chain_config *config = &is->config[is->config_index];
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unsigned int param_count = __get_pending_param_count(is);
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fimc_is_hw_wait_intmsr0_intmsd0(is);
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mcuctl_write(HIC_SET_PARAMETER, is, MCUCTL_REG_ISSR(0));
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mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
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mcuctl_write(is->config_index, is, MCUCTL_REG_ISSR(2));
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mcuctl_write(param_count, is, MCUCTL_REG_ISSR(3));
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mcuctl_write(config->p_region_index[0], is, MCUCTL_REG_ISSR(4));
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mcuctl_write(config->p_region_index[1], is, MCUCTL_REG_ISSR(5));
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fimc_is_hw_set_intgr0_gd0(is);
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return 0;
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}
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static int __maybe_unused fimc_is_hw_set_tune(struct fimc_is *is)
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{
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fimc_is_hw_wait_intmsr0_intmsd0(is);
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mcuctl_write(HIC_SET_TUNE, is, MCUCTL_REG_ISSR(0));
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mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
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mcuctl_write(is->h2i_cmd.entry_id, is, MCUCTL_REG_ISSR(2));
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fimc_is_hw_set_intgr0_gd0(is);
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return 0;
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}
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#define FIMC_IS_MAX_PARAMS 4
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int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num_args)
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{
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int i;
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if (num_args > FIMC_IS_MAX_PARAMS)
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return -EINVAL;
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is->i2h_cmd.num_args = num_args;
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for (i = 0; i < FIMC_IS_MAX_PARAMS; i++) {
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if (i < num_args)
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is->i2h_cmd.args[i] = mcuctl_read(is,
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MCUCTL_REG_ISSR(12 + i));
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else
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is->i2h_cmd.args[i] = 0;
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}
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return 0;
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}
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void fimc_is_hw_set_isp_buf_mask(struct fimc_is *is, unsigned int mask)
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{
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if (hweight32(mask) == 1) {
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dev_err(&is->pdev->dev, "%s(): not enough buffers (mask %#x)\n",
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__func__, mask);
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return;
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}
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if (mcuctl_read(is, MCUCTL_REG_ISSR(23)) != 0)
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dev_dbg(&is->pdev->dev, "non-zero DMA buffer mask\n");
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mcuctl_write(mask, is, MCUCTL_REG_ISSR(23));
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}
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void fimc_is_hw_set_sensor_num(struct fimc_is *is)
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{
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pr_debug("setting sensor index to: %d\n", is->sensor_index);
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mcuctl_write(IH_REPLY_DONE, is, MCUCTL_REG_ISSR(0));
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mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
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mcuctl_write(IHC_GET_SENSOR_NUM, is, MCUCTL_REG_ISSR(2));
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mcuctl_write(FIMC_IS_SENSORS_NUM, is, MCUCTL_REG_ISSR(3));
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}
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void fimc_is_hw_close_sensor(struct fimc_is *is, unsigned int index)
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{
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if (is->sensor_index != index)
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return;
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fimc_is_hw_wait_intmsr0_intmsd0(is);
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mcuctl_write(HIC_CLOSE_SENSOR, is, MCUCTL_REG_ISSR(0));
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mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
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mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(2));
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fimc_is_hw_set_intgr0_gd0(is);
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}
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void fimc_is_hw_get_setfile_addr(struct fimc_is *is)
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{
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fimc_is_hw_wait_intmsr0_intmsd0(is);
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mcuctl_write(HIC_GET_SET_FILE_ADDR, is, MCUCTL_REG_ISSR(0));
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mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
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fimc_is_hw_set_intgr0_gd0(is);
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}
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void fimc_is_hw_load_setfile(struct fimc_is *is)
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{
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fimc_is_hw_wait_intmsr0_intmsd0(is);
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mcuctl_write(HIC_LOAD_SET_FILE, is, MCUCTL_REG_ISSR(0));
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mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
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fimc_is_hw_set_intgr0_gd0(is);
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}
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int fimc_is_hw_change_mode(struct fimc_is *is)
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{
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static const u8 cmd[] = {
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HIC_PREVIEW_STILL, HIC_PREVIEW_VIDEO,
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HIC_CAPTURE_STILL, HIC_CAPTURE_VIDEO,
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};
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if (WARN_ON(is->config_index >= ARRAY_SIZE(cmd)))
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return -EINVAL;
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mcuctl_write(cmd[is->config_index], is, MCUCTL_REG_ISSR(0));
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mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
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mcuctl_write(is->setfile.sub_index, is, MCUCTL_REG_ISSR(2));
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fimc_is_hw_set_intgr0_gd0(is);
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return 0;
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}
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void fimc_is_hw_stream_on(struct fimc_is *is)
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{
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fimc_is_hw_wait_intmsr0_intmsd0(is);
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mcuctl_write(HIC_STREAM_ON, is, MCUCTL_REG_ISSR(0));
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mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
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mcuctl_write(0, is, MCUCTL_REG_ISSR(2));
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fimc_is_hw_set_intgr0_gd0(is);
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}
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void fimc_is_hw_stream_off(struct fimc_is *is)
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{
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fimc_is_hw_wait_intmsr0_intmsd0(is);
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mcuctl_write(HIC_STREAM_OFF, is, MCUCTL_REG_ISSR(0));
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mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
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fimc_is_hw_set_intgr0_gd0(is);
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}
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void fimc_is_hw_subip_power_off(struct fimc_is *is)
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{
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fimc_is_hw_wait_intmsr0_intmsd0(is);
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mcuctl_write(HIC_POWER_DOWN, is, MCUCTL_REG_ISSR(0));
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mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
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fimc_is_hw_set_intgr0_gd0(is);
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}
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int fimc_is_itf_s_param(struct fimc_is *is, bool update)
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{
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int ret;
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if (update)
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__is_hw_update_params(is);
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fimc_is_mem_barrier();
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clear_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
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fimc_is_hw_set_param(is);
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ret = fimc_is_wait_event(is, IS_ST_BLOCK_CMD_CLEARED, 1,
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FIMC_IS_CONFIG_TIMEOUT);
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if (ret < 0)
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dev_err(&is->pdev->dev, "%s() timeout\n", __func__);
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return ret;
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}
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int fimc_is_itf_mode_change(struct fimc_is *is)
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{
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int ret;
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clear_bit(IS_ST_CHANGE_MODE, &is->state);
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fimc_is_hw_change_mode(is);
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ret = fimc_is_wait_event(is, IS_ST_CHANGE_MODE, 1,
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FIMC_IS_CONFIG_TIMEOUT);
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if (ret < 0)
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dev_err(&is->pdev->dev, "%s(): mode change (%d) timeout\n",
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__func__, is->config_index);
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return ret;
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}
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