/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
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*/
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#ifndef FIMC_CORE_H_
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#define FIMC_CORE_H_
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/*#define DEBUG*/
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/mfd/syscon.h>
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#include <linux/types.h>
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#include <linux/videodev2.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <media/media-entity.h>
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#include <media/videobuf2-v4l2.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-mem2mem.h>
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#include <media/v4l2-mediabus.h>
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#include <media/drv-intf/exynos-fimc.h>
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#define dbg(fmt, args...) \
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pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
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/* Time to wait for next frame VSYNC interrupt while stopping operation. */
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#define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
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#define MAX_FIMC_CLOCKS 2
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#define FIMC_DRIVER_NAME "exynos4-fimc"
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#define FIMC_MAX_DEVS 4
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#define FIMC_MAX_OUT_BUFS 4
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#define SCALER_MAX_HRATIO 64
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#define SCALER_MAX_VRATIO 64
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#define DMA_MIN_SIZE 8
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#define FIMC_CAMIF_MAX_HEIGHT 0x2000
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#define FIMC_MAX_JPEG_BUF_SIZE (10 * SZ_1M)
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#define FIMC_MAX_PLANES 3
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#define FIMC_PIX_LIMITS_MAX 4
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#define FIMC_DEF_MIN_SIZE 16
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#define FIMC_DEF_HEIGHT_ALIGN 2
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#define FIMC_DEF_HOR_OFFS_ALIGN 1
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#define FIMC_DEFAULT_WIDTH 640
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#define FIMC_DEFAULT_HEIGHT 480
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/* indices to the clocks array */
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enum {
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CLK_BUS,
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CLK_GATE,
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};
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enum fimc_dev_flags {
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ST_LPM,
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/* m2m node */
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ST_M2M_RUN,
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ST_M2M_PEND,
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ST_M2M_SUSPENDING,
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ST_M2M_SUSPENDED,
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/* capture node */
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ST_CAPT_PEND,
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ST_CAPT_RUN,
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ST_CAPT_STREAM,
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ST_CAPT_ISP_STREAM,
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ST_CAPT_SUSPENDED,
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ST_CAPT_SHUT,
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ST_CAPT_BUSY,
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ST_CAPT_APPLY_CFG,
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ST_CAPT_JPEG,
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};
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#define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
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#define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
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#define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
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#define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
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#define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
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enum fimc_datapath {
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FIMC_IO_NONE,
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FIMC_IO_CAMERA,
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FIMC_IO_DMA,
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FIMC_IO_LCDFIFO,
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FIMC_IO_WRITEBACK,
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FIMC_IO_ISP,
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};
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enum fimc_color_fmt {
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FIMC_FMT_RGB444 = 0x10,
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FIMC_FMT_RGB555,
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FIMC_FMT_RGB565,
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FIMC_FMT_RGB666,
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FIMC_FMT_RGB888,
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FIMC_FMT_RGB30_LOCAL,
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FIMC_FMT_YCBCR420 = 0x20,
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FIMC_FMT_YCBYCR422,
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FIMC_FMT_YCRYCB422,
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FIMC_FMT_CBYCRY422,
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FIMC_FMT_CRYCBY422,
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FIMC_FMT_YCBCR444_LOCAL,
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FIMC_FMT_RAW8 = 0x40,
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FIMC_FMT_RAW10,
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FIMC_FMT_RAW12,
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FIMC_FMT_JPEG = 0x80,
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FIMC_FMT_YUYV_JPEG = 0x100,
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};
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#define fimc_fmt_is_user_defined(x) (!!((x) & 0x180))
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#define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
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#define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
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__strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
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/* The hardware context state. */
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#define FIMC_PARAMS (1 << 0)
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#define FIMC_COMPOSE (1 << 1)
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#define FIMC_CTX_M2M (1 << 16)
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#define FIMC_CTX_CAP (1 << 17)
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#define FIMC_CTX_SHUT (1 << 18)
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/* Image conversion flags */
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#define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
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#define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
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#define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
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#define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
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#define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
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#define FIMC_SCAN_MODE_INTERLACED (1 << 2)
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/*
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* YCbCr data dynamic range for RGB-YUV color conversion.
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* Y/Cb/Cr: (0 ~ 255) */
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#define FIMC_COLOR_RANGE_WIDE (0 << 3)
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/* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
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#define FIMC_COLOR_RANGE_NARROW (1 << 3)
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/**
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* struct fimc_dma_offset - pixel offset information for DMA
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* @y_h: y value horizontal offset
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* @y_v: y value vertical offset
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* @cb_h: cb value horizontal offset
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* @cb_v: cb value vertical offset
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* @cr_h: cr value horizontal offset
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* @cr_v: cr value vertical offset
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*/
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struct fimc_dma_offset {
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int y_h;
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int y_v;
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int cb_h;
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int cb_v;
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int cr_h;
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int cr_v;
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};
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/**
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* struct fimc_effect - color effect information
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* @type: effect type
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* @pat_cb: cr value when type is "arbitrary"
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* @pat_cr: cr value when type is "arbitrary"
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*/
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struct fimc_effect {
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u32 type;
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u8 pat_cb;
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u8 pat_cr;
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};
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/**
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* struct fimc_scaler - the configuration data for FIMC inetrnal scaler
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* @scaleup_h: flag indicating scaling up horizontally
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* @scaleup_v: flag indicating scaling up vertically
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* @copy_mode: flag indicating transparent DMA transfer (no scaling
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* and color format conversion)
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* @enabled: flag indicating if the scaler is used
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* @hfactor: horizontal shift factor
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* @vfactor: vertical shift factor
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* @pre_hratio: horizontal ratio of the prescaler
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* @pre_vratio: vertical ratio of the prescaler
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* @pre_dst_width: the prescaler's destination width
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* @pre_dst_height: the prescaler's destination height
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* @main_hratio: the main scaler's horizontal ratio
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* @main_vratio: the main scaler's vertical ratio
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* @real_width: source pixel (width - offset)
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* @real_height: source pixel (height - offset)
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*/
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struct fimc_scaler {
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unsigned int scaleup_h:1;
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unsigned int scaleup_v:1;
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unsigned int copy_mode:1;
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unsigned int enabled:1;
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u32 hfactor;
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u32 vfactor;
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u32 pre_hratio;
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u32 pre_vratio;
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u32 pre_dst_width;
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u32 pre_dst_height;
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u32 main_hratio;
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u32 main_vratio;
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u32 real_width;
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u32 real_height;
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};
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/**
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* struct fimc_addr - the FIMC physical address set for DMA
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* @y: luminance plane physical address
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* @cb: Cb plane physical address
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* @cr: Cr plane physical address
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*/
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struct fimc_addr {
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u32 y;
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u32 cb;
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u32 cr;
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};
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/**
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* struct fimc_vid_buffer - the driver's video buffer
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* @vb: v4l videobuf buffer
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* @list: linked list structure for buffer queue
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* @paddr: precalculated physical address set
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* @index: buffer index for the output DMA engine
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*/
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struct fimc_vid_buffer {
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struct vb2_v4l2_buffer vb;
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struct list_head list;
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struct fimc_addr paddr;
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int index;
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};
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/**
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* struct fimc_frame - source/target frame properties
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* @f_width: image full width (virtual screen size)
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* @f_height: image full height (virtual screen size)
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* @o_width: original image width as set by S_FMT
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* @o_height: original image height as set by S_FMT
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* @offs_h: image horizontal pixel offset
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* @offs_v: image vertical pixel offset
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* @width: image pixel width
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* @height: image pixel weight
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* @payload: image size in bytes (w x h x bpp)
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* @bytesperline: bytesperline value for each plane
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* @paddr: image frame buffer physical addresses
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* @dma_offset: DMA offset in bytes
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* @fmt: fimc color format pointer
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*/
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struct fimc_frame {
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u32 f_width;
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u32 f_height;
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u32 o_width;
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u32 o_height;
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u32 offs_h;
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u32 offs_v;
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u32 width;
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u32 height;
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unsigned int payload[VIDEO_MAX_PLANES];
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unsigned int bytesperline[VIDEO_MAX_PLANES];
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struct fimc_addr paddr;
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struct fimc_dma_offset dma_offset;
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struct fimc_fmt *fmt;
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u8 alpha;
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};
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/**
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* struct fimc_m2m_device - v4l2 memory-to-memory device data
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* @vfd: the video device node for v4l2 m2m mode
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* @m2m_dev: v4l2 memory-to-memory device data
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* @ctx: hardware context data
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* @refcnt: the reference counter
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*/
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struct fimc_m2m_device {
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struct video_device vfd;
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struct v4l2_m2m_dev *m2m_dev;
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struct fimc_ctx *ctx;
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int refcnt;
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};
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#define FIMC_SD_PAD_SINK_CAM 0
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#define FIMC_SD_PAD_SINK_FIFO 1
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#define FIMC_SD_PAD_SOURCE 2
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#define FIMC_SD_PADS_NUM 3
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/**
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* struct fimc_vid_cap - camera capture device information
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* @ctx: hardware context data
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* @subdev: subdev exposing the FIMC processing block
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* @ve: exynos video device entity structure
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* @vd_pad: fimc video capture node pad
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* @sd_pads: fimc video processing block pads
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* @ci_fmt: image format at the FIMC camera input (and the scaler output)
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* @wb_fmt: image format at the FIMC ISP Writeback input
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* @source_config: external image source related configuration structure
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* @pending_buf_q: the pending buffer queue head
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* @active_buf_q: the queue head of buffers scheduled in hardware
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* @vbq: the capture am video buffer queue
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* @active_buf_cnt: number of video buffers scheduled in hardware
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* @buf_index: index for managing the output DMA buffers
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* @frame_count: the frame counter for statistics
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* @reqbufs_count: the number of buffers requested in REQBUFS ioctl
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* @input: capture input type, grp_id of the attached subdev
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* @user_subdev_api: true if subdevs are not configured by the host driver
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*/
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struct fimc_vid_cap {
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struct fimc_ctx *ctx;
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struct v4l2_subdev subdev;
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struct exynos_video_entity ve;
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struct media_pad vd_pad;
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struct media_pad sd_pads[FIMC_SD_PADS_NUM];
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struct v4l2_mbus_framefmt ci_fmt;
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struct v4l2_mbus_framefmt wb_fmt;
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struct fimc_source_info source_config;
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struct list_head pending_buf_q;
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struct list_head active_buf_q;
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struct vb2_queue vbq;
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int active_buf_cnt;
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int buf_index;
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unsigned int frame_count;
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unsigned int reqbufs_count;
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bool streaming;
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u32 input;
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bool user_subdev_api;
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};
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/**
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* struct fimc_pix_limit - image pixel size limits in various IP configurations
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*
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* @scaler_en_w: max input pixel width when the scaler is enabled
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* @scaler_dis_w: max input pixel width when the scaler is disabled
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* @in_rot_en_h: max input width with the input rotator is on
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* @in_rot_dis_w: max input width with the input rotator is off
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* @out_rot_en_w: max output width with the output rotator on
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* @out_rot_dis_w: max output width with the output rotator off
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*/
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struct fimc_pix_limit {
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u16 scaler_en_w;
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u16 scaler_dis_w;
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u16 in_rot_en_h;
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u16 in_rot_dis_w;
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u16 out_rot_en_w;
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u16 out_rot_dis_w;
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};
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/**
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* struct fimc_variant - FIMC device variant information
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* @has_inp_rot: set if has input rotator
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* @has_out_rot: set if has output rotator
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* @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
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* are present in this IP revision
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* @has_cam_if: set if this instance has a camera input interface
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* @has_isp_wb: set if this instance has ISP writeback input
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* @pix_limit: pixel size constraints for the scaler
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* @min_inp_pixsize: minimum input pixel size
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* @min_out_pixsize: minimum output pixel size
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* @hor_offs_align: horizontal pixel offset alignment
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* @min_vsize_align: minimum vertical pixel size alignment
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*/
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struct fimc_variant {
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unsigned int has_inp_rot:1;
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unsigned int has_out_rot:1;
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unsigned int has_mainscaler_ext:1;
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unsigned int has_cam_if:1;
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unsigned int has_isp_wb:1;
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const struct fimc_pix_limit *pix_limit;
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u16 min_inp_pixsize;
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u16 min_out_pixsize;
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u16 hor_offs_align;
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u16 min_vsize_align;
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};
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/**
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* struct fimc_drvdata - per device type driver data
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* @variant: variant information for this device
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* @num_entities: number of fimc instances available in a SoC
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* @lclk_frequency: local bus clock frequency
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* @cistatus2: 1 if the FIMC IPs have CISTATUS2 register
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* @dma_pix_hoff: the horizontal DMA offset unit: 1 - pixels, 0 - bytes
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* @alpha_color: 1 if alpha color component is supported
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* @out_buf_count: maximum number of output DMA buffers supported
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*/
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struct fimc_drvdata {
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const struct fimc_variant *variant[FIMC_MAX_DEVS];
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int num_entities;
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unsigned long lclk_frequency;
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/* Fields common to all FIMC IP instances */
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u8 cistatus2;
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u8 dma_pix_hoff;
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u8 alpha_color;
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u8 out_buf_count;
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};
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#define fimc_get_drvdata(_pdev) \
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((struct fimc_drvdata *) platform_get_device_id(_pdev)->driver_data)
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struct fimc_ctx;
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/**
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* struct fimc_dev - abstraction for FIMC entity
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* @slock: the spinlock protecting this data structure
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* @lock: the mutex protecting this data structure
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* @pdev: pointer to the FIMC platform device
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* @pdata: pointer to the device platform data
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* @sysreg: pointer to the SYSREG regmap
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* @variant: the IP variant information
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* @id: FIMC device index (0..FIMC_MAX_DEVS)
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* @clock: clocks required for FIMC operation
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* @regs: the mapped hardware registers
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* @irq_queue: interrupt handler waitqueue
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* @v4l2_dev: root v4l2_device
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* @m2m: memory-to-memory V4L2 device information
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* @vid_cap: camera capture device information
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* @state: flags used to synchronize m2m and capture mode operation
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* @pipeline: fimc video capture pipeline data structure
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*/
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struct fimc_dev {
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spinlock_t slock;
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struct mutex lock;
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struct platform_device *pdev;
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struct s5p_platform_fimc *pdata;
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struct regmap *sysreg;
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const struct fimc_variant *variant;
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const struct fimc_drvdata *drv_data;
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int id;
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struct clk *clock[MAX_FIMC_CLOCKS];
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void __iomem *regs;
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wait_queue_head_t irq_queue;
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struct v4l2_device *v4l2_dev;
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struct fimc_m2m_device m2m;
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struct fimc_vid_cap vid_cap;
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unsigned long state;
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};
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/**
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* struct fimc_ctrls - v4l2 controls structure
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* @handler: the control handler
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* @colorfx: image effect control
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* @colorfx_cbcr: Cb/Cr coefficients control
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* @rotate: image rotation control
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* @hflip: horizontal flip control
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* @vflip: vertical flip control
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* @alpha: RGB alpha control
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* @ready: true if @handler is initialized
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*/
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struct fimc_ctrls {
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struct v4l2_ctrl_handler handler;
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struct {
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struct v4l2_ctrl *colorfx;
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struct v4l2_ctrl *colorfx_cbcr;
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};
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struct v4l2_ctrl *rotate;
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struct v4l2_ctrl *hflip;
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struct v4l2_ctrl *vflip;
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struct v4l2_ctrl *alpha;
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bool ready;
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};
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/**
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* fimc_ctx - the device context data
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* @s_frame: source frame properties
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* @d_frame: destination frame properties
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* @out_order_1p: output 1-plane YCBCR order
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* @out_order_2p: output 2-plane YCBCR order
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* @in_order_1p input 1-plane YCBCR order
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* @in_order_2p: input 2-plane YCBCR order
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* @in_path: input mode (DMA or camera)
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* @out_path: output mode (DMA or FIFO)
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* @scaler: image scaler properties
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* @effect: image effect
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* @rotation: image clockwise rotation in degrees
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* @hflip: indicates image horizontal flip if set
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* @vflip: indicates image vertical flip if set
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* @flags: additional flags for image conversion
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* @state: flags to keep track of user configuration
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* @fimc_dev: the FIMC device this context applies to
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* @fh: v4l2 file handle
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* @ctrls: v4l2 controls structure
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*/
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struct fimc_ctx {
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struct fimc_frame s_frame;
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struct fimc_frame d_frame;
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u32 out_order_1p;
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u32 out_order_2p;
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u32 in_order_1p;
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u32 in_order_2p;
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enum fimc_datapath in_path;
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enum fimc_datapath out_path;
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struct fimc_scaler scaler;
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struct fimc_effect effect;
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int rotation;
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unsigned int hflip:1;
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unsigned int vflip:1;
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u32 flags;
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u32 state;
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struct fimc_dev *fimc_dev;
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struct v4l2_fh fh;
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struct fimc_ctrls ctrls;
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};
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#define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
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static inline void set_frame_bounds(struct fimc_frame *f, u32 width, u32 height)
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{
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f->o_width = width;
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f->o_height = height;
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f->f_width = width;
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f->f_height = height;
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}
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static inline void set_frame_crop(struct fimc_frame *f,
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u32 left, u32 top, u32 width, u32 height)
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{
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f->offs_h = left;
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f->offs_v = top;
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f->width = width;
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f->height = height;
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}
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static inline u32 fimc_get_format_depth(struct fimc_fmt *ff)
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{
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u32 i, depth = 0;
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if (ff != NULL)
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for (i = 0; i < ff->colplanes; i++)
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depth += ff->depth[i];
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return depth;
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}
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static inline bool fimc_capture_active(struct fimc_dev *fimc)
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{
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unsigned long flags;
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bool ret;
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spin_lock_irqsave(&fimc->slock, flags);
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ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
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fimc->state & (1 << ST_CAPT_PEND));
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spin_unlock_irqrestore(&fimc->slock, flags);
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return ret;
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}
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static inline void fimc_ctx_state_set(u32 state, struct fimc_ctx *ctx)
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{
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unsigned long flags;
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spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
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ctx->state |= state;
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spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
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}
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static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
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{
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unsigned long flags;
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bool ret;
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spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
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ret = (ctx->state & mask) == mask;
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spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
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return ret;
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}
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static inline int tiled_fmt(struct fimc_fmt *fmt)
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{
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return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
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}
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static inline bool fimc_jpeg_fourcc(u32 pixelformat)
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{
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return (pixelformat == V4L2_PIX_FMT_JPEG ||
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pixelformat == V4L2_PIX_FMT_S5C_UYVY_JPG);
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}
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static inline bool fimc_user_defined_mbus_fmt(u32 code)
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{
|
return (code == MEDIA_BUS_FMT_JPEG_1X8 ||
|
code == MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8);
|
}
|
|
/* Return the alpha component bit mask */
|
static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt)
|
{
|
switch (fmt->color) {
|
case FIMC_FMT_RGB444: return 0x0f;
|
case FIMC_FMT_RGB555: return 0x01;
|
case FIMC_FMT_RGB888: return 0xff;
|
default: return 0;
|
};
|
}
|
|
static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
|
enum v4l2_buf_type type)
|
{
|
struct fimc_frame *frame;
|
|
if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ||
|
type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
|
if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
|
frame = &ctx->s_frame;
|
else
|
return ERR_PTR(-EINVAL);
|
} else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||
|
type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
|
frame = &ctx->d_frame;
|
} else {
|
v4l2_err(ctx->fimc_dev->v4l2_dev,
|
"Wrong buffer/video queue type (%d)\n", type);
|
return ERR_PTR(-EINVAL);
|
}
|
|
return frame;
|
}
|
|
/* -----------------------------------------------------*/
|
/* fimc-core.c */
|
int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
|
struct v4l2_fmtdesc *f);
|
int fimc_ctrls_create(struct fimc_ctx *ctx);
|
void fimc_ctrls_delete(struct fimc_ctx *ctx);
|
void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active);
|
void fimc_alpha_ctrl_update(struct fimc_ctx *ctx);
|
void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f);
|
void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
|
struct v4l2_pix_format_mplane *pix);
|
struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
|
unsigned int mask, int index);
|
struct fimc_fmt *fimc_get_format(unsigned int index);
|
|
int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
|
int dw, int dh, int rotation);
|
int fimc_set_scaler_info(struct fimc_ctx *ctx);
|
int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
|
int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
|
struct fimc_frame *frame, struct fimc_addr *paddr);
|
void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);
|
void fimc_set_yuv_order(struct fimc_ctx *ctx);
|
void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf);
|
|
int fimc_register_m2m_device(struct fimc_dev *fimc,
|
struct v4l2_device *v4l2_dev);
|
void fimc_unregister_m2m_device(struct fimc_dev *fimc);
|
int fimc_register_driver(void);
|
void fimc_unregister_driver(void);
|
|
#ifdef CONFIG_MFD_SYSCON
|
static inline struct regmap * fimc_get_sysreg_regmap(struct device_node *node)
|
{
|
return syscon_regmap_lookup_by_phandle(node, "samsung,sysreg");
|
}
|
#else
|
#define fimc_get_sysreg_regmap(node) (NULL)
|
#endif
|
|
/* -----------------------------------------------------*/
|
/* fimc-m2m.c */
|
void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state);
|
|
/* -----------------------------------------------------*/
|
/* fimc-capture.c */
|
int fimc_initialize_capture_subdev(struct fimc_dev *fimc);
|
void fimc_unregister_capture_subdev(struct fimc_dev *fimc);
|
int fimc_capture_ctrls_create(struct fimc_dev *fimc);
|
void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
|
void *arg);
|
int fimc_capture_suspend(struct fimc_dev *fimc);
|
int fimc_capture_resume(struct fimc_dev *fimc);
|
|
/*
|
* Buffer list manipulation functions. Must be called with fimc.slock held.
|
*/
|
|
/**
|
* fimc_active_queue_add - add buffer to the capture active buffers queue
|
* @buf: buffer to add to the active buffers list
|
*/
|
static inline void fimc_active_queue_add(struct fimc_vid_cap *vid_cap,
|
struct fimc_vid_buffer *buf)
|
{
|
list_add_tail(&buf->list, &vid_cap->active_buf_q);
|
vid_cap->active_buf_cnt++;
|
}
|
|
/**
|
* fimc_active_queue_pop - pop buffer from the capture active buffers queue
|
*
|
* The caller must assure the active_buf_q list is not empty.
|
*/
|
static inline struct fimc_vid_buffer *fimc_active_queue_pop(
|
struct fimc_vid_cap *vid_cap)
|
{
|
struct fimc_vid_buffer *buf;
|
buf = list_entry(vid_cap->active_buf_q.next,
|
struct fimc_vid_buffer, list);
|
list_del(&buf->list);
|
vid_cap->active_buf_cnt--;
|
return buf;
|
}
|
|
/**
|
* fimc_pending_queue_add - add buffer to the capture pending buffers queue
|
* @buf: buffer to add to the pending buffers list
|
*/
|
static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
|
struct fimc_vid_buffer *buf)
|
{
|
list_add_tail(&buf->list, &vid_cap->pending_buf_q);
|
}
|
|
/**
|
* fimc_pending_queue_pop - pop buffer from the capture pending buffers queue
|
*
|
* The caller must assure the pending_buf_q list is not empty.
|
*/
|
static inline struct fimc_vid_buffer *fimc_pending_queue_pop(
|
struct fimc_vid_cap *vid_cap)
|
{
|
struct fimc_vid_buffer *buf;
|
buf = list_entry(vid_cap->pending_buf_q.next,
|
struct fimc_vid_buffer, list);
|
list_del(&buf->list);
|
return buf;
|
}
|
|
#endif /* FIMC_CORE_H_ */
|
