// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2009 Texas Instruments.
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*
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* common vpss system module platform driver for all video drivers.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/err.h>
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#include <media/davinci/vpss.h>
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("VPSS Driver");
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MODULE_AUTHOR("Texas Instruments");
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/* DM644x defines */
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#define DM644X_SBL_PCR_VPSS (4)
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#define DM355_VPSSBL_INTSEL 0x10
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#define DM355_VPSSBL_EVTSEL 0x14
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/* vpss BL register offsets */
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#define DM355_VPSSBL_CCDCMUX 0x1c
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/* vpss CLK register offsets */
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#define DM355_VPSSCLK_CLKCTRL 0x04
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/* masks and shifts */
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#define VPSS_HSSISEL_SHIFT 4
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/*
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* VDINT0 - vpss_int0, VDINT1 - vpss_int1, H3A - vpss_int4,
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* IPIPE_INT1_SDR - vpss_int5
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*/
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#define DM355_VPSSBL_INTSEL_DEFAULT 0xff83ff10
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/* VENCINT - vpss_int8 */
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#define DM355_VPSSBL_EVTSEL_DEFAULT 0x4
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#define DM365_ISP5_PCCR 0x04
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#define DM365_ISP5_PCCR_BL_CLK_ENABLE BIT(0)
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#define DM365_ISP5_PCCR_ISIF_CLK_ENABLE BIT(1)
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#define DM365_ISP5_PCCR_H3A_CLK_ENABLE BIT(2)
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#define DM365_ISP5_PCCR_RSZ_CLK_ENABLE BIT(3)
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#define DM365_ISP5_PCCR_IPIPE_CLK_ENABLE BIT(4)
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#define DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE BIT(5)
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#define DM365_ISP5_PCCR_RSV BIT(6)
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#define DM365_ISP5_BCR 0x08
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#define DM365_ISP5_BCR_ISIF_OUT_ENABLE BIT(1)
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#define DM365_ISP5_INTSEL1 0x10
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#define DM365_ISP5_INTSEL2 0x14
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#define DM365_ISP5_INTSEL3 0x18
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#define DM365_ISP5_CCDCMUX 0x20
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#define DM365_ISP5_PG_FRAME_SIZE 0x28
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#define DM365_VPBE_CLK_CTRL 0x00
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#define VPSS_CLK_CTRL 0x01c40044
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#define VPSS_CLK_CTRL_VENCCLKEN BIT(3)
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#define VPSS_CLK_CTRL_DACCLKEN BIT(4)
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/*
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* vpss interrupts. VDINT0 - vpss_int0, VDINT1 - vpss_int1,
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* AF - vpss_int3
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*/
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#define DM365_ISP5_INTSEL1_DEFAULT 0x0b1f0100
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/* AEW - vpss_int6, RSZ_INT_DMA - vpss_int5 */
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#define DM365_ISP5_INTSEL2_DEFAULT 0x1f0a0f1f
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/* VENC - vpss_int8 */
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#define DM365_ISP5_INTSEL3_DEFAULT 0x00000015
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/* masks and shifts for DM365*/
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#define DM365_CCDC_PG_VD_POL_SHIFT 0
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#define DM365_CCDC_PG_HD_POL_SHIFT 1
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#define CCD_SRC_SEL_MASK (BIT_MASK(5) | BIT_MASK(4))
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#define CCD_SRC_SEL_SHIFT 4
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/* Different SoC platforms supported by this driver */
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enum vpss_platform_type {
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DM644X,
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DM355,
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DM365,
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};
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/*
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* vpss operations. Depends on platform. Not all functions are available
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* on all platforms. The api, first check if a function is available before
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* invoking it. In the probe, the function ptrs are initialized based on
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* vpss name. vpss name can be "dm355_vpss", "dm644x_vpss" etc.
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*/
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struct vpss_hw_ops {
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/* enable clock */
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int (*enable_clock)(enum vpss_clock_sel clock_sel, int en);
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/* select input to ccdc */
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void (*select_ccdc_source)(enum vpss_ccdc_source_sel src_sel);
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/* clear wbl overflow bit */
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int (*clear_wbl_overflow)(enum vpss_wbl_sel wbl_sel);
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/* set sync polarity */
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void (*set_sync_pol)(struct vpss_sync_pol);
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/* set the PG_FRAME_SIZE register*/
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void (*set_pg_frame_size)(struct vpss_pg_frame_size);
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/* check and clear interrupt if occurred */
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int (*dma_complete_interrupt)(void);
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};
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/* vpss configuration */
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struct vpss_oper_config {
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__iomem void *vpss_regs_base0;
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__iomem void *vpss_regs_base1;
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__iomem void *vpss_regs_base2;
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enum vpss_platform_type platform;
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spinlock_t vpss_lock;
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struct vpss_hw_ops hw_ops;
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};
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static struct vpss_oper_config oper_cfg;
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/* register access routines */
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static inline u32 bl_regr(u32 offset)
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{
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return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
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}
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static inline void bl_regw(u32 val, u32 offset)
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{
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__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
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}
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static inline u32 vpss_regr(u32 offset)
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{
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return __raw_readl(oper_cfg.vpss_regs_base1 + offset);
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}
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static inline void vpss_regw(u32 val, u32 offset)
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{
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__raw_writel(val, oper_cfg.vpss_regs_base1 + offset);
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}
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/* For DM365 only */
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static inline u32 isp5_read(u32 offset)
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{
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return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
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}
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/* For DM365 only */
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static inline void isp5_write(u32 val, u32 offset)
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{
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__raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
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}
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static void dm365_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
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{
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u32 temp = isp5_read(DM365_ISP5_CCDCMUX) & ~CCD_SRC_SEL_MASK;
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/* if we are using pattern generator, enable it */
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if (src_sel == VPSS_PGLPBK || src_sel == VPSS_CCDCPG)
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temp |= 0x08;
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temp |= (src_sel << CCD_SRC_SEL_SHIFT);
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isp5_write(temp, DM365_ISP5_CCDCMUX);
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}
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static void dm355_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
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{
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bl_regw(src_sel << VPSS_HSSISEL_SHIFT, DM355_VPSSBL_CCDCMUX);
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}
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int vpss_dma_complete_interrupt(void)
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{
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if (!oper_cfg.hw_ops.dma_complete_interrupt)
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return 2;
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return oper_cfg.hw_ops.dma_complete_interrupt();
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}
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EXPORT_SYMBOL(vpss_dma_complete_interrupt);
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int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel)
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{
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if (!oper_cfg.hw_ops.select_ccdc_source)
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return -EINVAL;
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oper_cfg.hw_ops.select_ccdc_source(src_sel);
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return 0;
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}
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EXPORT_SYMBOL(vpss_select_ccdc_source);
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static int dm644x_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
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{
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u32 mask = 1, val;
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if (wbl_sel < VPSS_PCR_AEW_WBL_0 ||
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wbl_sel > VPSS_PCR_CCDC_WBL_O)
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return -EINVAL;
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/* writing a 0 clear the overflow */
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mask = ~(mask << wbl_sel);
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val = bl_regr(DM644X_SBL_PCR_VPSS) & mask;
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bl_regw(val, DM644X_SBL_PCR_VPSS);
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return 0;
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}
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void vpss_set_sync_pol(struct vpss_sync_pol sync)
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{
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if (!oper_cfg.hw_ops.set_sync_pol)
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return;
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oper_cfg.hw_ops.set_sync_pol(sync);
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}
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EXPORT_SYMBOL(vpss_set_sync_pol);
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int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel)
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{
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if (!oper_cfg.hw_ops.clear_wbl_overflow)
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return -EINVAL;
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return oper_cfg.hw_ops.clear_wbl_overflow(wbl_sel);
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}
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EXPORT_SYMBOL(vpss_clear_wbl_overflow);
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/*
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* dm355_enable_clock - Enable VPSS Clock
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* @clock_sel: Clock to be enabled/disabled
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* @en: enable/disable flag
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*
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* This is called to enable or disable a vpss clock
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*/
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static int dm355_enable_clock(enum vpss_clock_sel clock_sel, int en)
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{
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unsigned long flags;
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u32 utemp, mask = 0x1, shift = 0;
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switch (clock_sel) {
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case VPSS_VPBE_CLOCK:
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/* nothing since lsb */
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break;
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case VPSS_VENC_CLOCK_SEL:
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shift = 2;
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break;
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case VPSS_CFALD_CLOCK:
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shift = 3;
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break;
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case VPSS_H3A_CLOCK:
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shift = 4;
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break;
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case VPSS_IPIPE_CLOCK:
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shift = 5;
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break;
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case VPSS_CCDC_CLOCK:
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shift = 6;
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break;
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default:
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printk(KERN_ERR "dm355_enable_clock: Invalid selector: %d\n",
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clock_sel);
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return -EINVAL;
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}
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spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
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utemp = vpss_regr(DM355_VPSSCLK_CLKCTRL);
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if (!en)
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utemp &= ~(mask << shift);
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else
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utemp |= (mask << shift);
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vpss_regw(utemp, DM355_VPSSCLK_CLKCTRL);
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spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
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return 0;
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}
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static int dm365_enable_clock(enum vpss_clock_sel clock_sel, int en)
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{
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unsigned long flags;
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u32 utemp, mask = 0x1, shift = 0, offset = DM365_ISP5_PCCR;
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u32 (*read)(u32 offset) = isp5_read;
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void(*write)(u32 val, u32 offset) = isp5_write;
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switch (clock_sel) {
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case VPSS_BL_CLOCK:
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break;
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case VPSS_CCDC_CLOCK:
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shift = 1;
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break;
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case VPSS_H3A_CLOCK:
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shift = 2;
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break;
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case VPSS_RSZ_CLOCK:
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shift = 3;
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break;
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case VPSS_IPIPE_CLOCK:
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shift = 4;
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break;
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case VPSS_IPIPEIF_CLOCK:
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shift = 5;
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break;
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case VPSS_PCLK_INTERNAL:
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shift = 6;
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break;
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case VPSS_PSYNC_CLOCK_SEL:
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shift = 7;
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break;
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case VPSS_VPBE_CLOCK:
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read = vpss_regr;
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write = vpss_regw;
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offset = DM365_VPBE_CLK_CTRL;
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break;
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case VPSS_VENC_CLOCK_SEL:
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shift = 2;
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read = vpss_regr;
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write = vpss_regw;
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offset = DM365_VPBE_CLK_CTRL;
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break;
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case VPSS_LDC_CLOCK:
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shift = 3;
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read = vpss_regr;
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write = vpss_regw;
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offset = DM365_VPBE_CLK_CTRL;
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break;
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case VPSS_FDIF_CLOCK:
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shift = 4;
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read = vpss_regr;
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write = vpss_regw;
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offset = DM365_VPBE_CLK_CTRL;
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break;
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case VPSS_OSD_CLOCK_SEL:
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shift = 6;
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read = vpss_regr;
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write = vpss_regw;
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offset = DM365_VPBE_CLK_CTRL;
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break;
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case VPSS_LDC_CLOCK_SEL:
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shift = 7;
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read = vpss_regr;
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write = vpss_regw;
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offset = DM365_VPBE_CLK_CTRL;
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break;
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default:
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printk(KERN_ERR "dm365_enable_clock: Invalid selector: %d\n",
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clock_sel);
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return -1;
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}
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spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
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utemp = read(offset);
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if (!en) {
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mask = ~mask;
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utemp &= (mask << shift);
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} else
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utemp |= (mask << shift);
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write(utemp, offset);
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spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
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return 0;
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}
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int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en)
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{
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if (!oper_cfg.hw_ops.enable_clock)
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return -EINVAL;
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return oper_cfg.hw_ops.enable_clock(clock_sel, en);
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}
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EXPORT_SYMBOL(vpss_enable_clock);
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void dm365_vpss_set_sync_pol(struct vpss_sync_pol sync)
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{
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int val = 0;
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val = isp5_read(DM365_ISP5_CCDCMUX);
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val |= (sync.ccdpg_hdpol << DM365_CCDC_PG_HD_POL_SHIFT);
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val |= (sync.ccdpg_vdpol << DM365_CCDC_PG_VD_POL_SHIFT);
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isp5_write(val, DM365_ISP5_CCDCMUX);
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}
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EXPORT_SYMBOL(dm365_vpss_set_sync_pol);
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void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
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{
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if (!oper_cfg.hw_ops.set_pg_frame_size)
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return;
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oper_cfg.hw_ops.set_pg_frame_size(frame_size);
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}
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EXPORT_SYMBOL(vpss_set_pg_frame_size);
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void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size)
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{
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int current_reg = ((frame_size.hlpfr >> 1) - 1) << 16;
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current_reg |= (frame_size.pplen - 1);
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isp5_write(current_reg, DM365_ISP5_PG_FRAME_SIZE);
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}
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EXPORT_SYMBOL(dm365_vpss_set_pg_frame_size);
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static int vpss_probe(struct platform_device *pdev)
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{
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struct resource *res;
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char *platform_name;
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if (!pdev->dev.platform_data) {
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dev_err(&pdev->dev, "no platform data\n");
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return -ENOENT;
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}
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platform_name = pdev->dev.platform_data;
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if (!strcmp(platform_name, "dm355_vpss"))
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oper_cfg.platform = DM355;
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else if (!strcmp(platform_name, "dm365_vpss"))
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oper_cfg.platform = DM365;
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else if (!strcmp(platform_name, "dm644x_vpss"))
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oper_cfg.platform = DM644X;
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else {
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dev_err(&pdev->dev, "vpss driver not supported on this platform\n");
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return -ENODEV;
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}
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dev_info(&pdev->dev, "%s vpss probed\n", platform_name);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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oper_cfg.vpss_regs_base0 = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(oper_cfg.vpss_regs_base0))
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return PTR_ERR(oper_cfg.vpss_regs_base0);
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if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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oper_cfg.vpss_regs_base1 = devm_ioremap_resource(&pdev->dev,
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res);
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if (IS_ERR(oper_cfg.vpss_regs_base1))
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return PTR_ERR(oper_cfg.vpss_regs_base1);
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}
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if (oper_cfg.platform == DM355) {
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oper_cfg.hw_ops.enable_clock = dm355_enable_clock;
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oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source;
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/* Setup vpss interrupts */
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bl_regw(DM355_VPSSBL_INTSEL_DEFAULT, DM355_VPSSBL_INTSEL);
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bl_regw(DM355_VPSSBL_EVTSEL_DEFAULT, DM355_VPSSBL_EVTSEL);
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} else if (oper_cfg.platform == DM365) {
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oper_cfg.hw_ops.enable_clock = dm365_enable_clock;
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oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source;
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/* Setup vpss interrupts */
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isp5_write((isp5_read(DM365_ISP5_PCCR) |
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DM365_ISP5_PCCR_BL_CLK_ENABLE |
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DM365_ISP5_PCCR_ISIF_CLK_ENABLE |
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DM365_ISP5_PCCR_H3A_CLK_ENABLE |
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DM365_ISP5_PCCR_RSZ_CLK_ENABLE |
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DM365_ISP5_PCCR_IPIPE_CLK_ENABLE |
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DM365_ISP5_PCCR_IPIPEIF_CLK_ENABLE |
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DM365_ISP5_PCCR_RSV), DM365_ISP5_PCCR);
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isp5_write((isp5_read(DM365_ISP5_BCR) |
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DM365_ISP5_BCR_ISIF_OUT_ENABLE), DM365_ISP5_BCR);
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isp5_write(DM365_ISP5_INTSEL1_DEFAULT, DM365_ISP5_INTSEL1);
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isp5_write(DM365_ISP5_INTSEL2_DEFAULT, DM365_ISP5_INTSEL2);
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isp5_write(DM365_ISP5_INTSEL3_DEFAULT, DM365_ISP5_INTSEL3);
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} else
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oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow;
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get(&pdev->dev);
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spin_lock_init(&oper_cfg.vpss_lock);
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dev_info(&pdev->dev, "%s vpss probe success\n", platform_name);
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return 0;
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}
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static int vpss_remove(struct platform_device *pdev)
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{
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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static int vpss_suspend(struct device *dev)
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{
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pm_runtime_put(dev);
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return 0;
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}
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static int vpss_resume(struct device *dev)
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{
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pm_runtime_get(dev);
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return 0;
|
}
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static const struct dev_pm_ops vpss_pm_ops = {
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.suspend = vpss_suspend,
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.resume = vpss_resume,
|
};
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static struct platform_driver vpss_driver = {
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.driver = {
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.name = "vpss",
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.pm = &vpss_pm_ops,
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},
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.remove = vpss_remove,
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.probe = vpss_probe,
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};
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static void vpss_exit(void)
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{
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platform_driver_unregister(&vpss_driver);
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iounmap(oper_cfg.vpss_regs_base2);
|
release_mem_region(VPSS_CLK_CTRL, 4);
|
}
|
|
static int __init vpss_init(void)
|
{
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int ret;
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|
if (!request_mem_region(VPSS_CLK_CTRL, 4, "vpss_clock_control"))
|
return -EBUSY;
|
|
oper_cfg.vpss_regs_base2 = ioremap(VPSS_CLK_CTRL, 4);
|
if (unlikely(!oper_cfg.vpss_regs_base2)) {
|
ret = -ENOMEM;
|
goto err_ioremap;
|
}
|
|
writel(VPSS_CLK_CTRL_VENCCLKEN |
|
VPSS_CLK_CTRL_DACCLKEN, oper_cfg.vpss_regs_base2);
|
|
ret = platform_driver_register(&vpss_driver);
|
if (ret)
|
goto err_pd_register;
|
|
return 0;
|
|
err_pd_register:
|
iounmap(oper_cfg.vpss_regs_base2);
|
err_ioremap:
|
release_mem_region(VPSS_CLK_CTRL, 4);
|
return ret;
|
}
|
subsys_initcall(vpss_init);
|
module_exit(vpss_exit);
|
