/*
|
* vpif - Video Port Interface driver
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* VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
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* that receiving video byte stream and two channels(2, 3) for video output.
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* The hardware supports SDTV, HDTV formats, raw data capture.
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* Currently, the driver supports NTSC and PAL standards.
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*
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* Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed .as is. WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spinlock.h>
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#include <linux/v4l2-dv-timings.h>
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#include <linux/of_graph.h>
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#include "vpif.h"
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MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");
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MODULE_LICENSE("GPL");
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#define VPIF_DRIVER_NAME "vpif"
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MODULE_ALIAS("platform:" VPIF_DRIVER_NAME);
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|
#define VPIF_CH0_MAX_MODES 22
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#define VPIF_CH1_MAX_MODES 2
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#define VPIF_CH2_MAX_MODES 15
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#define VPIF_CH3_MAX_MODES 2
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spinlock_t vpif_lock;
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EXPORT_SYMBOL_GPL(vpif_lock);
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void __iomem *vpif_base;
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EXPORT_SYMBOL_GPL(vpif_base);
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/*
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* vpif_ch_params: video standard configuration parameters for vpif
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*
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* The table must include all presets from supported subdevices.
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*/
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const struct vpif_channel_config_params vpif_ch_params[] = {
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/* HDTV formats */
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{
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.name = "480p59_94",
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.width = 720,
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.height = 480,
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.frm_fmt = 1,
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.ycmux_mode = 0,
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.eav2sav = 138-8,
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.sav2eav = 720,
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.l1 = 1,
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.l3 = 43,
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.l5 = 523,
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.vsize = 525,
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.capture_format = 0,
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.vbi_supported = 0,
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.hd_sd = 1,
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.dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
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},
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{
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.name = "576p50",
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.width = 720,
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.height = 576,
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.frm_fmt = 1,
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.ycmux_mode = 0,
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.eav2sav = 144-8,
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.sav2eav = 720,
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.l1 = 1,
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.l3 = 45,
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.l5 = 621,
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.vsize = 625,
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.capture_format = 0,
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.vbi_supported = 0,
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.hd_sd = 1,
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.dv_timings = V4L2_DV_BT_CEA_720X576P50,
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},
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{
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.name = "720p50",
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.width = 1280,
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.height = 720,
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.frm_fmt = 1,
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.ycmux_mode = 0,
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.eav2sav = 700-8,
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.sav2eav = 1280,
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.l1 = 1,
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.l3 = 26,
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.l5 = 746,
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.vsize = 750,
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.capture_format = 0,
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.vbi_supported = 0,
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.hd_sd = 1,
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.dv_timings = V4L2_DV_BT_CEA_1280X720P50,
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},
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{
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.name = "720p60",
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.width = 1280,
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.height = 720,
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.frm_fmt = 1,
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.ycmux_mode = 0,
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.eav2sav = 370 - 8,
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.sav2eav = 1280,
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.l1 = 1,
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.l3 = 26,
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.l5 = 746,
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.vsize = 750,
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.capture_format = 0,
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.vbi_supported = 0,
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.hd_sd = 1,
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.dv_timings = V4L2_DV_BT_CEA_1280X720P60,
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},
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{
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.name = "1080I50",
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.width = 1920,
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.height = 1080,
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.frm_fmt = 0,
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.ycmux_mode = 0,
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.eav2sav = 720 - 8,
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.sav2eav = 1920,
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.l1 = 1,
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.l3 = 21,
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.l5 = 561,
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.l7 = 563,
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.l9 = 584,
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.l11 = 1124,
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.vsize = 1125,
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.capture_format = 0,
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.vbi_supported = 0,
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.hd_sd = 1,
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.dv_timings = V4L2_DV_BT_CEA_1920X1080I50,
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},
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{
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.name = "1080I60",
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.width = 1920,
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.height = 1080,
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.frm_fmt = 0,
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.ycmux_mode = 0,
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.eav2sav = 280 - 8,
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.sav2eav = 1920,
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.l1 = 1,
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.l3 = 21,
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.l5 = 561,
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.l7 = 563,
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.l9 = 584,
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.l11 = 1124,
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.vsize = 1125,
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.capture_format = 0,
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.vbi_supported = 0,
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.hd_sd = 1,
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.dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
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},
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{
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.name = "1080p60",
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.width = 1920,
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.height = 1080,
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.frm_fmt = 1,
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.ycmux_mode = 0,
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.eav2sav = 280 - 8,
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.sav2eav = 1920,
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.l1 = 1,
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.l3 = 42,
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.l5 = 1122,
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.vsize = 1125,
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.capture_format = 0,
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.vbi_supported = 0,
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.hd_sd = 1,
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.dv_timings = V4L2_DV_BT_CEA_1920X1080P60,
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},
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/* SDTV formats */
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{
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.name = "NTSC_M",
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.width = 720,
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.height = 480,
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.frm_fmt = 0,
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.ycmux_mode = 1,
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.eav2sav = 268,
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.sav2eav = 1440,
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.l1 = 1,
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.l3 = 23,
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.l5 = 263,
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.l7 = 266,
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.l9 = 286,
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.l11 = 525,
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.vsize = 525,
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.capture_format = 0,
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.vbi_supported = 1,
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.hd_sd = 0,
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.stdid = V4L2_STD_525_60,
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},
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{
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.name = "PAL_BDGHIK",
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.width = 720,
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.height = 576,
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.frm_fmt = 0,
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.ycmux_mode = 1,
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.eav2sav = 280,
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.sav2eav = 1440,
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.l1 = 1,
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.l3 = 23,
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.l5 = 311,
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.l7 = 313,
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.l9 = 336,
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.l11 = 624,
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.vsize = 625,
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.capture_format = 0,
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.vbi_supported = 1,
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.hd_sd = 0,
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.stdid = V4L2_STD_625_50,
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},
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};
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EXPORT_SYMBOL_GPL(vpif_ch_params);
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const unsigned int vpif_ch_params_count = ARRAY_SIZE(vpif_ch_params);
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EXPORT_SYMBOL_GPL(vpif_ch_params_count);
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static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val)
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{
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if (val)
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vpif_set_bit(reg, bit);
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else
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vpif_clr_bit(reg, bit);
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}
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/* This structure is used to keep track of VPIF size register's offsets */
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struct vpif_registers {
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u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl;
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u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt;
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u32 vanc1_size, width_mask, len_mask;
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u8 max_modes;
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};
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static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = {
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/* Channel0 */
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{
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VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01,
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VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL,
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VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
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VPIF_CH0_MAX_MODES,
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},
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/* Channel1 */
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{
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VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01,
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VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL,
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VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
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VPIF_CH1_MAX_MODES,
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},
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/* Channel2 */
|
{
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VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01,
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VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL,
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VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE,
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VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF,
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VPIF_CH2_MAX_MODES
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},
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/* Channel3 */
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{
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VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01,
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VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL,
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VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE,
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VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF,
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VPIF_CH3_MAX_MODES
|
},
|
};
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/* vpif_set_mode_info:
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* This function is used to set horizontal and vertical config parameters
|
* As per the standard in the channel, configure the values of L1, L3,
|
* L5, L7 L9, L11 in VPIF Register , also write width and height
|
*/
|
static void vpif_set_mode_info(const struct vpif_channel_config_params *config,
|
u8 channel_id, u8 config_channel_id)
|
{
|
u32 value;
|
|
value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
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value <<= VPIF_CH_LEN_SHIFT;
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value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);
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regw(value, vpifregs[channel_id].h_cfg);
|
|
value = (config->l1 & vpifregs[config_channel_id].len_mask);
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value <<= VPIF_CH_LEN_SHIFT;
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value |= (config->l3 & vpifregs[config_channel_id].len_mask);
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regw(value, vpifregs[channel_id].v_cfg_00);
|
|
value = (config->l5 & vpifregs[config_channel_id].len_mask);
|
value <<= VPIF_CH_LEN_SHIFT;
|
value |= (config->l7 & vpifregs[config_channel_id].len_mask);
|
regw(value, vpifregs[channel_id].v_cfg_01);
|
|
value = (config->l9 & vpifregs[config_channel_id].len_mask);
|
value <<= VPIF_CH_LEN_SHIFT;
|
value |= (config->l11 & vpifregs[config_channel_id].len_mask);
|
regw(value, vpifregs[channel_id].v_cfg_02);
|
|
value = (config->vsize & vpifregs[config_channel_id].len_mask);
|
regw(value, vpifregs[channel_id].v_cfg);
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}
|
|
/* config_vpif_params
|
* Function to set the parameters of a channel
|
* Mainly modifies the channel ciontrol register
|
* It sets frame format, yc mux mode
|
*/
|
static void config_vpif_params(struct vpif_params *vpifparams,
|
u8 channel_id, u8 found)
|
{
|
const struct vpif_channel_config_params *config = &vpifparams->std_info;
|
u32 value, ch_nip, reg;
|
u8 start, end;
|
int i;
|
|
start = channel_id;
|
end = channel_id + found;
|
|
for (i = start; i < end; i++) {
|
reg = vpifregs[i].ch_ctrl;
|
if (channel_id < 2)
|
ch_nip = VPIF_CAPTURE_CH_NIP;
|
else
|
ch_nip = VPIF_DISPLAY_CH_NIP;
|
|
vpif_wr_bit(reg, ch_nip, config->frm_fmt);
|
vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);
|
vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,
|
vpifparams->video_params.storage_mode);
|
|
/* Set raster scanning SDR Format */
|
vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);
|
vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);
|
|
if (channel_id > 1) /* Set the Pixel enable bit */
|
vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);
|
else if (config->capture_format) {
|
/* Set the polarity of various pins */
|
vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,
|
vpifparams->iface.fid_pol);
|
vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,
|
vpifparams->iface.vd_pol);
|
vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,
|
vpifparams->iface.hd_pol);
|
|
value = regr(reg);
|
/* Set data width */
|
value &= ~(0x3u <<
|
VPIF_CH_DATA_WIDTH_BIT);
|
value |= ((vpifparams->params.data_sz) <<
|
VPIF_CH_DATA_WIDTH_BIT);
|
regw(value, reg);
|
}
|
|
/* Write the pitch in the driver */
|
regw((vpifparams->video_params.hpitch),
|
vpifregs[i].line_offset);
|
}
|
}
|
|
/* vpif_set_video_params
|
* This function is used to set video parameters in VPIF register
|
*/
|
int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)
|
{
|
const struct vpif_channel_config_params *config = &vpifparams->std_info;
|
int found = 1;
|
|
vpif_set_mode_info(config, channel_id, channel_id);
|
if (!config->ycmux_mode) {
|
/* YC are on separate channels (HDTV formats) */
|
vpif_set_mode_info(config, channel_id + 1, channel_id);
|
found = 2;
|
}
|
|
config_vpif_params(vpifparams, channel_id, found);
|
|
regw(0x80, VPIF_REQ_SIZE);
|
regw(0x01, VPIF_EMULATION_CTRL);
|
|
return found;
|
}
|
EXPORT_SYMBOL(vpif_set_video_params);
|
|
void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
|
u8 channel_id)
|
{
|
u32 value;
|
|
value = 0x3F8 & (vbiparams->hstart0);
|
value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
|
regw(value, vpifregs[channel_id].vanc0_strt);
|
|
value = 0x3F8 & (vbiparams->hstart1);
|
value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
|
regw(value, vpifregs[channel_id].vanc1_strt);
|
|
value = 0x3F8 & (vbiparams->hsize0);
|
value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
|
regw(value, vpifregs[channel_id].vanc0_size);
|
|
value = 0x3F8 & (vbiparams->hsize1);
|
value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
|
regw(value, vpifregs[channel_id].vanc1_size);
|
|
}
|
EXPORT_SYMBOL(vpif_set_vbi_display_params);
|
|
int vpif_channel_getfid(u8 channel_id)
|
{
|
return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)
|
>> VPIF_CH_FID_SHIFT;
|
}
|
EXPORT_SYMBOL(vpif_channel_getfid);
|
|
static int vpif_probe(struct platform_device *pdev)
|
{
|
static struct resource *res, *res_irq;
|
struct platform_device *pdev_capture, *pdev_display;
|
struct device_node *endpoint = NULL;
|
int ret;
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
vpif_base = devm_ioremap_resource(&pdev->dev, res);
|
if (IS_ERR(vpif_base))
|
return PTR_ERR(vpif_base);
|
|
pm_runtime_enable(&pdev->dev);
|
pm_runtime_get(&pdev->dev);
|
|
spin_lock_init(&vpif_lock);
|
dev_info(&pdev->dev, "vpif probe success\n");
|
|
/*
|
* If VPIF Node has endpoints, assume "new" DT support,
|
* where capture and display drivers don't have DT nodes
|
* so their devices need to be registered manually here
|
* for their legacy platform_drivers to work.
|
*/
|
endpoint = of_graph_get_next_endpoint(pdev->dev.of_node,
|
endpoint);
|
if (!endpoint)
|
return 0;
|
|
/*
|
* For DT platforms, manually create platform_devices for
|
* capture/display drivers.
|
*/
|
res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
if (!res_irq) {
|
dev_warn(&pdev->dev, "Missing IRQ resource.\n");
|
ret = -EINVAL;
|
goto err_put_rpm;
|
}
|
|
pdev_capture = devm_kzalloc(&pdev->dev, sizeof(*pdev_capture),
|
GFP_KERNEL);
|
if (pdev_capture) {
|
pdev_capture->name = "vpif_capture";
|
pdev_capture->id = -1;
|
pdev_capture->resource = res_irq;
|
pdev_capture->num_resources = 1;
|
pdev_capture->dev.dma_mask = pdev->dev.dma_mask;
|
pdev_capture->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask;
|
pdev_capture->dev.parent = &pdev->dev;
|
platform_device_register(pdev_capture);
|
} else {
|
dev_warn(&pdev->dev, "Unable to allocate memory for pdev_capture.\n");
|
}
|
|
pdev_display = devm_kzalloc(&pdev->dev, sizeof(*pdev_display),
|
GFP_KERNEL);
|
if (pdev_display) {
|
pdev_display->name = "vpif_display";
|
pdev_display->id = -1;
|
pdev_display->resource = res_irq;
|
pdev_display->num_resources = 1;
|
pdev_display->dev.dma_mask = pdev->dev.dma_mask;
|
pdev_display->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask;
|
pdev_display->dev.parent = &pdev->dev;
|
platform_device_register(pdev_display);
|
} else {
|
dev_warn(&pdev->dev, "Unable to allocate memory for pdev_display.\n");
|
}
|
|
return 0;
|
|
err_put_rpm:
|
pm_runtime_put(&pdev->dev);
|
pm_runtime_disable(&pdev->dev);
|
|
return ret;
|
}
|
|
static int vpif_remove(struct platform_device *pdev)
|
{
|
pm_runtime_put(&pdev->dev);
|
pm_runtime_disable(&pdev->dev);
|
return 0;
|
}
|
|
#ifdef CONFIG_PM
|
static int vpif_suspend(struct device *dev)
|
{
|
pm_runtime_put(dev);
|
return 0;
|
}
|
|
static int vpif_resume(struct device *dev)
|
{
|
pm_runtime_get(dev);
|
return 0;
|
}
|
|
static const struct dev_pm_ops vpif_pm = {
|
.suspend = vpif_suspend,
|
.resume = vpif_resume,
|
};
|
|
#define vpif_pm_ops (&vpif_pm)
|
#else
|
#define vpif_pm_ops NULL
|
#endif
|
|
#if IS_ENABLED(CONFIG_OF)
|
static const struct of_device_id vpif_of_match[] = {
|
{ .compatible = "ti,da850-vpif", },
|
{ /* sentinel */ },
|
};
|
MODULE_DEVICE_TABLE(of, vpif_of_match);
|
#endif
|
|
static struct platform_driver vpif_driver = {
|
.driver = {
|
.of_match_table = of_match_ptr(vpif_of_match),
|
.name = VPIF_DRIVER_NAME,
|
.pm = vpif_pm_ops,
|
},
|
.remove = vpif_remove,
|
.probe = vpif_probe,
|
};
|
|
static void vpif_exit(void)
|
{
|
platform_driver_unregister(&vpif_driver);
|
}
|
|
static int __init vpif_init(void)
|
{
|
return platform_driver_register(&vpif_driver);
|
}
|
subsys_initcall(vpif_init);
|
module_exit(vpif_exit);
|
