// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2005-2009 Texas Instruments Inc
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*
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* CCDC hardware module for DM355
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* ------------------------------
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*
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* This module is for configuring DM355 CCD controller of VPFE to capture
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* Raw yuv or Bayer RGB data from a decoder. CCDC has several modules
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* such as Defect Pixel Correction, Color Space Conversion etc to
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* pre-process the Bayer RGB data, before writing it to SDRAM.
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*
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* TODO: 1) Raw bayer parameter settings and bayer capture
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* 2) Split module parameter structure to module specific ioctl structs
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* 3) add support for lense shading correction
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* 4) investigate if enum used for user space type definition
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* to be replaced by #defines or integer
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*/
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#include <linux/platform_device.h>
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#include <linux/uaccess.h>
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#include <linux/videodev2.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <media/davinci/dm355_ccdc.h>
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#include <media/davinci/vpss.h>
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#include "dm355_ccdc_regs.h"
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#include "ccdc_hw_device.h"
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("CCDC Driver for DM355");
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MODULE_AUTHOR("Texas Instruments");
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static struct ccdc_oper_config {
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struct device *dev;
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/* CCDC interface type */
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enum vpfe_hw_if_type if_type;
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/* Raw Bayer configuration */
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struct ccdc_params_raw bayer;
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/* YCbCr configuration */
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struct ccdc_params_ycbcr ycbcr;
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/* ccdc base address */
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void __iomem *base_addr;
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} ccdc_cfg = {
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/* Raw configurations */
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.bayer = {
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.pix_fmt = CCDC_PIXFMT_RAW,
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.frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
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.win = CCDC_WIN_VGA,
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.fid_pol = VPFE_PINPOL_POSITIVE,
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.vd_pol = VPFE_PINPOL_POSITIVE,
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.hd_pol = VPFE_PINPOL_POSITIVE,
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.gain = {
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.r_ye = 256,
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.gb_g = 256,
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.gr_cy = 256,
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.b_mg = 256
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},
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.config_params = {
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.datasft = 2,
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.mfilt1 = CCDC_NO_MEDIAN_FILTER1,
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.mfilt2 = CCDC_NO_MEDIAN_FILTER2,
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.alaw = {
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.gamma_wd = 2,
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},
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.blk_clamp = {
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.sample_pixel = 1,
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.dc_sub = 25
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},
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.col_pat_field0 = {
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.olop = CCDC_GREEN_BLUE,
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.olep = CCDC_BLUE,
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.elop = CCDC_RED,
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.elep = CCDC_GREEN_RED
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},
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.col_pat_field1 = {
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.olop = CCDC_GREEN_BLUE,
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.olep = CCDC_BLUE,
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.elop = CCDC_RED,
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.elep = CCDC_GREEN_RED
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},
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},
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},
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/* YCbCr configuration */
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.ycbcr = {
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.win = CCDC_WIN_PAL,
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.pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
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.frm_fmt = CCDC_FRMFMT_INTERLACED,
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.fid_pol = VPFE_PINPOL_POSITIVE,
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.vd_pol = VPFE_PINPOL_POSITIVE,
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.hd_pol = VPFE_PINPOL_POSITIVE,
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.bt656_enable = 1,
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.pix_order = CCDC_PIXORDER_CBYCRY,
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.buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED
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},
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};
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/* Raw Bayer formats */
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static u32 ccdc_raw_bayer_pix_formats[] =
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{V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
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/* Raw YUV formats */
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static u32 ccdc_raw_yuv_pix_formats[] =
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{V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
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/* register access routines */
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static inline u32 regr(u32 offset)
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{
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return __raw_readl(ccdc_cfg.base_addr + offset);
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}
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static inline void regw(u32 val, u32 offset)
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{
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__raw_writel(val, ccdc_cfg.base_addr + offset);
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}
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static void ccdc_enable(int en)
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{
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unsigned int temp;
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temp = regr(SYNCEN);
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temp &= (~CCDC_SYNCEN_VDHDEN_MASK);
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temp |= (en & CCDC_SYNCEN_VDHDEN_MASK);
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regw(temp, SYNCEN);
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}
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static void ccdc_enable_output_to_sdram(int en)
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{
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unsigned int temp;
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temp = regr(SYNCEN);
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temp &= (~(CCDC_SYNCEN_WEN_MASK));
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temp |= ((en << CCDC_SYNCEN_WEN_SHIFT) & CCDC_SYNCEN_WEN_MASK);
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regw(temp, SYNCEN);
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}
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static void ccdc_config_gain_offset(void)
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{
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/* configure gain */
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regw(ccdc_cfg.bayer.gain.r_ye, RYEGAIN);
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regw(ccdc_cfg.bayer.gain.gr_cy, GRCYGAIN);
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regw(ccdc_cfg.bayer.gain.gb_g, GBGGAIN);
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regw(ccdc_cfg.bayer.gain.b_mg, BMGGAIN);
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/* configure offset */
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regw(ccdc_cfg.bayer.ccdc_offset, OFFSET);
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}
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/*
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* ccdc_restore_defaults()
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* This function restore power on defaults in the ccdc registers
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*/
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static int ccdc_restore_defaults(void)
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{
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int i;
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dev_dbg(ccdc_cfg.dev, "\nstarting ccdc_restore_defaults...");
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/* set all registers to zero */
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for (i = 0; i <= CCDC_REG_LAST; i += 4)
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regw(0, i);
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/* now override the values with power on defaults in registers */
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regw(MODESET_DEFAULT, MODESET);
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/* no culling support */
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regw(CULH_DEFAULT, CULH);
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regw(CULV_DEFAULT, CULV);
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/* Set default Gain and Offset */
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ccdc_cfg.bayer.gain.r_ye = GAIN_DEFAULT;
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ccdc_cfg.bayer.gain.gb_g = GAIN_DEFAULT;
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ccdc_cfg.bayer.gain.gr_cy = GAIN_DEFAULT;
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ccdc_cfg.bayer.gain.b_mg = GAIN_DEFAULT;
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ccdc_config_gain_offset();
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regw(OUTCLIP_DEFAULT, OUTCLIP);
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regw(LSCCFG2_DEFAULT, LSCCFG2);
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/* select ccdc input */
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if (vpss_select_ccdc_source(VPSS_CCDCIN)) {
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dev_dbg(ccdc_cfg.dev, "\ncouldn't select ccdc input source");
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return -EFAULT;
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}
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/* select ccdc clock */
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if (vpss_enable_clock(VPSS_CCDC_CLOCK, 1) < 0) {
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dev_dbg(ccdc_cfg.dev, "\ncouldn't enable ccdc clock");
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return -EFAULT;
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}
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dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_restore_defaults...");
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return 0;
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}
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static int ccdc_open(struct device *device)
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{
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return ccdc_restore_defaults();
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}
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static int ccdc_close(struct device *device)
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{
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/* disable clock */
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vpss_enable_clock(VPSS_CCDC_CLOCK, 0);
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/* do nothing for now */
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return 0;
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}
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/*
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* ccdc_setwin()
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* This function will configure the window size to
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* be capture in CCDC reg.
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*/
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static void ccdc_setwin(struct v4l2_rect *image_win,
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enum ccdc_frmfmt frm_fmt, int ppc)
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{
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int horz_start, horz_nr_pixels;
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int vert_start, vert_nr_lines;
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int mid_img = 0;
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dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_setwin...");
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/*
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* ppc - per pixel count. indicates how many pixels per cell
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* output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
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* raw capture this is 1
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*/
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horz_start = image_win->left << (ppc - 1);
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horz_nr_pixels = ((image_win->width) << (ppc - 1)) - 1;
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/* Writing the horizontal info into the registers */
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regw(horz_start, SPH);
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regw(horz_nr_pixels, NPH);
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vert_start = image_win->top;
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if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
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vert_nr_lines = (image_win->height >> 1) - 1;
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vert_start >>= 1;
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/* Since first line doesn't have any data */
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vert_start += 1;
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/* configure VDINT0 and VDINT1 */
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regw(vert_start, VDINT0);
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} else {
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/* Since first line doesn't have any data */
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vert_start += 1;
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vert_nr_lines = image_win->height - 1;
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/* configure VDINT0 and VDINT1 */
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mid_img = vert_start + (image_win->height / 2);
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regw(vert_start, VDINT0);
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regw(mid_img, VDINT1);
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}
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regw(vert_start & CCDC_START_VER_ONE_MASK, SLV0);
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regw(vert_start & CCDC_START_VER_TWO_MASK, SLV1);
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regw(vert_nr_lines & CCDC_NUM_LINES_VER, NLV);
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dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_setwin...");
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}
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/* This function will configure CCDC for YCbCr video capture */
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static void ccdc_config_ycbcr(void)
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{
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struct ccdc_params_ycbcr *params = &ccdc_cfg.ycbcr;
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u32 temp;
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/* first set the CCDC power on defaults values in all registers */
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dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_ycbcr...");
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ccdc_restore_defaults();
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/* configure pixel format & video frame format */
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temp = (((params->pix_fmt & CCDC_INPUT_MODE_MASK) <<
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CCDC_INPUT_MODE_SHIFT) |
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((params->frm_fmt & CCDC_FRM_FMT_MASK) <<
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CCDC_FRM_FMT_SHIFT));
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/* setup BT.656 sync mode */
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if (params->bt656_enable) {
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regw(CCDC_REC656IF_BT656_EN, REC656IF);
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/*
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* configure the FID, VD, HD pin polarity fld,hd pol positive,
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* vd negative, 8-bit pack mode
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*/
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temp |= CCDC_VD_POL_NEGATIVE;
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} else { /* y/c external sync mode */
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temp |= (((params->fid_pol & CCDC_FID_POL_MASK) <<
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CCDC_FID_POL_SHIFT) |
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((params->hd_pol & CCDC_HD_POL_MASK) <<
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CCDC_HD_POL_SHIFT) |
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((params->vd_pol & CCDC_VD_POL_MASK) <<
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CCDC_VD_POL_SHIFT));
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}
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/* pack the data to 8-bit */
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temp |= CCDC_DATA_PACK_ENABLE;
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regw(temp, MODESET);
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/* configure video window */
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ccdc_setwin(¶ms->win, params->frm_fmt, 2);
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/* configure the order of y cb cr in SD-RAM */
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temp = (params->pix_order << CCDC_Y8POS_SHIFT);
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temp |= CCDC_LATCH_ON_VSYNC_DISABLE | CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC;
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regw(temp, CCDCFG);
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/*
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* configure the horizontal line offset. This is done by rounding up
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* width to a multiple of 16 pixels and multiply by two to account for
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* y:cb:cr 4:2:2 data
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*/
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regw(((params->win.width * 2 + 31) >> 5), HSIZE);
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/* configure the memory line offset */
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if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED) {
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/* two fields are interleaved in memory */
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regw(CCDC_SDOFST_FIELD_INTERLEAVED, SDOFST);
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}
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dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_config_ycbcr...\n");
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}
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/*
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* ccdc_config_black_clamp()
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* configure parameters for Optical Black Clamp
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*/
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static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp)
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{
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u32 val;
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if (!bclamp->b_clamp_enable) {
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/* configure DCSub */
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regw(bclamp->dc_sub & CCDC_BLK_DC_SUB_MASK, DCSUB);
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regw(0x0000, CLAMP);
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return;
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}
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/* Enable the Black clamping, set sample lines and pixels */
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val = (bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) |
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((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) <<
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CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE;
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regw(val, CLAMP);
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/* If Black clamping is enable then make dcsub 0 */
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val = (bclamp->sample_ln & CCDC_NUM_LINE_CALC_MASK)
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<< CCDC_NUM_LINE_CALC_SHIFT;
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regw(val, DCSUB);
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}
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/*
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* ccdc_config_black_compense()
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* configure parameters for Black Compensation
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*/
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static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp)
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{
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u32 val;
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val = (bcomp->b & CCDC_BLK_COMP_MASK) |
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((bcomp->gb & CCDC_BLK_COMP_MASK) <<
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CCDC_BLK_COMP_GB_COMP_SHIFT);
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regw(val, BLKCMP1);
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val = ((bcomp->gr & CCDC_BLK_COMP_MASK) <<
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CCDC_BLK_COMP_GR_COMP_SHIFT) |
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((bcomp->r & CCDC_BLK_COMP_MASK) <<
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CCDC_BLK_COMP_R_COMP_SHIFT);
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regw(val, BLKCMP0);
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}
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/*
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* ccdc_write_dfc_entry()
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* write an entry in the dfc table.
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*/
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static int ccdc_write_dfc_entry(int index, struct ccdc_vertical_dft *dfc)
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{
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/* TODO This is to be re-visited and adjusted */
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#define DFC_WRITE_WAIT_COUNT 1000
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u32 val, count = DFC_WRITE_WAIT_COUNT;
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regw(dfc->dft_corr_vert[index], DFCMEM0);
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regw(dfc->dft_corr_horz[index], DFCMEM1);
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regw(dfc->dft_corr_sub1[index], DFCMEM2);
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regw(dfc->dft_corr_sub2[index], DFCMEM3);
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regw(dfc->dft_corr_sub3[index], DFCMEM4);
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/* set WR bit to write */
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val = regr(DFCMEMCTL) | CCDC_DFCMEMCTL_DFCMWR_MASK;
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regw(val, DFCMEMCTL);
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/*
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* Assume, it is very short. If we get an error, we need to
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* adjust this value
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*/
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while (regr(DFCMEMCTL) & CCDC_DFCMEMCTL_DFCMWR_MASK)
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count--;
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/*
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* TODO We expect the count to be non-zero to be successful. Adjust
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* the count if write requires more time
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*/
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if (count) {
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dev_err(ccdc_cfg.dev, "defect table write timeout !!!\n");
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return -1;
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}
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return 0;
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}
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/*
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* ccdc_config_vdfc()
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* configure parameters for Vertical Defect Correction
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*/
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static int ccdc_config_vdfc(struct ccdc_vertical_dft *dfc)
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{
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u32 val;
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int i;
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/* Configure General Defect Correction. The table used is from IPIPE */
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val = dfc->gen_dft_en & CCDC_DFCCTL_GDFCEN_MASK;
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/* Configure Vertical Defect Correction if needed */
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if (!dfc->ver_dft_en) {
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/* Enable only General Defect Correction */
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regw(val, DFCCTL);
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return 0;
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}
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if (dfc->table_size > CCDC_DFT_TABLE_SIZE)
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return -EINVAL;
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val |= CCDC_DFCCTL_VDFC_DISABLE;
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val |= (dfc->dft_corr_ctl.vdfcsl & CCDC_DFCCTL_VDFCSL_MASK) <<
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CCDC_DFCCTL_VDFCSL_SHIFT;
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val |= (dfc->dft_corr_ctl.vdfcuda & CCDC_DFCCTL_VDFCUDA_MASK) <<
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CCDC_DFCCTL_VDFCUDA_SHIFT;
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val |= (dfc->dft_corr_ctl.vdflsft & CCDC_DFCCTL_VDFLSFT_MASK) <<
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CCDC_DFCCTL_VDFLSFT_SHIFT;
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regw(val , DFCCTL);
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/* clear address ptr to offset 0 */
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val = CCDC_DFCMEMCTL_DFCMARST_MASK << CCDC_DFCMEMCTL_DFCMARST_SHIFT;
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/* write defect table entries */
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for (i = 0; i < dfc->table_size; i++) {
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/* increment address for non zero index */
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if (i != 0)
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val = CCDC_DFCMEMCTL_INC_ADDR;
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regw(val, DFCMEMCTL);
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if (ccdc_write_dfc_entry(i, dfc) < 0)
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return -EFAULT;
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}
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/* update saturation level and enable dfc */
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regw(dfc->saturation_ctl & CCDC_VDC_DFCVSAT_MASK, DFCVSAT);
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val = regr(DFCCTL) | (CCDC_DFCCTL_VDFCEN_MASK <<
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CCDC_DFCCTL_VDFCEN_SHIFT);
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regw(val, DFCCTL);
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return 0;
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}
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/*
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* ccdc_config_csc()
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* configure parameters for color space conversion
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* Each register CSCM0-7 has two values in S8Q5 format.
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*/
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static void ccdc_config_csc(struct ccdc_csc *csc)
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{
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u32 val1 = 0, val2;
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int i;
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if (!csc->enable)
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return;
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/* Enable the CSC sub-module */
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regw(CCDC_CSC_ENABLE, CSCCTL);
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/* Converting the co-eff as per the format of the register */
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for (i = 0; i < CCDC_CSC_COEFF_TABLE_SIZE; i++) {
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if ((i % 2) == 0) {
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/* CSCM - LSB */
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val1 = (csc->coeff[i].integer &
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CCDC_CSC_COEF_INTEG_MASK)
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<< CCDC_CSC_COEF_INTEG_SHIFT;
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/*
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* convert decimal part to binary. Use 2 decimal
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* precision, user values range from .00 - 0.99
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*/
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val1 |= (((csc->coeff[i].decimal &
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CCDC_CSC_COEF_DECIMAL_MASK) *
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CCDC_CSC_DEC_MAX) / 100);
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} else {
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/* CSCM - MSB */
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val2 = (csc->coeff[i].integer &
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CCDC_CSC_COEF_INTEG_MASK)
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<< CCDC_CSC_COEF_INTEG_SHIFT;
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val2 |= (((csc->coeff[i].decimal &
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CCDC_CSC_COEF_DECIMAL_MASK) *
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CCDC_CSC_DEC_MAX) / 100);
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val2 <<= CCDC_CSCM_MSB_SHIFT;
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val2 |= val1;
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regw(val2, (CSCM0 + ((i - 1) << 1)));
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}
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}
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}
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/*
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* ccdc_config_color_patterns()
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* configure parameters for color patterns
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*/
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static void ccdc_config_color_patterns(struct ccdc_col_pat *pat0,
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struct ccdc_col_pat *pat1)
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{
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u32 val;
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val = (pat0->olop | (pat0->olep << 2) | (pat0->elop << 4) |
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(pat0->elep << 6) | (pat1->olop << 8) | (pat1->olep << 10) |
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(pat1->elop << 12) | (pat1->elep << 14));
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regw(val, COLPTN);
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}
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/* This function will configure CCDC for Raw mode image capture */
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static int ccdc_config_raw(void)
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{
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struct ccdc_params_raw *params = &ccdc_cfg.bayer;
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struct ccdc_config_params_raw *config_params =
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&ccdc_cfg.bayer.config_params;
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unsigned int val;
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dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_raw...");
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/* restore power on defaults to register */
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ccdc_restore_defaults();
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/* CCDCFG register:
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* set CCD Not to swap input since input is RAW data
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* set FID detection function to Latch at V-Sync
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* set WENLOG - ccdc valid area to AND
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* set TRGSEL to WENBIT
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* set EXTRG to DISABLE
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* disable latching function on VSYNC - shadowed registers
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*/
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regw(CCDC_YCINSWP_RAW | CCDC_CCDCFG_FIDMD_LATCH_VSYNC |
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CCDC_CCDCFG_WENLOG_AND | CCDC_CCDCFG_TRGSEL_WEN |
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CCDC_CCDCFG_EXTRG_DISABLE | CCDC_LATCH_ON_VSYNC_DISABLE, CCDCFG);
|
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/*
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* Set VDHD direction to input, input type to raw input
|
* normal data polarity, do not use external WEN
|
*/
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val = (CCDC_VDHDOUT_INPUT | CCDC_RAW_IP_MODE | CCDC_DATAPOL_NORMAL |
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CCDC_EXWEN_DISABLE);
|
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/*
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* Configure the vertical sync polarity (MODESET.VDPOL), horizontal
|
* sync polarity (MODESET.HDPOL), field id polarity (MODESET.FLDPOL),
|
* frame format(progressive or interlace), & pixel format (Input mode)
|
*/
|
val |= (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) |
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((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) |
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((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) |
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((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) |
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((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT));
|
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/* set pack for alaw compression */
|
if ((config_params->data_sz == CCDC_DATA_8BITS) ||
|
config_params->alaw.enable)
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val |= CCDC_DATA_PACK_ENABLE;
|
|
/* Configure for LPF */
|
if (config_params->lpf_enable)
|
val |= (config_params->lpf_enable & CCDC_LPF_MASK) <<
|
CCDC_LPF_SHIFT;
|
|
/* Configure the data shift */
|
val |= (config_params->datasft & CCDC_DATASFT_MASK) <<
|
CCDC_DATASFT_SHIFT;
|
regw(val , MODESET);
|
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to MODESET...\n", val);
|
|
/* Configure the Median Filter threshold */
|
regw((config_params->med_filt_thres) & CCDC_MED_FILT_THRESH, MEDFILT);
|
|
/* Configure GAMMAWD register. defaur 11-2, and Mosaic cfa pattern */
|
val = CCDC_GAMMA_BITS_11_2 << CCDC_GAMMAWD_INPUT_SHIFT |
|
CCDC_CFA_MOSAIC;
|
|
/* Enable and configure aLaw register if needed */
|
if (config_params->alaw.enable) {
|
val |= (CCDC_ALAW_ENABLE |
|
((config_params->alaw.gamma_wd &
|
CCDC_ALAW_GAMMA_WD_MASK) <<
|
CCDC_GAMMAWD_INPUT_SHIFT));
|
}
|
|
/* Configure Median filter1 & filter2 */
|
val |= ((config_params->mfilt1 << CCDC_MFILT1_SHIFT) |
|
(config_params->mfilt2 << CCDC_MFILT2_SHIFT));
|
|
regw(val, GAMMAWD);
|
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to GAMMAWD...\n", val);
|
|
/* configure video window */
|
ccdc_setwin(¶ms->win, params->frm_fmt, 1);
|
|
/* Optical Clamp Averaging */
|
ccdc_config_black_clamp(&config_params->blk_clamp);
|
|
/* Black level compensation */
|
ccdc_config_black_compense(&config_params->blk_comp);
|
|
/* Vertical Defect Correction if needed */
|
if (ccdc_config_vdfc(&config_params->vertical_dft) < 0)
|
return -EFAULT;
|
|
/* color space conversion */
|
ccdc_config_csc(&config_params->csc);
|
|
/* color pattern */
|
ccdc_config_color_patterns(&config_params->col_pat_field0,
|
&config_params->col_pat_field1);
|
|
/* Configure the Gain & offset control */
|
ccdc_config_gain_offset();
|
|
dev_dbg(ccdc_cfg.dev, "\nWriting %x to COLPTN...\n", val);
|
|
/* Configure DATAOFST register */
|
val = (config_params->data_offset.horz_offset & CCDC_DATAOFST_MASK) <<
|
CCDC_DATAOFST_H_SHIFT;
|
val |= (config_params->data_offset.vert_offset & CCDC_DATAOFST_MASK) <<
|
CCDC_DATAOFST_V_SHIFT;
|
regw(val, DATAOFST);
|
|
/* configuring HSIZE register */
|
val = (params->horz_flip_enable & CCDC_HSIZE_FLIP_MASK) <<
|
CCDC_HSIZE_FLIP_SHIFT;
|
|
/* If pack 8 is enable then 1 pixel will take 1 byte */
|
if ((config_params->data_sz == CCDC_DATA_8BITS) ||
|
config_params->alaw.enable) {
|
val |= (((params->win.width) + 31) >> 5) &
|
CCDC_HSIZE_VAL_MASK;
|
|
/* adjust to multiple of 32 */
|
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to HSIZE...\n",
|
(((params->win.width) + 31) >> 5) &
|
CCDC_HSIZE_VAL_MASK);
|
} else {
|
/* else one pixel will take 2 byte */
|
val |= (((params->win.width * 2) + 31) >> 5) &
|
CCDC_HSIZE_VAL_MASK;
|
|
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to HSIZE...\n",
|
(((params->win.width * 2) + 31) >> 5) &
|
CCDC_HSIZE_VAL_MASK);
|
}
|
regw(val, HSIZE);
|
|
/* Configure SDOFST register */
|
if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
|
if (params->image_invert_enable) {
|
/* For interlace inverse mode */
|
regw(CCDC_SDOFST_INTERLACE_INVERSE, SDOFST);
|
dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
|
CCDC_SDOFST_INTERLACE_INVERSE);
|
} else {
|
/* For interlace non inverse mode */
|
regw(CCDC_SDOFST_INTERLACE_NORMAL, SDOFST);
|
dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
|
CCDC_SDOFST_INTERLACE_NORMAL);
|
}
|
} else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
|
if (params->image_invert_enable) {
|
/* For progessive inverse mode */
|
regw(CCDC_SDOFST_PROGRESSIVE_INVERSE, SDOFST);
|
dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
|
CCDC_SDOFST_PROGRESSIVE_INVERSE);
|
} else {
|
/* For progessive non inverse mode */
|
regw(CCDC_SDOFST_PROGRESSIVE_NORMAL, SDOFST);
|
dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
|
CCDC_SDOFST_PROGRESSIVE_NORMAL);
|
}
|
}
|
dev_dbg(ccdc_cfg.dev, "\nend of ccdc_config_raw...");
|
return 0;
|
}
|
|
static int ccdc_configure(void)
|
{
|
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
|
return ccdc_config_raw();
|
else
|
ccdc_config_ycbcr();
|
return 0;
|
}
|
|
static int ccdc_set_buftype(enum ccdc_buftype buf_type)
|
{
|
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
|
ccdc_cfg.bayer.buf_type = buf_type;
|
else
|
ccdc_cfg.ycbcr.buf_type = buf_type;
|
return 0;
|
}
|
static enum ccdc_buftype ccdc_get_buftype(void)
|
{
|
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
|
return ccdc_cfg.bayer.buf_type;
|
return ccdc_cfg.ycbcr.buf_type;
|
}
|
|
static int ccdc_enum_pix(u32 *pix, int i)
|
{
|
int ret = -EINVAL;
|
if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
|
if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) {
|
*pix = ccdc_raw_bayer_pix_formats[i];
|
ret = 0;
|
}
|
} else {
|
if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) {
|
*pix = ccdc_raw_yuv_pix_formats[i];
|
ret = 0;
|
}
|
}
|
return ret;
|
}
|
|
static int ccdc_set_pixel_format(u32 pixfmt)
|
{
|
struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
|
|
if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
|
ccdc_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
|
if (pixfmt == V4L2_PIX_FMT_SBGGR8)
|
alaw->enable = 1;
|
else if (pixfmt != V4L2_PIX_FMT_SBGGR16)
|
return -EINVAL;
|
} else {
|
if (pixfmt == V4L2_PIX_FMT_YUYV)
|
ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
|
else if (pixfmt == V4L2_PIX_FMT_UYVY)
|
ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
|
else
|
return -EINVAL;
|
}
|
return 0;
|
}
|
static u32 ccdc_get_pixel_format(void)
|
{
|
struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
|
u32 pixfmt;
|
|
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
|
if (alaw->enable)
|
pixfmt = V4L2_PIX_FMT_SBGGR8;
|
else
|
pixfmt = V4L2_PIX_FMT_SBGGR16;
|
else {
|
if (ccdc_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
|
pixfmt = V4L2_PIX_FMT_YUYV;
|
else
|
pixfmt = V4L2_PIX_FMT_UYVY;
|
}
|
return pixfmt;
|
}
|
static int ccdc_set_image_window(struct v4l2_rect *win)
|
{
|
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
|
ccdc_cfg.bayer.win = *win;
|
else
|
ccdc_cfg.ycbcr.win = *win;
|
return 0;
|
}
|
|
static void ccdc_get_image_window(struct v4l2_rect *win)
|
{
|
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
|
*win = ccdc_cfg.bayer.win;
|
else
|
*win = ccdc_cfg.ycbcr.win;
|
}
|
|
static unsigned int ccdc_get_line_length(void)
|
{
|
struct ccdc_config_params_raw *config_params =
|
&ccdc_cfg.bayer.config_params;
|
unsigned int len;
|
|
if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
|
if ((config_params->alaw.enable) ||
|
(config_params->data_sz == CCDC_DATA_8BITS))
|
len = ccdc_cfg.bayer.win.width;
|
else
|
len = ccdc_cfg.bayer.win.width * 2;
|
} else
|
len = ccdc_cfg.ycbcr.win.width * 2;
|
return ALIGN(len, 32);
|
}
|
|
static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt)
|
{
|
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
|
ccdc_cfg.bayer.frm_fmt = frm_fmt;
|
else
|
ccdc_cfg.ycbcr.frm_fmt = frm_fmt;
|
return 0;
|
}
|
|
static enum ccdc_frmfmt ccdc_get_frame_format(void)
|
{
|
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
|
return ccdc_cfg.bayer.frm_fmt;
|
else
|
return ccdc_cfg.ycbcr.frm_fmt;
|
}
|
|
static int ccdc_getfid(void)
|
{
|
return (regr(MODESET) >> 15) & 1;
|
}
|
|
/* misc operations */
|
static inline void ccdc_setfbaddr(unsigned long addr)
|
{
|
regw((addr >> 21) & 0x007f, STADRH);
|
regw((addr >> 5) & 0x0ffff, STADRL);
|
}
|
|
static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params)
|
{
|
ccdc_cfg.if_type = params->if_type;
|
|
switch (params->if_type) {
|
case VPFE_BT656:
|
case VPFE_YCBCR_SYNC_16:
|
case VPFE_YCBCR_SYNC_8:
|
ccdc_cfg.ycbcr.vd_pol = params->vdpol;
|
ccdc_cfg.ycbcr.hd_pol = params->hdpol;
|
break;
|
default:
|
/* TODO add support for raw bayer here */
|
return -EINVAL;
|
}
|
return 0;
|
}
|
|
static const struct ccdc_hw_device ccdc_hw_dev = {
|
.name = "DM355 CCDC",
|
.owner = THIS_MODULE,
|
.hw_ops = {
|
.open = ccdc_open,
|
.close = ccdc_close,
|
.enable = ccdc_enable,
|
.enable_out_to_sdram = ccdc_enable_output_to_sdram,
|
.set_hw_if_params = ccdc_set_hw_if_params,
|
.configure = ccdc_configure,
|
.set_buftype = ccdc_set_buftype,
|
.get_buftype = ccdc_get_buftype,
|
.enum_pix = ccdc_enum_pix,
|
.set_pixel_format = ccdc_set_pixel_format,
|
.get_pixel_format = ccdc_get_pixel_format,
|
.set_frame_format = ccdc_set_frame_format,
|
.get_frame_format = ccdc_get_frame_format,
|
.set_image_window = ccdc_set_image_window,
|
.get_image_window = ccdc_get_image_window,
|
.get_line_length = ccdc_get_line_length,
|
.setfbaddr = ccdc_setfbaddr,
|
.getfid = ccdc_getfid,
|
},
|
};
|
|
static int dm355_ccdc_probe(struct platform_device *pdev)
|
{
|
void (*setup_pinmux)(void);
|
struct resource *res;
|
int status = 0;
|
|
/*
|
* first try to register with vpfe. If not correct platform, then we
|
* don't have to iomap
|
*/
|
status = vpfe_register_ccdc_device(&ccdc_hw_dev);
|
if (status < 0)
|
return status;
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
if (!res) {
|
status = -ENODEV;
|
goto fail_nores;
|
}
|
|
res = request_mem_region(res->start, resource_size(res), res->name);
|
if (!res) {
|
status = -EBUSY;
|
goto fail_nores;
|
}
|
|
ccdc_cfg.base_addr = ioremap(res->start, resource_size(res));
|
if (!ccdc_cfg.base_addr) {
|
status = -ENOMEM;
|
goto fail_nomem;
|
}
|
|
/* Platform data holds setup_pinmux function ptr */
|
if (NULL == pdev->dev.platform_data) {
|
status = -ENODEV;
|
goto fail_nomap;
|
}
|
setup_pinmux = pdev->dev.platform_data;
|
/*
|
* setup Mux configuration for ccdc which may be different for
|
* different SoCs using this CCDC
|
*/
|
setup_pinmux();
|
ccdc_cfg.dev = &pdev->dev;
|
printk(KERN_NOTICE "%s is registered with vpfe.\n", ccdc_hw_dev.name);
|
return 0;
|
fail_nomap:
|
iounmap(ccdc_cfg.base_addr);
|
fail_nomem:
|
release_mem_region(res->start, resource_size(res));
|
fail_nores:
|
vpfe_unregister_ccdc_device(&ccdc_hw_dev);
|
return status;
|
}
|
|
static int dm355_ccdc_remove(struct platform_device *pdev)
|
{
|
struct resource *res;
|
|
iounmap(ccdc_cfg.base_addr);
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
if (res)
|
release_mem_region(res->start, resource_size(res));
|
vpfe_unregister_ccdc_device(&ccdc_hw_dev);
|
return 0;
|
}
|
|
static struct platform_driver dm355_ccdc_driver = {
|
.driver = {
|
.name = "dm355_ccdc",
|
},
|
.remove = dm355_ccdc_remove,
|
.probe = dm355_ccdc_probe,
|
};
|
|
module_platform_driver(dm355_ccdc_driver);
|
