// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
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*
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* Based on original driver by Krzysztof Ha?asa:
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* Copyright (C) 2015 Industrial Research Institute for Automation
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* and Measurements PIAP
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*
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* Notes
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* -----
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*
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* 1. Under stress-testing, it has been observed that the PCIe link
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* goes down, without reason. Therefore, the driver takes special care
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* to allow device hot-unplugging.
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*
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* 2. TW686X devices are capable of setting a few different DMA modes,
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* including: scatter-gather, field and frame modes. However,
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* under stress testings it has been found that the machine can
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* freeze completely if DMA registers are programmed while streaming
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* is active.
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*
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* Therefore, driver implements a dma_mode called 'memcpy' which
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* avoids cycling the DMA buffers, and insteads allocates extra DMA buffers
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* and then copies into vmalloc'ed user buffers.
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*
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* In addition to this, when streaming is on, the driver tries to access
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* hardware registers as infrequently as possible. This is done by using
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* a timer to limit the rate at which DMA is reset on DMA channels error.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci_ids.h>
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#include <linux/slab.h>
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#include <linux/timer.h>
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#include "tw686x.h"
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#include "tw686x-regs.h"
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/*
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* This module parameter allows to control the DMA_TIMER_INTERVAL value.
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* The DMA_TIMER_INTERVAL register controls the minimum DMA interrupt
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* time span (iow, the maximum DMA interrupt rate) thus allowing for
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* IRQ coalescing.
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*
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* The chip datasheet does not mention a time unit for this value, so
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* users wanting fine-grain control over the interrupt rate should
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* determine the desired value through testing.
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*/
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static u32 dma_interval = 0x00098968;
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module_param(dma_interval, int, 0444);
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MODULE_PARM_DESC(dma_interval, "Minimum time span for DMA interrupting host");
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static unsigned int dma_mode = TW686X_DMA_MODE_MEMCPY;
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static const char *dma_mode_name(unsigned int mode)
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{
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switch (mode) {
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case TW686X_DMA_MODE_MEMCPY:
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return "memcpy";
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case TW686X_DMA_MODE_CONTIG:
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return "contig";
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case TW686X_DMA_MODE_SG:
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return "sg";
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default:
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return "unknown";
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}
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}
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static int tw686x_dma_mode_get(char *buffer, const struct kernel_param *kp)
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{
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return sprintf(buffer, "%s", dma_mode_name(dma_mode));
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}
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static int tw686x_dma_mode_set(const char *val, const struct kernel_param *kp)
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{
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if (!strcasecmp(val, dma_mode_name(TW686X_DMA_MODE_MEMCPY)))
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dma_mode = TW686X_DMA_MODE_MEMCPY;
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else if (!strcasecmp(val, dma_mode_name(TW686X_DMA_MODE_CONTIG)))
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dma_mode = TW686X_DMA_MODE_CONTIG;
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else if (!strcasecmp(val, dma_mode_name(TW686X_DMA_MODE_SG)))
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dma_mode = TW686X_DMA_MODE_SG;
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else
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return -EINVAL;
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return 0;
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}
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module_param_call(dma_mode, tw686x_dma_mode_set, tw686x_dma_mode_get,
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&dma_mode, S_IRUGO|S_IWUSR);
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MODULE_PARM_DESC(dma_mode, "DMA operation mode (memcpy/contig/sg, default=memcpy)");
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void tw686x_disable_channel(struct tw686x_dev *dev, unsigned int channel)
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{
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u32 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE);
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u32 dma_cmd = reg_read(dev, DMA_CMD);
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dma_en &= ~BIT(channel);
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dma_cmd &= ~BIT(channel);
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/* Must remove it from pending too */
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dev->pending_dma_en &= ~BIT(channel);
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dev->pending_dma_cmd &= ~BIT(channel);
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/* Stop DMA if no channels are enabled */
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if (!dma_en)
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dma_cmd = 0;
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reg_write(dev, DMA_CHANNEL_ENABLE, dma_en);
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reg_write(dev, DMA_CMD, dma_cmd);
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}
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void tw686x_enable_channel(struct tw686x_dev *dev, unsigned int channel)
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{
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u32 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE);
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u32 dma_cmd = reg_read(dev, DMA_CMD);
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dev->pending_dma_en |= dma_en | BIT(channel);
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dev->pending_dma_cmd |= dma_cmd | DMA_CMD_ENABLE | BIT(channel);
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}
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/*
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* The purpose of this awful hack is to avoid enabling the DMA
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* channels "too fast" which makes some TW686x devices very
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* angry and freeze the CPU (see note 1).
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*/
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static void tw686x_dma_delay(struct timer_list *t)
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{
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struct tw686x_dev *dev = from_timer(dev, t, dma_delay_timer);
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unsigned long flags;
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spin_lock_irqsave(&dev->lock, flags);
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reg_write(dev, DMA_CHANNEL_ENABLE, dev->pending_dma_en);
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reg_write(dev, DMA_CMD, dev->pending_dma_cmd);
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dev->pending_dma_en = 0;
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dev->pending_dma_cmd = 0;
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spin_unlock_irqrestore(&dev->lock, flags);
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}
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static void tw686x_reset_channels(struct tw686x_dev *dev, unsigned int ch_mask)
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{
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u32 dma_en, dma_cmd;
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dma_en = reg_read(dev, DMA_CHANNEL_ENABLE);
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dma_cmd = reg_read(dev, DMA_CMD);
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/*
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* Save pending register status, the timer will
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* restore them.
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*/
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dev->pending_dma_en |= dma_en;
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dev->pending_dma_cmd |= dma_cmd;
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/* Disable the reset channels */
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reg_write(dev, DMA_CHANNEL_ENABLE, dma_en & ~ch_mask);
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if ((dma_en & ~ch_mask) == 0) {
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dev_dbg(&dev->pci_dev->dev, "reset: stopping DMA\n");
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dma_cmd &= ~DMA_CMD_ENABLE;
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}
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reg_write(dev, DMA_CMD, dma_cmd & ~ch_mask);
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}
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static irqreturn_t tw686x_irq(int irq, void *dev_id)
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{
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struct tw686x_dev *dev = (struct tw686x_dev *)dev_id;
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unsigned int video_requests, audio_requests, reset_ch;
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u32 fifo_status, fifo_signal, fifo_ov, fifo_bad, fifo_errors;
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u32 int_status, dma_en, video_en, pb_status;
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unsigned long flags;
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int_status = reg_read(dev, INT_STATUS); /* cleared on read */
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fifo_status = reg_read(dev, VIDEO_FIFO_STATUS);
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/* INT_STATUS does not include FIFO_STATUS errors! */
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if (!int_status && !TW686X_FIFO_ERROR(fifo_status))
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return IRQ_NONE;
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if (int_status & INT_STATUS_DMA_TOUT) {
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dev_dbg(&dev->pci_dev->dev,
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"DMA timeout. Resetting DMA for all channels\n");
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reset_ch = ~0;
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goto reset_channels;
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}
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spin_lock_irqsave(&dev->lock, flags);
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dma_en = reg_read(dev, DMA_CHANNEL_ENABLE);
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spin_unlock_irqrestore(&dev->lock, flags);
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video_en = dma_en & 0xff;
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fifo_signal = ~(fifo_status & 0xff) & video_en;
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fifo_ov = fifo_status >> 24;
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fifo_bad = fifo_status >> 16;
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/* Mask of channels with signal and FIFO errors */
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fifo_errors = fifo_signal & (fifo_ov | fifo_bad);
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reset_ch = 0;
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pb_status = reg_read(dev, PB_STATUS);
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/* Coalesce video frame/error events */
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video_requests = (int_status & video_en) | fifo_errors;
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audio_requests = (int_status & dma_en) >> 8;
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if (video_requests)
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tw686x_video_irq(dev, video_requests, pb_status,
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fifo_status, &reset_ch);
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if (audio_requests)
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tw686x_audio_irq(dev, audio_requests, pb_status);
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reset_channels:
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if (reset_ch) {
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spin_lock_irqsave(&dev->lock, flags);
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tw686x_reset_channels(dev, reset_ch);
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spin_unlock_irqrestore(&dev->lock, flags);
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mod_timer(&dev->dma_delay_timer,
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jiffies + msecs_to_jiffies(100));
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}
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return IRQ_HANDLED;
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}
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static void tw686x_dev_release(struct v4l2_device *v4l2_dev)
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{
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struct tw686x_dev *dev = container_of(v4l2_dev, struct tw686x_dev,
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v4l2_dev);
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unsigned int ch;
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for (ch = 0; ch < max_channels(dev); ch++)
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v4l2_ctrl_handler_free(&dev->video_channels[ch].ctrl_handler);
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v4l2_device_unregister(&dev->v4l2_dev);
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kfree(dev->audio_channels);
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kfree(dev->video_channels);
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kfree(dev);
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}
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static int tw686x_probe(struct pci_dev *pci_dev,
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const struct pci_device_id *pci_id)
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{
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struct tw686x_dev *dev;
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int err;
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dev = kzalloc(sizeof(*dev), GFP_KERNEL);
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if (!dev)
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return -ENOMEM;
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dev->type = pci_id->driver_data;
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dev->dma_mode = dma_mode;
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sprintf(dev->name, "tw%04X", pci_dev->device);
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dev->video_channels = kcalloc(max_channels(dev),
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sizeof(*dev->video_channels), GFP_KERNEL);
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if (!dev->video_channels) {
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err = -ENOMEM;
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goto free_dev;
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}
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dev->audio_channels = kcalloc(max_channels(dev),
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sizeof(*dev->audio_channels), GFP_KERNEL);
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if (!dev->audio_channels) {
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err = -ENOMEM;
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goto free_video;
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}
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pr_info("%s: PCI %s, IRQ %d, MMIO 0x%lx (%s mode)\n", dev->name,
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pci_name(pci_dev), pci_dev->irq,
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(unsigned long)pci_resource_start(pci_dev, 0),
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dma_mode_name(dma_mode));
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dev->pci_dev = pci_dev;
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if (pci_enable_device(pci_dev)) {
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err = -EIO;
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goto free_audio;
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}
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pci_set_master(pci_dev);
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err = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
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if (err) {
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dev_err(&pci_dev->dev, "32-bit PCI DMA not supported\n");
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err = -EIO;
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goto disable_pci;
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}
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err = pci_request_regions(pci_dev, dev->name);
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if (err) {
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dev_err(&pci_dev->dev, "unable to request PCI region\n");
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goto disable_pci;
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}
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dev->mmio = pci_ioremap_bar(pci_dev, 0);
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if (!dev->mmio) {
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dev_err(&pci_dev->dev, "unable to remap PCI region\n");
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err = -ENOMEM;
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goto free_region;
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}
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/* Reset all subsystems */
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reg_write(dev, SYS_SOFT_RST, 0x0f);
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mdelay(1);
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reg_write(dev, SRST[0], 0x3f);
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if (max_channels(dev) > 4)
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reg_write(dev, SRST[1], 0x3f);
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/* Disable the DMA engine */
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reg_write(dev, DMA_CMD, 0);
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reg_write(dev, DMA_CHANNEL_ENABLE, 0);
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/* Enable DMA FIFO overflow and pointer check */
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reg_write(dev, DMA_CONFIG, 0xffffff04);
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reg_write(dev, DMA_CHANNEL_TIMEOUT, 0x140c8584);
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reg_write(dev, DMA_TIMER_INTERVAL, dma_interval);
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spin_lock_init(&dev->lock);
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timer_setup(&dev->dma_delay_timer, tw686x_dma_delay, 0);
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/*
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* This must be set right before initializing v4l2_dev.
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* It's used to release resources after the last handle
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* held is released.
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*/
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dev->v4l2_dev.release = tw686x_dev_release;
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err = tw686x_video_init(dev);
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if (err) {
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dev_err(&pci_dev->dev, "can't register video\n");
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goto iounmap;
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}
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err = tw686x_audio_init(dev);
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if (err)
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dev_warn(&pci_dev->dev, "can't register audio\n");
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err = request_irq(pci_dev->irq, tw686x_irq, IRQF_SHARED,
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dev->name, dev);
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if (err < 0) {
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dev_err(&pci_dev->dev, "unable to request interrupt\n");
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goto iounmap;
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}
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pci_set_drvdata(pci_dev, dev);
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return 0;
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iounmap:
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pci_iounmap(pci_dev, dev->mmio);
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free_region:
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pci_release_regions(pci_dev);
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disable_pci:
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pci_disable_device(pci_dev);
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free_audio:
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kfree(dev->audio_channels);
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free_video:
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kfree(dev->video_channels);
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free_dev:
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kfree(dev);
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return err;
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}
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static void tw686x_remove(struct pci_dev *pci_dev)
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{
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struct tw686x_dev *dev = pci_get_drvdata(pci_dev);
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unsigned long flags;
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/* This guarantees the IRQ handler is no longer running,
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* which means we can kiss good-bye some resources.
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*/
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free_irq(pci_dev->irq, dev);
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tw686x_video_free(dev);
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tw686x_audio_free(dev);
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del_timer_sync(&dev->dma_delay_timer);
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pci_iounmap(pci_dev, dev->mmio);
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pci_release_regions(pci_dev);
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pci_disable_device(pci_dev);
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/*
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* Setting pci_dev to NULL allows to detect hardware is no longer
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* available and will be used by vb2_ops. This is required because
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* the device sometimes hot-unplugs itself as the result of a PCIe
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* link down.
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* The lock is really important here.
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*/
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spin_lock_irqsave(&dev->lock, flags);
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dev->pci_dev = NULL;
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spin_unlock_irqrestore(&dev->lock, flags);
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/*
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* This calls tw686x_dev_release if it's the last reference.
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* Otherwise, release is postponed until there are no users left.
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*/
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v4l2_device_put(&dev->v4l2_dev);
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}
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/*
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* On TW6864 and TW6868, all channels share the pair of video DMA SG tables,
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* with 10-bit start_idx and end_idx determining start and end of frame buffer
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* for particular channel.
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* TW6868 with all its 8 channels would be problematic (only 127 SG entries per
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* channel) but we support only 4 channels on this chip anyway (the first
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* 4 channels are driven with internal video decoder, the other 4 would require
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* an external TW286x part).
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*
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* On TW6865 and TW6869, each channel has its own DMA SG table, with indexes
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* starting with 0. Both chips have complete sets of internal video decoders
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* (respectively 4 or 8-channel).
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*
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* All chips have separate SG tables for two video frames.
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*/
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/* driver_data is number of A/V channels */
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static const struct pci_device_id tw686x_pci_tbl[] = {
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{
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PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6864),
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.driver_data = 4
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},
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{
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PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6865), /* not tested */
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.driver_data = 4 | TYPE_SECOND_GEN
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},
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/*
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* TW6868 supports 8 A/V channels with an external TW2865 chip;
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* not supported by the driver.
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*/
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{
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PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6868), /* not tested */
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.driver_data = 4
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},
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{
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PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6869),
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.driver_data = 8 | TYPE_SECOND_GEN},
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{}
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};
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MODULE_DEVICE_TABLE(pci, tw686x_pci_tbl);
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static struct pci_driver tw686x_pci_driver = {
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.name = "tw686x",
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.id_table = tw686x_pci_tbl,
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.probe = tw686x_probe,
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.remove = tw686x_remove,
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};
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module_pci_driver(tw686x_pci_driver);
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MODULE_DESCRIPTION("Driver for video frame grabber cards based on Intersil/Techwell TW686[4589]");
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MODULE_AUTHOR("Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>");
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MODULE_AUTHOR("Krzysztof Ha?asa <khalasa@piap.pl>");
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MODULE_LICENSE("GPL v2");
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