/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2014-2015 Cisco Systems, Inc. and/or its affiliates.
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* All rights reserved.
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*/
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#ifndef M00479_CLK_LOSS_DETECTOR_MEMMAP_PACKAGE_H
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#define M00479_CLK_LOSS_DETECTOR_MEMMAP_PACKAGE_H
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/*******************************************************************
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* Register Block
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* M00479_CLK_LOSS_DETECTOR_MEMMAP_PACKAGE_VHD_REGMAP
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*******************************************************************/
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struct m00479_clk_loss_detector_regmap {
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/* Control module */
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uint32_t ctrl; /* Reg 0x0000, Default=0x0 */
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uint32_t status; /* Reg 0x0004 */
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/* Number of ref clk cycles before checking the clock under test */
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uint32_t ref_clk_cnt_val; /* Reg 0x0008, Default=0xc4 */
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/* Number of test clk cycles required in the ref_clk_cnt_val period
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* to ensure that the test clock is performing as expected */
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uint32_t test_clk_cnt_val; /* Reg 0x000c, Default=0xa */
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};
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#define M00479_CLK_LOSS_DETECTOR_REG_CTRL_OFST 0
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#define M00479_CLK_LOSS_DETECTOR_REG_STATUS_OFST 4
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#define M00479_CLK_LOSS_DETECTOR_REG_REF_CLK_CNT_VAL_OFST 8
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#define M00479_CLK_LOSS_DETECTOR_REG_TEST_CLK_CNT_VAL_OFST 12
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/*******************************************************************
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* Bit Mask for register
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* M00479_CLK_LOSS_DETECTOR_MEMMAP_PACKAGE_VHD_BITMAP
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*******************************************************************/
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/* ctrl [0:0] */
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#define M00479_CTRL_BITMAP_ENABLE_OFST (0)
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#define M00479_CTRL_BITMAP_ENABLE_MSK (0x1 << M00479_CTRL_BITMAP_ENABLE_OFST)
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/* status [0:0] */
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#define M00479_STATUS_BITMAP_CLOCK_MISSING_OFST (0)
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#define M00479_STATUS_BITMAP_CLOCK_MISSING_MSK (0x1 << M00479_STATUS_BITMAP_CLOCK_MISSING_OFST)
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#endif /*M00479_CLK_LOSS_DETECTOR_MEMMAP_PACKAGE_H*/
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