/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2014-2015 Cisco Systems, Inc. and/or its affiliates.
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* All rights reserved.
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*/
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#ifndef M00473_FREEWHEEL_MEMMAP_PACKAGE_H
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#define M00473_FREEWHEEL_MEMMAP_PACKAGE_H
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/*******************************************************************
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* Register Block
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* M00473_FREEWHEEL_MEMMAP_PACKAGE_VHD_REGMAP
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*******************************************************************/
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struct m00473_freewheel_regmap {
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uint32_t ctrl; /* Reg 0x0000, Default=0x0 */
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uint32_t status; /* Reg 0x0004 */
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uint32_t active_length; /* Reg 0x0008, Default=0x1fa400 */
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uint32_t total_length; /* Reg 0x000c, Default=0x31151b */
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uint32_t data_width; /* Reg 0x0010 */
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uint32_t output_color; /* Reg 0x0014, Default=0xffff */
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uint32_t clk_freq; /* Reg 0x0018 */
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};
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#define M00473_FREEWHEEL_REG_CTRL_OFST 0
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#define M00473_FREEWHEEL_REG_STATUS_OFST 4
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#define M00473_FREEWHEEL_REG_ACTIVE_LENGTH_OFST 8
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#define M00473_FREEWHEEL_REG_TOTAL_LENGTH_OFST 12
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#define M00473_FREEWHEEL_REG_DATA_WIDTH_OFST 16
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#define M00473_FREEWHEEL_REG_OUTPUT_COLOR_OFST 20
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#define M00473_FREEWHEEL_REG_CLK_FREQ_OFST 24
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/*******************************************************************
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* Bit Mask for register
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* M00473_FREEWHEEL_MEMMAP_PACKAGE_VHD_BITMAP
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*******************************************************************/
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/* ctrl [1:0] */
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#define M00473_CTRL_BITMAP_ENABLE_OFST (0)
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#define M00473_CTRL_BITMAP_ENABLE_MSK (0x1 << M00473_CTRL_BITMAP_ENABLE_OFST)
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#define M00473_CTRL_BITMAP_FORCE_FREEWHEEL_MODE_OFST (1)
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#define M00473_CTRL_BITMAP_FORCE_FREEWHEEL_MODE_MSK (0x1 << M00473_CTRL_BITMAP_FORCE_FREEWHEEL_MODE_OFST)
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/* status [0:0] */
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#define M00473_STATUS_BITMAP_FREEWHEEL_MODE_OFST (0)
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#define M00473_STATUS_BITMAP_FREEWHEEL_MODE_MSK (0x1 << M00473_STATUS_BITMAP_FREEWHEEL_MODE_OFST)
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#endif /*M00473_FREEWHEEL_MEMMAP_PACKAGE_H*/
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