// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Omnitek Scatter-Gather DMA Controller
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*
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* Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
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* All rights reserved.
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*/
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#include <linux/string.h>
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#include <linux/io.h>
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#include <linux/pci_regs.h>
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#include <linux/spinlock.h>
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#include "cobalt-driver.h"
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#include "cobalt-omnitek.h"
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/* descriptor */
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#define END_OF_CHAIN (1 << 1)
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#define INTERRUPT_ENABLE (1 << 2)
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#define WRITE_TO_PCI (1 << 3)
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#define READ_FROM_PCI (0 << 3)
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#define DESCRIPTOR_FLAG_MSK (END_OF_CHAIN | INTERRUPT_ENABLE | WRITE_TO_PCI)
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#define NEXT_ADRS_MSK 0xffffffe0
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/* control/status register */
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#define ENABLE (1 << 0)
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#define START (1 << 1)
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#define ABORT (1 << 2)
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#define DONE (1 << 4)
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#define SG_INTERRUPT (1 << 5)
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#define EVENT_INTERRUPT (1 << 6)
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#define SCATTER_GATHER_MODE (1 << 8)
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#define DISABLE_VIDEO_RESYNC (1 << 9)
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#define EVENT_INTERRUPT_ENABLE (1 << 10)
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#define DIRECTIONAL_MSK (3 << 16)
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#define INPUT_ONLY (0 << 16)
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#define OUTPUT_ONLY (1 << 16)
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#define BIDIRECTIONAL (2 << 16)
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#define DMA_TYPE_MEMORY (0 << 18)
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#define DMA_TYPE_FIFO (1 << 18)
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#define BASE (cobalt->bar0)
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#define CAPABILITY_HEADER (BASE)
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#define CAPABILITY_REGISTER (BASE + 0x04)
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#define PCI_64BIT (1 << 8)
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#define LOCAL_64BIT (1 << 9)
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#define INTERRUPT_STATUS (BASE + 0x08)
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#define PCI(c) (BASE + 0x40 + ((c) * 0x40))
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#define SIZE(c) (BASE + 0x58 + ((c) * 0x40))
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#define DESCRIPTOR(c) (BASE + 0x50 + ((c) * 0x40))
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#define CS_REG(c) (BASE + 0x60 + ((c) * 0x40))
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#define BYTES_TRANSFERRED(c) (BASE + 0x64 + ((c) * 0x40))
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static char *get_dma_direction(u32 status)
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{
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switch (status & DIRECTIONAL_MSK) {
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case INPUT_ONLY: return "Input";
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case OUTPUT_ONLY: return "Output";
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case BIDIRECTIONAL: return "Bidirectional";
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}
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return "";
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}
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static void show_dma_capability(struct cobalt *cobalt)
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{
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u32 header = ioread32(CAPABILITY_HEADER);
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u32 capa = ioread32(CAPABILITY_REGISTER);
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u32 i;
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cobalt_info("Omnitek DMA capability: ID 0x%02x Version 0x%02x Next 0x%x Size 0x%x\n",
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header & 0xff, (header >> 8) & 0xff,
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(header >> 16) & 0xffff, (capa >> 24) & 0xff);
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switch ((capa >> 8) & 0x3) {
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case 0:
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cobalt_info("Omnitek DMA: 32 bits PCIe and Local\n");
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break;
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case 1:
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cobalt_info("Omnitek DMA: 64 bits PCIe, 32 bits Local\n");
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break;
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case 3:
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cobalt_info("Omnitek DMA: 64 bits PCIe and Local\n");
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break;
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}
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for (i = 0; i < (capa & 0xf); i++) {
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u32 status = ioread32(CS_REG(i));
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cobalt_info("Omnitek DMA channel #%d: %s %s\n", i,
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status & DMA_TYPE_FIFO ? "FIFO" : "MEMORY",
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get_dma_direction(status));
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}
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}
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void omni_sg_dma_start(struct cobalt_stream *s, struct sg_dma_desc_info *desc)
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{
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struct cobalt *cobalt = s->cobalt;
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iowrite32((u32)((u64)desc->bus >> 32), DESCRIPTOR(s->dma_channel) + 4);
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iowrite32((u32)desc->bus & NEXT_ADRS_MSK, DESCRIPTOR(s->dma_channel));
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iowrite32(ENABLE | SCATTER_GATHER_MODE | START, CS_REG(s->dma_channel));
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}
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bool is_dma_done(struct cobalt_stream *s)
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{
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struct cobalt *cobalt = s->cobalt;
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if (ioread32(CS_REG(s->dma_channel)) & DONE)
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return true;
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return false;
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}
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void omni_sg_dma_abort_channel(struct cobalt_stream *s)
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{
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struct cobalt *cobalt = s->cobalt;
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if (!is_dma_done(s))
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iowrite32(ABORT, CS_REG(s->dma_channel));
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}
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int omni_sg_dma_init(struct cobalt *cobalt)
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{
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u32 capa = ioread32(CAPABILITY_REGISTER);
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int i;
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cobalt->first_fifo_channel = 0;
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cobalt->dma_channels = capa & 0xf;
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if (capa & PCI_64BIT)
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cobalt->pci_32_bit = false;
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else
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cobalt->pci_32_bit = true;
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for (i = 0; i < cobalt->dma_channels; i++) {
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u32 status = ioread32(CS_REG(i));
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u32 ctrl = ioread32(CS_REG(i));
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if (!(ctrl & DONE))
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iowrite32(ABORT, CS_REG(i));
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if (!(status & DMA_TYPE_FIFO))
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cobalt->first_fifo_channel++;
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}
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show_dma_capability(cobalt);
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return 0;
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}
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int descriptor_list_create(struct cobalt *cobalt,
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struct scatterlist *scatter_list, bool to_pci, unsigned sglen,
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unsigned size, unsigned width, unsigned stride,
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struct sg_dma_desc_info *desc)
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{
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struct sg_dma_descriptor *d = (struct sg_dma_descriptor *)desc->virt;
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dma_addr_t next = desc->bus;
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unsigned offset = 0;
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unsigned copy_bytes = width;
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unsigned copied = 0;
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bool first = true;
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/* Must be 4-byte aligned */
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WARN_ON(sg_dma_address(scatter_list) & 3);
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WARN_ON(size & 3);
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WARN_ON(next & 3);
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WARN_ON(stride & 3);
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WARN_ON(stride < width);
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if (width >= stride)
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copy_bytes = stride = size;
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while (size) {
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dma_addr_t addr = sg_dma_address(scatter_list) + offset;
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unsigned bytes;
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if (addr == 0)
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return -EFAULT;
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if (cobalt->pci_32_bit) {
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WARN_ON((u64)addr >> 32);
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if ((u64)addr >> 32)
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return -EFAULT;
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}
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/* PCIe address */
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d->pci_l = addr & 0xffffffff;
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/* If dma_addr_t is 32 bits, then addr >> 32 is actually the
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equivalent of addr >> 0 in gcc. So must cast to u64. */
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d->pci_h = (u64)addr >> 32;
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/* Sync to start of streaming frame */
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d->local = 0;
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d->reserved0 = 0;
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/* Transfer bytes */
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bytes = min(sg_dma_len(scatter_list) - offset,
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copy_bytes - copied);
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if (first) {
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if (to_pci)
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d->local = 0x11111111;
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first = false;
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if (sglen == 1) {
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/* Make sure there are always at least two
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* descriptors */
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d->bytes = (bytes / 2) & ~3;
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d->reserved1 = 0;
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size -= d->bytes;
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copied += d->bytes;
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offset += d->bytes;
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addr += d->bytes;
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next += sizeof(struct sg_dma_descriptor);
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d->next_h = (u32)((u64)next >> 32);
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d->next_l = (u32)next |
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(to_pci ? WRITE_TO_PCI : 0);
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bytes -= d->bytes;
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d++;
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/* PCIe address */
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d->pci_l = addr & 0xffffffff;
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/* If dma_addr_t is 32 bits, then addr >> 32
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* is actually the equivalent of addr >> 0 in
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* gcc. So must cast to u64. */
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d->pci_h = (u64)addr >> 32;
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/* Sync to start of streaming frame */
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d->local = 0;
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d->reserved0 = 0;
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}
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}
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d->bytes = bytes;
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d->reserved1 = 0;
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size -= bytes;
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copied += bytes;
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offset += bytes;
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if (copied == copy_bytes) {
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while (copied < stride) {
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bytes = min(sg_dma_len(scatter_list) - offset,
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stride - copied);
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copied += bytes;
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offset += bytes;
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size -= bytes;
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if (sg_dma_len(scatter_list) == offset) {
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offset = 0;
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scatter_list = sg_next(scatter_list);
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}
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}
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copied = 0;
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} else {
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offset = 0;
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scatter_list = sg_next(scatter_list);
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}
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/* Next descriptor + control bits */
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next += sizeof(struct sg_dma_descriptor);
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if (size == 0) {
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/* Loopback to the first descriptor */
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d->next_h = (u32)((u64)desc->bus >> 32);
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d->next_l = (u32)desc->bus |
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(to_pci ? WRITE_TO_PCI : 0) | INTERRUPT_ENABLE;
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if (!to_pci)
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d->local = 0x22222222;
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desc->last_desc_virt = d;
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} else {
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d->next_h = (u32)((u64)next >> 32);
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d->next_l = (u32)next | (to_pci ? WRITE_TO_PCI : 0);
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}
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d++;
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}
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return 0;
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}
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void descriptor_list_chain(struct sg_dma_desc_info *this,
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struct sg_dma_desc_info *next)
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{
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struct sg_dma_descriptor *d = this->last_desc_virt;
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u32 direction = d->next_l & WRITE_TO_PCI;
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if (next == NULL) {
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d->next_h = 0;
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d->next_l = direction | INTERRUPT_ENABLE | END_OF_CHAIN;
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} else {
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d->next_h = (u32)((u64)next->bus >> 32);
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d->next_l = (u32)next->bus | direction | INTERRUPT_ENABLE;
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}
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}
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void *descriptor_list_allocate(struct sg_dma_desc_info *desc, size_t bytes)
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{
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desc->size = bytes;
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desc->virt = dma_alloc_coherent(desc->dev, bytes,
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&desc->bus, GFP_KERNEL);
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return desc->virt;
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}
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void descriptor_list_free(struct sg_dma_desc_info *desc)
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{
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if (desc->virt)
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dma_free_coherent(desc->dev, desc->size,
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desc->virt, desc->bus);
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desc->virt = NULL;
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}
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void descriptor_list_interrupt_enable(struct sg_dma_desc_info *desc)
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{
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struct sg_dma_descriptor *d = desc->last_desc_virt;
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d->next_l |= INTERRUPT_ENABLE;
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}
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void descriptor_list_interrupt_disable(struct sg_dma_desc_info *desc)
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{
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struct sg_dma_descriptor *d = desc->last_desc_virt;
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d->next_l &= ~INTERRUPT_ENABLE;
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}
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void descriptor_list_loopback(struct sg_dma_desc_info *desc)
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{
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struct sg_dma_descriptor *d = desc->last_desc_virt;
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d->next_h = (u32)((u64)desc->bus >> 32);
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d->next_l = (u32)desc->bus | (d->next_l & DESCRIPTOR_FLAG_MSK);
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}
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void descriptor_list_end_of_chain(struct sg_dma_desc_info *desc)
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{
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struct sg_dma_descriptor *d = desc->last_desc_virt;
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d->next_l |= END_OF_CHAIN;
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}
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