// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Tegra CEC implementation
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*
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* The original 3.10 CEC driver using a custom API:
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*
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* Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* Conversion to the CEC framework and to the mainline kernel:
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*
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* Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/pm.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/clk/tegra.h>
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#include <media/cec-notifier.h>
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#include "tegra_cec.h"
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#define TEGRA_CEC_NAME "tegra-cec"
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struct tegra_cec {
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struct cec_adapter *adap;
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struct device *dev;
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struct clk *clk;
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void __iomem *cec_base;
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struct cec_notifier *notifier;
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int tegra_cec_irq;
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bool rx_done;
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bool tx_done;
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int tx_status;
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u8 rx_buf[CEC_MAX_MSG_SIZE];
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u8 rx_buf_cnt;
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u32 tx_buf[CEC_MAX_MSG_SIZE];
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u8 tx_buf_cur;
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u8 tx_buf_cnt;
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};
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static inline u32 cec_read(struct tegra_cec *cec, u32 reg)
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{
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return readl(cec->cec_base + reg);
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}
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static inline void cec_write(struct tegra_cec *cec, u32 reg, u32 val)
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{
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writel(val, cec->cec_base + reg);
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}
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static void tegra_cec_error_recovery(struct tegra_cec *cec)
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{
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u32 hw_ctrl;
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hw_ctrl = cec_read(cec, TEGRA_CEC_HW_CONTROL);
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cec_write(cec, TEGRA_CEC_HW_CONTROL, 0);
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cec_write(cec, TEGRA_CEC_INT_STAT, 0xffffffff);
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cec_write(cec, TEGRA_CEC_HW_CONTROL, hw_ctrl);
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}
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static irqreturn_t tegra_cec_irq_thread_handler(int irq, void *data)
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{
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struct device *dev = data;
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struct tegra_cec *cec = dev_get_drvdata(dev);
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if (cec->tx_done) {
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cec_transmit_attempt_done(cec->adap, cec->tx_status);
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cec->tx_done = false;
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}
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if (cec->rx_done) {
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struct cec_msg msg = {};
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msg.len = cec->rx_buf_cnt;
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memcpy(msg.msg, cec->rx_buf, msg.len);
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cec_received_msg(cec->adap, &msg);
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cec->rx_done = false;
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cec->rx_buf_cnt = 0;
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t tegra_cec_irq_handler(int irq, void *data)
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{
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struct device *dev = data;
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struct tegra_cec *cec = dev_get_drvdata(dev);
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u32 status, mask;
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status = cec_read(cec, TEGRA_CEC_INT_STAT);
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mask = cec_read(cec, TEGRA_CEC_INT_MASK);
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status &= mask;
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if (!status)
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return IRQ_HANDLED;
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if (status & TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN) {
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dev_err(dev, "TX underrun, interrupt timing issue!\n");
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tegra_cec_error_recovery(cec);
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cec_write(cec, TEGRA_CEC_INT_MASK,
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mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY);
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cec->tx_done = true;
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cec->tx_status = CEC_TX_STATUS_ERROR;
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return IRQ_WAKE_THREAD;
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}
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if ((status & TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED) ||
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(status & TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED)) {
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tegra_cec_error_recovery(cec);
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cec_write(cec, TEGRA_CEC_INT_MASK,
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mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY);
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cec->tx_done = true;
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if (status & TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED)
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cec->tx_status = CEC_TX_STATUS_LOW_DRIVE;
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else
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cec->tx_status = CEC_TX_STATUS_ARB_LOST;
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return IRQ_WAKE_THREAD;
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}
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if (status & TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED) {
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cec_write(cec, TEGRA_CEC_INT_STAT,
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TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED);
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if (status & TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD) {
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tegra_cec_error_recovery(cec);
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cec->tx_done = true;
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cec->tx_status = CEC_TX_STATUS_NACK;
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} else {
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cec->tx_done = true;
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cec->tx_status = CEC_TX_STATUS_OK;
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}
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return IRQ_WAKE_THREAD;
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}
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if (status & TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD)
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dev_warn(dev, "TX NAKed on the fly!\n");
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if (status & TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY) {
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if (cec->tx_buf_cur == cec->tx_buf_cnt) {
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cec_write(cec, TEGRA_CEC_INT_MASK,
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mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY);
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} else {
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cec_write(cec, TEGRA_CEC_TX_REGISTER,
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cec->tx_buf[cec->tx_buf_cur++]);
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cec_write(cec, TEGRA_CEC_INT_STAT,
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TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY);
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}
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}
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if (status & TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED) {
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cec_write(cec, TEGRA_CEC_INT_STAT,
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TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED);
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cec->rx_done = false;
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cec->rx_buf_cnt = 0;
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}
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if (status & TEGRA_CEC_INT_STAT_RX_REGISTER_FULL) {
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u32 v;
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cec_write(cec, TEGRA_CEC_INT_STAT,
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TEGRA_CEC_INT_STAT_RX_REGISTER_FULL);
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v = cec_read(cec, TEGRA_CEC_RX_REGISTER);
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if (cec->rx_buf_cnt < CEC_MAX_MSG_SIZE)
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cec->rx_buf[cec->rx_buf_cnt++] = v & 0xff;
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if (v & TEGRA_CEC_RX_REGISTER_EOM) {
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cec->rx_done = true;
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return IRQ_WAKE_THREAD;
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}
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}
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return IRQ_HANDLED;
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}
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static int tegra_cec_adap_enable(struct cec_adapter *adap, bool enable)
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{
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struct tegra_cec *cec = adap->priv;
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cec->rx_buf_cnt = 0;
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cec->tx_buf_cnt = 0;
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cec->tx_buf_cur = 0;
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cec_write(cec, TEGRA_CEC_HW_CONTROL, 0);
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cec_write(cec, TEGRA_CEC_INT_MASK, 0);
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cec_write(cec, TEGRA_CEC_INT_STAT, 0xffffffff);
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cec_write(cec, TEGRA_CEC_SW_CONTROL, 0);
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if (!enable)
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return 0;
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cec_write(cec, TEGRA_CEC_INPUT_FILTER, (1U << 31) | 0x20);
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cec_write(cec, TEGRA_CEC_RX_TIMING_0,
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(0x7a << TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT) |
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(0x6d << TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT) |
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(0x93 << TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT) |
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(0x86 << TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT));
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cec_write(cec, TEGRA_CEC_RX_TIMING_1,
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(0x35 << TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT) |
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(0x21 << TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT) |
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(0x56 << TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT) |
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(0x40 << TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT));
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cec_write(cec, TEGRA_CEC_RX_TIMING_2,
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(0x50 << TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT));
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cec_write(cec, TEGRA_CEC_TX_TIMING_0,
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(0x74 << TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT) |
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(0x8d << TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT) |
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(0x08 << TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT) |
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(0x71 << TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT));
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cec_write(cec, TEGRA_CEC_TX_TIMING_1,
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(0x2f << TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT) |
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(0x13 << TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT) |
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(0x4b << TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT) |
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(0x21 << TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT));
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cec_write(cec, TEGRA_CEC_TX_TIMING_2,
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(0x07 << TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT) |
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(0x05 << TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT) |
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(0x03 << TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT));
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cec_write(cec, TEGRA_CEC_INT_MASK,
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TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN |
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TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD |
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TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED |
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TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED |
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TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED |
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TEGRA_CEC_INT_MASK_RX_REGISTER_FULL |
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TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED);
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cec_write(cec, TEGRA_CEC_HW_CONTROL, TEGRA_CEC_HWCTRL_TX_RX_MODE);
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return 0;
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}
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static int tegra_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)
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{
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struct tegra_cec *cec = adap->priv;
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u32 state = cec_read(cec, TEGRA_CEC_HW_CONTROL);
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if (logical_addr == CEC_LOG_ADDR_INVALID)
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state &= ~TEGRA_CEC_HWCTRL_RX_LADDR_MASK;
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else
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state |= TEGRA_CEC_HWCTRL_RX_LADDR((1 << logical_addr));
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cec_write(cec, TEGRA_CEC_HW_CONTROL, state);
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return 0;
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}
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static int tegra_cec_adap_monitor_all_enable(struct cec_adapter *adap,
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bool enable)
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{
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struct tegra_cec *cec = adap->priv;
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u32 reg = cec_read(cec, TEGRA_CEC_HW_CONTROL);
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if (enable)
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reg |= TEGRA_CEC_HWCTRL_RX_SNOOP;
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else
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reg &= ~TEGRA_CEC_HWCTRL_RX_SNOOP;
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cec_write(cec, TEGRA_CEC_HW_CONTROL, reg);
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return 0;
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}
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static int tegra_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
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u32 signal_free_time_ms, struct cec_msg *msg)
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{
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bool retry_xfer = signal_free_time_ms == CEC_SIGNAL_FREE_TIME_RETRY;
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struct tegra_cec *cec = adap->priv;
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unsigned int i;
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u32 mode = 0;
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u32 mask;
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if (cec_msg_is_broadcast(msg))
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mode = TEGRA_CEC_TX_REG_BCAST;
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cec->tx_buf_cur = 0;
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cec->tx_buf_cnt = msg->len;
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for (i = 0; i < msg->len; i++) {
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cec->tx_buf[i] = mode | msg->msg[i];
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if (i == 0)
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cec->tx_buf[i] |= TEGRA_CEC_TX_REG_START_BIT;
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if (i == msg->len - 1)
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cec->tx_buf[i] |= TEGRA_CEC_TX_REG_EOM;
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if (i == 0 && retry_xfer)
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cec->tx_buf[i] |= TEGRA_CEC_TX_REG_RETRY;
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}
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mask = cec_read(cec, TEGRA_CEC_INT_MASK);
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cec_write(cec, TEGRA_CEC_INT_MASK,
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mask | TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY);
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return 0;
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}
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static const struct cec_adap_ops tegra_cec_ops = {
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.adap_enable = tegra_cec_adap_enable,
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.adap_log_addr = tegra_cec_adap_log_addr,
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.adap_transmit = tegra_cec_adap_transmit,
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.adap_monitor_all_enable = tegra_cec_adap_monitor_all_enable,
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};
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static int tegra_cec_probe(struct platform_device *pdev)
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{
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struct device *hdmi_dev;
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struct tegra_cec *cec;
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struct resource *res;
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int ret = 0;
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hdmi_dev = cec_notifier_parse_hdmi_phandle(&pdev->dev);
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if (IS_ERR(hdmi_dev))
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return PTR_ERR(hdmi_dev);
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cec = devm_kzalloc(&pdev->dev, sizeof(struct tegra_cec), GFP_KERNEL);
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if (!cec)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev,
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"Unable to allocate resources for device\n");
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return -EBUSY;
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}
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if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
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pdev->name)) {
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dev_err(&pdev->dev,
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"Unable to request mem region for device\n");
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return -EBUSY;
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}
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cec->tegra_cec_irq = platform_get_irq(pdev, 0);
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if (cec->tegra_cec_irq <= 0)
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return -EBUSY;
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cec->cec_base = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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if (!cec->cec_base) {
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dev_err(&pdev->dev, "Unable to grab IOs for device\n");
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return -EBUSY;
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}
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cec->clk = devm_clk_get(&pdev->dev, "cec");
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if (IS_ERR_OR_NULL(cec->clk)) {
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dev_err(&pdev->dev, "Can't get clock for CEC\n");
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return -ENOENT;
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}
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ret = clk_prepare_enable(cec->clk);
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if (ret) {
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dev_err(&pdev->dev, "Unable to prepare clock for CEC\n");
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return ret;
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}
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/* set context info. */
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cec->dev = &pdev->dev;
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platform_set_drvdata(pdev, cec);
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ret = devm_request_threaded_irq(&pdev->dev, cec->tegra_cec_irq,
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tegra_cec_irq_handler, tegra_cec_irq_thread_handler,
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0, "cec_irq", &pdev->dev);
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if (ret) {
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dev_err(&pdev->dev,
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"Unable to request interrupt for device\n");
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goto err_clk;
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}
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cec->adap = cec_allocate_adapter(&tegra_cec_ops, cec, TEGRA_CEC_NAME,
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CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL |
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CEC_CAP_CONNECTOR_INFO,
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CEC_MAX_LOG_ADDRS);
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if (IS_ERR(cec->adap)) {
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ret = -ENOMEM;
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dev_err(&pdev->dev, "Couldn't create cec adapter\n");
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goto err_clk;
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}
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cec->notifier = cec_notifier_cec_adap_register(hdmi_dev, NULL,
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cec->adap);
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if (!cec->notifier) {
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ret = -ENOMEM;
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goto err_adapter;
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}
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ret = cec_register_adapter(cec->adap, &pdev->dev);
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if (ret) {
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dev_err(&pdev->dev, "Couldn't register device\n");
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goto err_notifier;
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}
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return 0;
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err_notifier:
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cec_notifier_cec_adap_unregister(cec->notifier, cec->adap);
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err_adapter:
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cec_delete_adapter(cec->adap);
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err_clk:
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clk_disable_unprepare(cec->clk);
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return ret;
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}
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static int tegra_cec_remove(struct platform_device *pdev)
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{
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struct tegra_cec *cec = platform_get_drvdata(pdev);
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clk_disable_unprepare(cec->clk);
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cec_notifier_cec_adap_unregister(cec->notifier, cec->adap);
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cec_unregister_adapter(cec->adap);
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return 0;
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}
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#ifdef CONFIG_PM
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static int tegra_cec_suspend(struct platform_device *pdev, pm_message_t state)
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{
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struct tegra_cec *cec = platform_get_drvdata(pdev);
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clk_disable_unprepare(cec->clk);
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dev_notice(&pdev->dev, "suspended\n");
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return 0;
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}
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static int tegra_cec_resume(struct platform_device *pdev)
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{
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struct tegra_cec *cec = platform_get_drvdata(pdev);
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dev_notice(&pdev->dev, "Resuming\n");
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return clk_prepare_enable(cec->clk);
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}
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#endif
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static const struct of_device_id tegra_cec_of_match[] = {
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{ .compatible = "nvidia,tegra114-cec", },
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{ .compatible = "nvidia,tegra124-cec", },
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{ .compatible = "nvidia,tegra210-cec", },
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{},
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};
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static struct platform_driver tegra_cec_driver = {
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.driver = {
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.name = TEGRA_CEC_NAME,
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.of_match_table = of_match_ptr(tegra_cec_of_match),
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},
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.probe = tegra_cec_probe,
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.remove = tegra_cec_remove,
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#ifdef CONFIG_PM
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.suspend = tegra_cec_suspend,
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.resume = tegra_cec_resume,
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#endif
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};
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module_platform_driver(tegra_cec_driver);
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MODULE_DESCRIPTION("Tegra HDMI CEC driver");
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MODULE_AUTHOR("NVIDIA CORPORATION");
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MODULE_AUTHOR("Cisco Systems, Inc. and/or its affiliates");
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MODULE_LICENSE("GPL v2");
|
