// SPDX-License-Identifier: GPL-2.0
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/*
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* STM32 CEC driver
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* Copyright (C) STMicroelectronics SA 2017
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*
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <media/cec.h>
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#define CEC_NAME "stm32-cec"
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/* CEC registers */
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#define CEC_CR 0x0000 /* Control Register */
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#define CEC_CFGR 0x0004 /* ConFiGuration Register */
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#define CEC_TXDR 0x0008 /* Rx data Register */
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#define CEC_RXDR 0x000C /* Rx data Register */
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#define CEC_ISR 0x0010 /* Interrupt and status Register */
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#define CEC_IER 0x0014 /* Interrupt enable Register */
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#define TXEOM BIT(2)
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#define TXSOM BIT(1)
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#define CECEN BIT(0)
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#define LSTN BIT(31)
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#define OAR GENMASK(30, 16)
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#define SFTOP BIT(8)
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#define BRDNOGEN BIT(7)
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#define LBPEGEN BIT(6)
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#define BREGEN BIT(5)
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#define BRESTP BIT(4)
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#define RXTOL BIT(3)
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#define SFT GENMASK(2, 0)
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#define FULL_CFG (LSTN | SFTOP | BRDNOGEN | LBPEGEN | BREGEN | BRESTP \
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| RXTOL)
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#define TXACKE BIT(12)
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#define TXERR BIT(11)
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#define TXUDR BIT(10)
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#define TXEND BIT(9)
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#define TXBR BIT(8)
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#define ARBLST BIT(7)
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#define RXACKE BIT(6)
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#define RXOVR BIT(2)
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#define RXEND BIT(1)
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#define RXBR BIT(0)
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#define ALL_TX_IT (TXEND | TXBR | TXACKE | TXERR | TXUDR | ARBLST)
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#define ALL_RX_IT (RXEND | RXBR | RXACKE | RXOVR)
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/*
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* 400 ms is the time it takes for one 16 byte message to be
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* transferred and 5 is the maximum number of retries. Add
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* another 100 ms as a margin.
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*/
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#define CEC_XFER_TIMEOUT_MS (5 * 400 + 100)
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struct stm32_cec {
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struct cec_adapter *adap;
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struct device *dev;
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struct clk *clk_cec;
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struct clk *clk_hdmi_cec;
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struct reset_control *rstc;
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struct regmap *regmap;
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int irq;
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u32 irq_status;
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struct cec_msg rx_msg;
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struct cec_msg tx_msg;
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int tx_cnt;
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};
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static void cec_hw_init(struct stm32_cec *cec)
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{
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regmap_update_bits(cec->regmap, CEC_CR, TXEOM | TXSOM | CECEN, 0);
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regmap_update_bits(cec->regmap, CEC_IER, ALL_TX_IT | ALL_RX_IT,
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ALL_TX_IT | ALL_RX_IT);
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regmap_update_bits(cec->regmap, CEC_CFGR, FULL_CFG, FULL_CFG);
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}
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static void stm32_tx_done(struct stm32_cec *cec, u32 status)
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{
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if (status & (TXERR | TXUDR)) {
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cec_transmit_done(cec->adap, CEC_TX_STATUS_ERROR,
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0, 0, 0, 1);
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return;
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}
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if (status & ARBLST) {
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cec_transmit_done(cec->adap, CEC_TX_STATUS_ARB_LOST,
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1, 0, 0, 0);
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return;
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}
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if (status & TXACKE) {
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cec_transmit_done(cec->adap, CEC_TX_STATUS_NACK,
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0, 1, 0, 0);
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return;
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}
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if (cec->irq_status & TXBR) {
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/* send next byte */
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if (cec->tx_cnt < cec->tx_msg.len)
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regmap_write(cec->regmap, CEC_TXDR,
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cec->tx_msg.msg[cec->tx_cnt++]);
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/* TXEOM is set to command transmission of the last byte */
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if (cec->tx_cnt == cec->tx_msg.len)
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regmap_update_bits(cec->regmap, CEC_CR, TXEOM, TXEOM);
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}
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if (cec->irq_status & TXEND)
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cec_transmit_done(cec->adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
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}
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static void stm32_rx_done(struct stm32_cec *cec, u32 status)
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{
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if (cec->irq_status & (RXACKE | RXOVR)) {
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cec->rx_msg.len = 0;
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return;
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}
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if (cec->irq_status & RXBR) {
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u32 val;
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regmap_read(cec->regmap, CEC_RXDR, &val);
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cec->rx_msg.msg[cec->rx_msg.len++] = val & 0xFF;
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}
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if (cec->irq_status & RXEND) {
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cec_received_msg(cec->adap, &cec->rx_msg);
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cec->rx_msg.len = 0;
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}
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}
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static irqreturn_t stm32_cec_irq_thread(int irq, void *arg)
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{
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struct stm32_cec *cec = arg;
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if (cec->irq_status & ALL_TX_IT)
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stm32_tx_done(cec, cec->irq_status);
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if (cec->irq_status & ALL_RX_IT)
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stm32_rx_done(cec, cec->irq_status);
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cec->irq_status = 0;
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return IRQ_HANDLED;
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}
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static irqreturn_t stm32_cec_irq_handler(int irq, void *arg)
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{
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struct stm32_cec *cec = arg;
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regmap_read(cec->regmap, CEC_ISR, &cec->irq_status);
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regmap_update_bits(cec->regmap, CEC_ISR,
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ALL_TX_IT | ALL_RX_IT,
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ALL_TX_IT | ALL_RX_IT);
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return IRQ_WAKE_THREAD;
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}
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static int stm32_cec_adap_enable(struct cec_adapter *adap, bool enable)
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{
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struct stm32_cec *cec = adap->priv;
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int ret = 0;
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if (enable) {
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ret = clk_enable(cec->clk_cec);
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if (ret)
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dev_err(cec->dev, "fail to enable cec clock\n");
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clk_enable(cec->clk_hdmi_cec);
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regmap_update_bits(cec->regmap, CEC_CR, CECEN, CECEN);
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} else {
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clk_disable(cec->clk_cec);
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clk_disable(cec->clk_hdmi_cec);
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regmap_update_bits(cec->regmap, CEC_CR, CECEN, 0);
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}
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return ret;
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}
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static int stm32_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)
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{
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struct stm32_cec *cec = adap->priv;
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u32 oar = (1 << logical_addr) << 16;
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u32 val;
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/* Poll every 100µs the register CEC_CR to wait end of transmission */
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regmap_read_poll_timeout(cec->regmap, CEC_CR, val, !(val & TXSOM),
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100, CEC_XFER_TIMEOUT_MS * 1000);
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regmap_update_bits(cec->regmap, CEC_CR, CECEN, 0);
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if (logical_addr == CEC_LOG_ADDR_INVALID)
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regmap_update_bits(cec->regmap, CEC_CFGR, OAR, 0);
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else
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regmap_update_bits(cec->regmap, CEC_CFGR, oar, oar);
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regmap_update_bits(cec->regmap, CEC_CR, CECEN, CECEN);
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return 0;
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}
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static int stm32_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
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u32 signal_free_time, struct cec_msg *msg)
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{
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struct stm32_cec *cec = adap->priv;
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/* Copy message */
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cec->tx_msg = *msg;
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cec->tx_cnt = 0;
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/*
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* If the CEC message consists of only one byte,
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* TXEOM must be set before of TXSOM.
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*/
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if (cec->tx_msg.len == 1)
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regmap_update_bits(cec->regmap, CEC_CR, TXEOM, TXEOM);
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/* TXSOM is set to command transmission of the first byte */
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regmap_update_bits(cec->regmap, CEC_CR, TXSOM, TXSOM);
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/* Write the header (first byte of message) */
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regmap_write(cec->regmap, CEC_TXDR, cec->tx_msg.msg[0]);
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cec->tx_cnt++;
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return 0;
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}
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static const struct cec_adap_ops stm32_cec_adap_ops = {
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.adap_enable = stm32_cec_adap_enable,
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.adap_log_addr = stm32_cec_adap_log_addr,
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.adap_transmit = stm32_cec_adap_transmit,
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};
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static const struct regmap_config stm32_cec_regmap_cfg = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = sizeof(u32),
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.max_register = 0x14,
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.fast_io = true,
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};
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static int stm32_cec_probe(struct platform_device *pdev)
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{
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u32 caps = CEC_CAP_DEFAULTS | CEC_CAP_PHYS_ADDR | CEC_MODE_MONITOR_ALL;
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struct resource *res;
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struct stm32_cec *cec;
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void __iomem *mmio;
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int ret;
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cec = devm_kzalloc(&pdev->dev, sizeof(*cec), GFP_KERNEL);
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if (!cec)
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return -ENOMEM;
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cec->dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mmio = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mmio))
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return PTR_ERR(mmio);
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cec->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "cec", mmio,
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&stm32_cec_regmap_cfg);
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if (IS_ERR(cec->regmap))
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return PTR_ERR(cec->regmap);
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cec->irq = platform_get_irq(pdev, 0);
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if (cec->irq < 0)
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return cec->irq;
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ret = devm_request_threaded_irq(&pdev->dev, cec->irq,
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stm32_cec_irq_handler,
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stm32_cec_irq_thread,
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0,
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pdev->name, cec);
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if (ret)
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return ret;
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cec->clk_cec = devm_clk_get(&pdev->dev, "cec");
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if (IS_ERR(cec->clk_cec)) {
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if (PTR_ERR(cec->clk_cec) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "Cannot get cec clock\n");
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return PTR_ERR(cec->clk_cec);
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}
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ret = clk_prepare(cec->clk_cec);
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if (ret) {
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dev_err(&pdev->dev, "Unable to prepare cec clock\n");
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return ret;
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}
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cec->clk_hdmi_cec = devm_clk_get(&pdev->dev, "hdmi-cec");
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if (IS_ERR(cec->clk_hdmi_cec) &&
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PTR_ERR(cec->clk_hdmi_cec) == -EPROBE_DEFER) {
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ret = -EPROBE_DEFER;
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goto err_unprepare_cec_clk;
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}
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if (!IS_ERR(cec->clk_hdmi_cec)) {
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ret = clk_prepare(cec->clk_hdmi_cec);
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if (ret) {
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dev_err(&pdev->dev, "Can't prepare hdmi-cec clock\n");
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goto err_unprepare_cec_clk;
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}
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}
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/*
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* CEC_CAP_PHYS_ADDR caps should be removed when a cec notifier is
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* available for example when a drm driver can provide edid
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*/
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cec->adap = cec_allocate_adapter(&stm32_cec_adap_ops, cec,
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CEC_NAME, caps, CEC_MAX_LOG_ADDRS);
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ret = PTR_ERR_OR_ZERO(cec->adap);
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if (ret)
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goto err_unprepare_hdmi_cec_clk;
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ret = cec_register_adapter(cec->adap, &pdev->dev);
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if (ret)
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goto err_delete_adapter;
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cec_hw_init(cec);
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platform_set_drvdata(pdev, cec);
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return 0;
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err_delete_adapter:
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cec_delete_adapter(cec->adap);
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err_unprepare_hdmi_cec_clk:
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clk_unprepare(cec->clk_hdmi_cec);
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err_unprepare_cec_clk:
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clk_unprepare(cec->clk_cec);
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return ret;
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}
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static int stm32_cec_remove(struct platform_device *pdev)
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{
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struct stm32_cec *cec = platform_get_drvdata(pdev);
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clk_unprepare(cec->clk_cec);
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clk_unprepare(cec->clk_hdmi_cec);
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cec_unregister_adapter(cec->adap);
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return 0;
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}
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static const struct of_device_id stm32_cec_of_match[] = {
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{ .compatible = "st,stm32-cec" },
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{ /* end node */ }
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};
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MODULE_DEVICE_TABLE(of, stm32_cec_of_match);
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static struct platform_driver stm32_cec_driver = {
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.probe = stm32_cec_probe,
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.remove = stm32_cec_remove,
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.driver = {
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.name = CEC_NAME,
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.of_match_table = stm32_cec_of_match,
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},
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};
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module_platform_driver(stm32_cec_driver);
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MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
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MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
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MODULE_DESCRIPTION("STMicroelectronics STM32 Consumer Electronics Control");
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MODULE_LICENSE("GPL v2");
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