/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* SECO X86 Boards CEC register defines
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*
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* Author: Ettore Chimenti <ek5.chimenti@gmail.com>
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* Copyright (C) 2018, SECO Spa.
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* Copyright (C) 2018, Aidilab Srl.
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*/
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#ifndef __SECO_CEC_H__
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#define __SECO_CEC_H__
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#define SECOCEC_MAX_ADDRS 1
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#define SECOCEC_DEV_NAME "secocec"
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#define SECOCEC_LATEST_FW 0x0f0b
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#define SMBTIMEOUT 0xfff
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#define SMB_POLL_UDELAY 10
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#define SMBUS_WRITE 0
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#define SMBUS_READ 1
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#define CMD_BYTE_DATA 0
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#define CMD_WORD_DATA 1
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/*
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* SMBus definitons for Braswell
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*/
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#define BRA_DONE_STATUS BIT(7)
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#define BRA_INUSE_STS BIT(6)
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#define BRA_FAILED_OP BIT(4)
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#define BRA_BUS_ERR BIT(3)
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#define BRA_DEV_ERR BIT(2)
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#define BRA_INTR BIT(1)
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#define BRA_HOST_BUSY BIT(0)
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#define BRA_HSTS_ERR_MASK (BRA_FAILED_OP | BRA_BUS_ERR | BRA_DEV_ERR)
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#define BRA_PEC_EN BIT(7)
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#define BRA_START BIT(6)
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#define BRA_LAST__BYTE BIT(5)
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#define BRA_INTREN BIT(0)
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#define BRA_SMB_CMD (7 << 2)
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#define BRA_SMB_CMD_QUICK (0 << 2)
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#define BRA_SMB_CMD_BYTE (1 << 2)
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#define BRA_SMB_CMD_BYTE_DATA (2 << 2)
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#define BRA_SMB_CMD_WORD_DATA (3 << 2)
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#define BRA_SMB_CMD_PROCESS_CALL (4 << 2)
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#define BRA_SMB_CMD_BLOCK (5 << 2)
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#define BRA_SMB_CMD_I2CREAD (6 << 2)
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#define BRA_SMB_CMD_BLOCK_PROCESS (7 << 2)
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#define BRA_SMB_BASE_ADDR 0x2040
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#define HSTS (BRA_SMB_BASE_ADDR + 0)
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#define HCNT (BRA_SMB_BASE_ADDR + 2)
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#define HCMD (BRA_SMB_BASE_ADDR + 3)
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#define XMIT_SLVA (BRA_SMB_BASE_ADDR + 4)
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#define HDAT0 (BRA_SMB_BASE_ADDR + 5)
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#define HDAT1 (BRA_SMB_BASE_ADDR + 6)
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/*
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* Microcontroller Address
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*/
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#define SECOCEC_MICRO_ADDRESS 0x40
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/*
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* STM32 SMBus Registers
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*/
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#define SECOCEC_VERSION 0x00
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#define SECOCEC_ENABLE_REG_1 0x01
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#define SECOCEC_ENABLE_REG_2 0x02
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#define SECOCEC_STATUS_REG_1 0x03
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#define SECOCEC_STATUS_REG_2 0x04
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#define SECOCEC_STATUS 0x28
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#define SECOCEC_DEVICE_LA 0x29
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#define SECOCEC_READ_OPERATION_ID 0x2a
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#define SECOCEC_READ_DATA_LENGTH 0x2b
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#define SECOCEC_READ_DATA_00 0x2c
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#define SECOCEC_READ_DATA_02 0x2d
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#define SECOCEC_READ_DATA_04 0x2e
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#define SECOCEC_READ_DATA_06 0x2f
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#define SECOCEC_READ_DATA_08 0x30
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#define SECOCEC_READ_DATA_10 0x31
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#define SECOCEC_READ_DATA_12 0x32
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#define SECOCEC_READ_BYTE0 0x33
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#define SECOCEC_WRITE_OPERATION_ID 0x34
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#define SECOCEC_WRITE_DATA_LENGTH 0x35
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#define SECOCEC_WRITE_DATA_00 0x36
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#define SECOCEC_WRITE_DATA_02 0x37
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#define SECOCEC_WRITE_DATA_04 0x38
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#define SECOCEC_WRITE_DATA_06 0x39
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#define SECOCEC_WRITE_DATA_08 0x3a
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#define SECOCEC_WRITE_DATA_10 0x3b
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#define SECOCEC_WRITE_DATA_12 0x3c
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#define SECOCEC_WRITE_BYTE0 0x3d
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#define SECOCEC_IR_READ_DATA 0x3e
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/*
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* IR
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*/
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#define SECOCEC_IR_COMMAND_MASK 0x007F
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#define SECOCEC_IR_COMMAND_SHL 0
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#define SECOCEC_IR_ADDRESS_MASK 0x1F00
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#define SECOCEC_IR_ADDRESS_SHL 8
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#define SECOCEC_IR_TOGGLE_MASK 0x8000
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#define SECOCEC_IR_TOGGLE_SHL 15
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/*
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* Enabling register
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*/
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#define SECOCEC_ENABLE_REG_1_CEC 0x1000
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#define SECOCEC_ENABLE_REG_1_IR 0x2000
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#define SECOCEC_ENABLE_REG_1_IR_PASSTHROUGH 0x4000
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/*
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* Status register
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*/
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#define SECOCEC_STATUS_REG_1_CEC SECOCEC_ENABLE_REG_1_CEC
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#define SECOCEC_STATUS_REG_1_IR SECOCEC_ENABLE_REG_1_IR
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#define SECOCEC_STATUS_REG_1_IR_PASSTHR SECOCEC_ENABLE_REG_1_IR_PASSTHR
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/*
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* Status data
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*/
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#define SECOCEC_STATUS_MSG_RECEIVED_MASK BIT(0)
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#define SECOCEC_STATUS_RX_ERROR_MASK BIT(1)
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#define SECOCEC_STATUS_MSG_SENT_MASK BIT(2)
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#define SECOCEC_STATUS_TX_ERROR_MASK BIT(3)
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#define SECOCEC_STATUS_TX_NACK_ERROR BIT(4)
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#define SECOCEC_STATUS_RX_OVERFLOW_MASK BIT(5)
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#endif /* __SECO_CEC_H__ */
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