// SPDX-License-Identifier: GPL-2.0+
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/*
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* Driver for Amlogic Meson AO CEC G12A Controller
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*
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* Copyright (C) 2017 Amlogic, Inc. All rights reserved
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/regmap.h>
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#include <media/cec.h>
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#include <media/cec-notifier.h>
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#include <linux/clk-provider.h>
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/* CEC Registers */
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#define CECB_CLK_CNTL_REG0 0x00
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#define CECB_CLK_CNTL_N1 GENMASK(11, 0)
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#define CECB_CLK_CNTL_N2 GENMASK(23, 12)
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#define CECB_CLK_CNTL_DUAL_EN BIT(28)
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#define CECB_CLK_CNTL_OUTPUT_EN BIT(30)
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#define CECB_CLK_CNTL_INPUT_EN BIT(31)
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#define CECB_CLK_CNTL_REG1 0x04
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#define CECB_CLK_CNTL_M1 GENMASK(11, 0)
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#define CECB_CLK_CNTL_M2 GENMASK(23, 12)
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#define CECB_CLK_CNTL_BYPASS_EN BIT(24)
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/*
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* [14:12] Filter_del. For glitch-filtering CEC line, ignore signal
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* change pulse width < filter_del * T(filter_tick) * 3.
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* [9:8] Filter_tick_sel: Select which periodical pulse for
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* glitch-filtering CEC line signal.
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* - 0=Use T(xtal)*3 = 125ns;
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* - 1=Use once-per-1us pulse;
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* - 2=Use once-per-10us pulse;
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* - 3=Use once-per-100us pulse.
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* [3] Sysclk_en. 0=Disable system clock; 1=Enable system clock.
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* [2:1] cntl_clk
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* - 0 = Disable clk (Power-off mode)
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* - 1 = Enable gated clock (Normal mode)
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* - 2 = Enable free-run clk (Debug mode)
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* [0] SW_RESET 1=Apply reset; 0=No reset.
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*/
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#define CECB_GEN_CNTL_REG 0x08
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#define CECB_GEN_CNTL_RESET BIT(0)
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#define CECB_GEN_CNTL_CLK_DISABLE 0
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#define CECB_GEN_CNTL_CLK_ENABLE 1
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#define CECB_GEN_CNTL_CLK_ENABLE_DBG 2
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#define CECB_GEN_CNTL_CLK_CTRL_MASK GENMASK(2, 1)
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#define CECB_GEN_CNTL_SYS_CLK_EN BIT(3)
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#define CECB_GEN_CNTL_FILTER_TICK_125NS 0
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#define CECB_GEN_CNTL_FILTER_TICK_1US 1
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#define CECB_GEN_CNTL_FILTER_TICK_10US 2
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#define CECB_GEN_CNTL_FILTER_TICK_100US 3
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#define CECB_GEN_CNTL_FILTER_TICK_SEL GENMASK(9, 8)
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#define CECB_GEN_CNTL_FILTER_DEL GENMASK(14, 12)
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/*
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* [7:0] cec_reg_addr
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* [15:8] cec_reg_wrdata
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* [16] cec_reg_wr
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* - 0 = Read
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* - 1 = Write
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* [31:24] cec_reg_rddata
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*/
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#define CECB_RW_REG 0x0c
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#define CECB_RW_ADDR GENMASK(7, 0)
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#define CECB_RW_WR_DATA GENMASK(15, 8)
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#define CECB_RW_WRITE_EN BIT(16)
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#define CECB_RW_BUS_BUSY BIT(23)
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#define CECB_RW_RD_DATA GENMASK(31, 24)
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/*
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* [0] DONE Interrupt
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* [1] End Of Message Interrupt
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* [2] Not Acknowlegde Interrupt
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* [3] Arbitration Loss Interrupt
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* [4] Initiator Error Interrupt
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* [5] Follower Error Interrupt
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* [6] Wake-Up Interrupt
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*/
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#define CECB_INTR_MASKN_REG 0x10
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#define CECB_INTR_CLR_REG 0x14
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#define CECB_INTR_STAT_REG 0x18
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#define CECB_INTR_DONE BIT(0)
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#define CECB_INTR_EOM BIT(1)
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#define CECB_INTR_NACK BIT(2)
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#define CECB_INTR_ARB_LOSS BIT(3)
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#define CECB_INTR_INITIATOR_ERR BIT(4)
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#define CECB_INTR_FOLLOWER_ERR BIT(5)
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#define CECB_INTR_WAKE_UP BIT(6)
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/* CEC Commands */
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#define CECB_CTRL 0x00
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#define CECB_CTRL_SEND BIT(0)
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#define CECB_CTRL_TYPE GENMASK(2, 1)
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#define CECB_CTRL_TYPE_RETRY 0
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#define CECB_CTRL_TYPE_NEW 1
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#define CECB_CTRL_TYPE_NEXT 2
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#define CECB_CTRL2 0x01
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#define CECB_CTRL2_RISE_DEL_MAX GENMASK(4, 0)
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#define CECB_INTR_MASK 0x02
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#define CECB_LADD_LOW 0x05
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#define CECB_LADD_HIGH 0x06
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#define CECB_TX_CNT 0x07
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#define CECB_RX_CNT 0x08
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#define CECB_STAT0 0x09
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#define CECB_TX_DATA00 0x10
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#define CECB_TX_DATA01 0x11
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#define CECB_TX_DATA02 0x12
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#define CECB_TX_DATA03 0x13
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#define CECB_TX_DATA04 0x14
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#define CECB_TX_DATA05 0x15
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#define CECB_TX_DATA06 0x16
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#define CECB_TX_DATA07 0x17
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#define CECB_TX_DATA08 0x18
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#define CECB_TX_DATA09 0x19
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#define CECB_TX_DATA10 0x1A
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#define CECB_TX_DATA11 0x1B
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#define CECB_TX_DATA12 0x1C
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#define CECB_TX_DATA13 0x1D
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#define CECB_TX_DATA14 0x1E
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#define CECB_TX_DATA15 0x1F
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#define CECB_RX_DATA00 0x20
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#define CECB_RX_DATA01 0x21
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#define CECB_RX_DATA02 0x22
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#define CECB_RX_DATA03 0x23
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#define CECB_RX_DATA04 0x24
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#define CECB_RX_DATA05 0x25
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#define CECB_RX_DATA06 0x26
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#define CECB_RX_DATA07 0x27
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#define CECB_RX_DATA08 0x28
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#define CECB_RX_DATA09 0x29
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#define CECB_RX_DATA10 0x2A
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#define CECB_RX_DATA11 0x2B
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#define CECB_RX_DATA12 0x2C
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#define CECB_RX_DATA13 0x2D
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#define CECB_RX_DATA14 0x2E
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#define CECB_RX_DATA15 0x2F
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#define CECB_LOCK_BUF 0x30
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#define CECB_LOCK_BUF_EN BIT(0)
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#define CECB_WAKEUPCTRL 0x31
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struct meson_ao_cec_g12a_data {
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/* Setup the internal CECB_CTRL2 register */
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bool ctrl2_setup;
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};
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struct meson_ao_cec_g12a_device {
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struct platform_device *pdev;
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struct regmap *regmap;
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struct regmap *regmap_cec;
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spinlock_t cec_reg_lock;
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struct cec_notifier *notify;
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struct cec_adapter *adap;
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struct cec_msg rx_msg;
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struct clk *oscin;
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struct clk *core;
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const struct meson_ao_cec_g12a_data *data;
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};
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static const struct regmap_config meson_ao_cec_g12a_regmap_conf = {
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.reg_bits = 8,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = CECB_INTR_STAT_REG,
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};
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/*
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* The AO-CECB embeds a dual/divider to generate a more precise
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* 32,768KHz clock for CEC core clock.
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* ______ ______
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* | | | |
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* ______ | Div1 |-| Cnt1 | ______
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* | | /|______| |______|\ | |
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* Xtal-->| Gate |---| ______ ______ X-X--| Gate |-->
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* |______| | \| | | |/ | |______|
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* | | Div2 |-| Cnt2 | |
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* | |______| |______| |
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* |_______________________|
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*
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* The dividing can be switched to single or dual, with a counter
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* for each divider to set when the switching is done.
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* The entire dividing mechanism can be also bypassed.
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*/
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struct meson_ao_cec_g12a_dualdiv_clk {
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struct clk_hw hw;
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struct regmap *regmap;
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};
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#define hw_to_meson_ao_cec_g12a_dualdiv_clk(_hw) \
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container_of(_hw, struct meson_ao_cec_g12a_dualdiv_clk, hw) \
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static unsigned long
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meson_ao_cec_g12a_dualdiv_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct meson_ao_cec_g12a_dualdiv_clk *dualdiv_clk =
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hw_to_meson_ao_cec_g12a_dualdiv_clk(hw);
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unsigned long n1;
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u32 reg0, reg1;
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regmap_read(dualdiv_clk->regmap, CECB_CLK_CNTL_REG0, ®0);
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regmap_read(dualdiv_clk->regmap, CECB_CLK_CNTL_REG0, ®1);
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if (reg1 & CECB_CLK_CNTL_BYPASS_EN)
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return parent_rate;
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if (reg0 & CECB_CLK_CNTL_DUAL_EN) {
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unsigned long n2, m1, m2, f1, f2, p1, p2;
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n1 = FIELD_GET(CECB_CLK_CNTL_N1, reg0) + 1;
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n2 = FIELD_GET(CECB_CLK_CNTL_N2, reg0) + 1;
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m1 = FIELD_GET(CECB_CLK_CNTL_M1, reg1) + 1;
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m2 = FIELD_GET(CECB_CLK_CNTL_M1, reg1) + 1;
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f1 = DIV_ROUND_CLOSEST(parent_rate, n1);
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f2 = DIV_ROUND_CLOSEST(parent_rate, n2);
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p1 = DIV_ROUND_CLOSEST(100000000 * m1, f1 * (m1 + m2));
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p2 = DIV_ROUND_CLOSEST(100000000 * m2, f2 * (m1 + m2));
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return DIV_ROUND_UP(100000000, p1 + p2);
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}
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n1 = FIELD_GET(CECB_CLK_CNTL_N1, reg0) + 1;
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return DIV_ROUND_CLOSEST(parent_rate, n1);
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}
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static int meson_ao_cec_g12a_dualdiv_clk_enable(struct clk_hw *hw)
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{
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struct meson_ao_cec_g12a_dualdiv_clk *dualdiv_clk =
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hw_to_meson_ao_cec_g12a_dualdiv_clk(hw);
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/* Disable Input & Output */
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regmap_update_bits(dualdiv_clk->regmap, CECB_CLK_CNTL_REG0,
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CECB_CLK_CNTL_INPUT_EN | CECB_CLK_CNTL_OUTPUT_EN,
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0);
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/* Set N1 & N2 */
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regmap_update_bits(dualdiv_clk->regmap, CECB_CLK_CNTL_REG0,
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CECB_CLK_CNTL_N1,
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FIELD_PREP(CECB_CLK_CNTL_N1, 733 - 1));
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regmap_update_bits(dualdiv_clk->regmap, CECB_CLK_CNTL_REG0,
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CECB_CLK_CNTL_N2,
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FIELD_PREP(CECB_CLK_CNTL_N2, 732 - 1));
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/* Set M1 & M2 */
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regmap_update_bits(dualdiv_clk->regmap, CECB_CLK_CNTL_REG1,
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CECB_CLK_CNTL_M1,
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FIELD_PREP(CECB_CLK_CNTL_M1, 8 - 1));
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regmap_update_bits(dualdiv_clk->regmap, CECB_CLK_CNTL_REG1,
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CECB_CLK_CNTL_M2,
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FIELD_PREP(CECB_CLK_CNTL_M2, 11 - 1));
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/* Enable Dual divisor */
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regmap_update_bits(dualdiv_clk->regmap, CECB_CLK_CNTL_REG0,
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CECB_CLK_CNTL_DUAL_EN, CECB_CLK_CNTL_DUAL_EN);
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/* Disable divisor bypass */
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regmap_update_bits(dualdiv_clk->regmap, CECB_CLK_CNTL_REG1,
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CECB_CLK_CNTL_BYPASS_EN, 0);
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/* Enable Input & Output */
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regmap_update_bits(dualdiv_clk->regmap, CECB_CLK_CNTL_REG0,
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CECB_CLK_CNTL_INPUT_EN | CECB_CLK_CNTL_OUTPUT_EN,
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CECB_CLK_CNTL_INPUT_EN | CECB_CLK_CNTL_OUTPUT_EN);
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return 0;
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}
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static void meson_ao_cec_g12a_dualdiv_clk_disable(struct clk_hw *hw)
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{
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struct meson_ao_cec_g12a_dualdiv_clk *dualdiv_clk =
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hw_to_meson_ao_cec_g12a_dualdiv_clk(hw);
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regmap_update_bits(dualdiv_clk->regmap, CECB_CLK_CNTL_REG0,
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CECB_CLK_CNTL_INPUT_EN | CECB_CLK_CNTL_OUTPUT_EN,
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0);
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}
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static int meson_ao_cec_g12a_dualdiv_clk_is_enabled(struct clk_hw *hw)
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{
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struct meson_ao_cec_g12a_dualdiv_clk *dualdiv_clk =
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hw_to_meson_ao_cec_g12a_dualdiv_clk(hw);
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int val;
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regmap_read(dualdiv_clk->regmap, CECB_CLK_CNTL_REG0, &val);
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return !!(val & (CECB_CLK_CNTL_INPUT_EN | CECB_CLK_CNTL_OUTPUT_EN));
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}
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static const struct clk_ops meson_ao_cec_g12a_dualdiv_clk_ops = {
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.recalc_rate = meson_ao_cec_g12a_dualdiv_clk_recalc_rate,
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.is_enabled = meson_ao_cec_g12a_dualdiv_clk_is_enabled,
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.enable = meson_ao_cec_g12a_dualdiv_clk_enable,
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.disable = meson_ao_cec_g12a_dualdiv_clk_disable,
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};
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static int meson_ao_cec_g12a_setup_clk(struct meson_ao_cec_g12a_device *ao_cec)
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{
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struct meson_ao_cec_g12a_dualdiv_clk *dualdiv_clk;
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struct device *dev = &ao_cec->pdev->dev;
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struct clk_init_data init;
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const char *parent_name;
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struct clk *clk;
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char *name;
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dualdiv_clk = devm_kzalloc(dev, sizeof(*dualdiv_clk), GFP_KERNEL);
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if (!dualdiv_clk)
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return -ENOMEM;
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name = kasprintf(GFP_KERNEL, "%s#dualdiv_clk", dev_name(dev));
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if (!name)
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return -ENOMEM;
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parent_name = __clk_get_name(ao_cec->oscin);
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init.name = name;
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init.ops = &meson_ao_cec_g12a_dualdiv_clk_ops;
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init.flags = 0;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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dualdiv_clk->regmap = ao_cec->regmap;
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dualdiv_clk->hw.init = &init;
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clk = devm_clk_register(dev, &dualdiv_clk->hw);
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kfree(name);
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if (IS_ERR(clk)) {
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dev_err(dev, "failed to register clock\n");
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return PTR_ERR(clk);
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}
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ao_cec->core = clk;
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return 0;
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}
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static int meson_ao_cec_g12a_read(void *context, unsigned int addr,
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unsigned int *data)
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{
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struct meson_ao_cec_g12a_device *ao_cec = context;
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u32 reg = FIELD_PREP(CECB_RW_ADDR, addr);
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int ret = 0;
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ret = regmap_write(ao_cec->regmap, CECB_RW_REG, reg);
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if (ret)
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return ret;
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ret = regmap_read_poll_timeout(ao_cec->regmap, CECB_RW_REG, reg,
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!(reg & CECB_RW_BUS_BUSY),
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5, 1000);
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if (ret)
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return ret;
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ret = regmap_read(ao_cec->regmap, CECB_RW_REG, ®);
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*data = FIELD_GET(CECB_RW_RD_DATA, reg);
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return ret;
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}
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static int meson_ao_cec_g12a_write(void *context, unsigned int addr,
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unsigned int data)
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{
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struct meson_ao_cec_g12a_device *ao_cec = context;
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u32 reg = FIELD_PREP(CECB_RW_ADDR, addr) |
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FIELD_PREP(CECB_RW_WR_DATA, data) |
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CECB_RW_WRITE_EN;
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return regmap_write(ao_cec->regmap, CECB_RW_REG, reg);
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}
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static const struct regmap_config meson_ao_cec_g12a_cec_regmap_conf = {
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.reg_bits = 8,
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.val_bits = 8,
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.reg_read = meson_ao_cec_g12a_read,
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.reg_write = meson_ao_cec_g12a_write,
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.max_register = 0xffff,
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};
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static inline void
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meson_ao_cec_g12a_irq_setup(struct meson_ao_cec_g12a_device *ao_cec,
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bool enable)
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{
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u32 cfg = CECB_INTR_DONE | CECB_INTR_EOM | CECB_INTR_NACK |
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CECB_INTR_ARB_LOSS | CECB_INTR_INITIATOR_ERR |
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CECB_INTR_FOLLOWER_ERR;
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regmap_write(ao_cec->regmap, CECB_INTR_MASKN_REG,
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enable ? cfg : 0);
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}
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static void meson_ao_cec_g12a_irq_rx(struct meson_ao_cec_g12a_device *ao_cec)
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{
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int i, ret = 0;
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u32 val;
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ret = regmap_read(ao_cec->regmap_cec, CECB_RX_CNT, &val);
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ao_cec->rx_msg.len = val;
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if (ao_cec->rx_msg.len > CEC_MAX_MSG_SIZE)
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ao_cec->rx_msg.len = CEC_MAX_MSG_SIZE;
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for (i = 0; i < ao_cec->rx_msg.len; i++) {
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ret |= regmap_read(ao_cec->regmap_cec,
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CECB_RX_DATA00 + i, &val);
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ao_cec->rx_msg.msg[i] = val & 0xff;
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}
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ret |= regmap_write(ao_cec->regmap_cec, CECB_LOCK_BUF, 0);
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if (ret)
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return;
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cec_received_msg(ao_cec->adap, &ao_cec->rx_msg);
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}
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static irqreturn_t meson_ao_cec_g12a_irq(int irq, void *data)
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{
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struct meson_ao_cec_g12a_device *ao_cec = data;
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u32 stat;
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regmap_read(ao_cec->regmap, CECB_INTR_STAT_REG, &stat);
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if (stat)
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return IRQ_WAKE_THREAD;
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return IRQ_NONE;
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}
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static irqreturn_t meson_ao_cec_g12a_irq_thread(int irq, void *data)
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{
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struct meson_ao_cec_g12a_device *ao_cec = data;
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u32 stat;
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regmap_read(ao_cec->regmap, CECB_INTR_STAT_REG, &stat);
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regmap_write(ao_cec->regmap, CECB_INTR_CLR_REG, stat);
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if (stat & CECB_INTR_DONE)
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cec_transmit_attempt_done(ao_cec->adap, CEC_TX_STATUS_OK);
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if (stat & CECB_INTR_EOM)
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meson_ao_cec_g12a_irq_rx(ao_cec);
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if (stat & CECB_INTR_NACK)
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cec_transmit_attempt_done(ao_cec->adap, CEC_TX_STATUS_NACK);
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if (stat & CECB_INTR_ARB_LOSS) {
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regmap_write(ao_cec->regmap_cec, CECB_TX_CNT, 0);
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regmap_update_bits(ao_cec->regmap_cec, CECB_CTRL,
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CECB_CTRL_SEND | CECB_CTRL_TYPE, 0);
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cec_transmit_attempt_done(ao_cec->adap, CEC_TX_STATUS_ARB_LOST);
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}
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/* Initiator reports an error on the CEC bus */
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if (stat & CECB_INTR_INITIATOR_ERR)
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cec_transmit_attempt_done(ao_cec->adap, CEC_TX_STATUS_ERROR);
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/* Follower reports a receive error, just reset RX buffer */
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if (stat & CECB_INTR_FOLLOWER_ERR)
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regmap_write(ao_cec->regmap_cec, CECB_LOCK_BUF, 0);
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return IRQ_HANDLED;
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}
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static int
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meson_ao_cec_g12a_set_log_addr(struct cec_adapter *adap, u8 logical_addr)
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{
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struct meson_ao_cec_g12a_device *ao_cec = adap->priv;
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int ret = 0;
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if (logical_addr == CEC_LOG_ADDR_INVALID) {
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/* Assume this will allways succeed */
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regmap_write(ao_cec->regmap_cec, CECB_LADD_LOW, 0);
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regmap_write(ao_cec->regmap_cec, CECB_LADD_HIGH, 0);
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return 0;
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} else if (logical_addr < 8) {
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ret = regmap_update_bits(ao_cec->regmap_cec, CECB_LADD_LOW,
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BIT(logical_addr),
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BIT(logical_addr));
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} else {
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ret = regmap_update_bits(ao_cec->regmap_cec, CECB_LADD_HIGH,
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BIT(logical_addr - 8),
|
BIT(logical_addr - 8));
|
}
|
|
/* Always set Broadcast/Unregistered 15 address */
|
ret |= regmap_update_bits(ao_cec->regmap_cec, CECB_LADD_HIGH,
|
BIT(CEC_LOG_ADDR_UNREGISTERED - 8),
|
BIT(CEC_LOG_ADDR_UNREGISTERED - 8));
|
|
return ret ? -EIO : 0;
|
}
|
|
static int meson_ao_cec_g12a_transmit(struct cec_adapter *adap, u8 attempts,
|
u32 signal_free_time, struct cec_msg *msg)
|
{
|
struct meson_ao_cec_g12a_device *ao_cec = adap->priv;
|
unsigned int type;
|
int ret = 0;
|
u32 val;
|
int i;
|
|
/* Check if RX is in progress */
|
ret = regmap_read(ao_cec->regmap_cec, CECB_LOCK_BUF, &val);
|
if (ret)
|
return ret;
|
if (val & CECB_LOCK_BUF_EN)
|
return -EBUSY;
|
|
/* Check if TX Busy */
|
ret = regmap_read(ao_cec->regmap_cec, CECB_CTRL, &val);
|
if (ret)
|
return ret;
|
if (val & CECB_CTRL_SEND)
|
return -EBUSY;
|
|
switch (signal_free_time) {
|
case CEC_SIGNAL_FREE_TIME_RETRY:
|
type = CECB_CTRL_TYPE_RETRY;
|
break;
|
case CEC_SIGNAL_FREE_TIME_NEXT_XFER:
|
type = CECB_CTRL_TYPE_NEXT;
|
break;
|
case CEC_SIGNAL_FREE_TIME_NEW_INITIATOR:
|
default:
|
type = CECB_CTRL_TYPE_NEW;
|
break;
|
}
|
|
for (i = 0; i < msg->len; i++)
|
ret |= regmap_write(ao_cec->regmap_cec, CECB_TX_DATA00 + i,
|
msg->msg[i]);
|
|
ret |= regmap_write(ao_cec->regmap_cec, CECB_TX_CNT, msg->len);
|
if (ret)
|
return -EIO;
|
|
ret = regmap_update_bits(ao_cec->regmap_cec, CECB_CTRL,
|
CECB_CTRL_SEND |
|
CECB_CTRL_TYPE,
|
CECB_CTRL_SEND |
|
FIELD_PREP(CECB_CTRL_TYPE, type));
|
|
return ret;
|
}
|
|
static int meson_ao_cec_g12a_adap_enable(struct cec_adapter *adap, bool enable)
|
{
|
struct meson_ao_cec_g12a_device *ao_cec = adap->priv;
|
|
meson_ao_cec_g12a_irq_setup(ao_cec, false);
|
|
regmap_update_bits(ao_cec->regmap, CECB_GEN_CNTL_REG,
|
CECB_GEN_CNTL_RESET, CECB_GEN_CNTL_RESET);
|
|
if (!enable)
|
return 0;
|
|
/* Setup Filter */
|
regmap_update_bits(ao_cec->regmap, CECB_GEN_CNTL_REG,
|
CECB_GEN_CNTL_FILTER_TICK_SEL |
|
CECB_GEN_CNTL_FILTER_DEL,
|
FIELD_PREP(CECB_GEN_CNTL_FILTER_TICK_SEL,
|
CECB_GEN_CNTL_FILTER_TICK_1US) |
|
FIELD_PREP(CECB_GEN_CNTL_FILTER_DEL, 7));
|
|
/* Enable System Clock */
|
regmap_update_bits(ao_cec->regmap, CECB_GEN_CNTL_REG,
|
CECB_GEN_CNTL_SYS_CLK_EN,
|
CECB_GEN_CNTL_SYS_CLK_EN);
|
|
/* Enable gated clock (Normal mode). */
|
regmap_update_bits(ao_cec->regmap, CECB_GEN_CNTL_REG,
|
CECB_GEN_CNTL_CLK_CTRL_MASK,
|
FIELD_PREP(CECB_GEN_CNTL_CLK_CTRL_MASK,
|
CECB_GEN_CNTL_CLK_ENABLE));
|
|
/* Release Reset */
|
regmap_update_bits(ao_cec->regmap, CECB_GEN_CNTL_REG,
|
CECB_GEN_CNTL_RESET, 0);
|
|
if (ao_cec->data->ctrl2_setup)
|
regmap_write(ao_cec->regmap_cec, CECB_CTRL2,
|
FIELD_PREP(CECB_CTRL2_RISE_DEL_MAX, 2));
|
|
meson_ao_cec_g12a_irq_setup(ao_cec, true);
|
|
return 0;
|
}
|
|
static const struct cec_adap_ops meson_ao_cec_g12a_ops = {
|
.adap_enable = meson_ao_cec_g12a_adap_enable,
|
.adap_log_addr = meson_ao_cec_g12a_set_log_addr,
|
.adap_transmit = meson_ao_cec_g12a_transmit,
|
};
|
|
static int meson_ao_cec_g12a_probe(struct platform_device *pdev)
|
{
|
struct meson_ao_cec_g12a_device *ao_cec;
|
struct device *hdmi_dev;
|
struct resource *res;
|
void __iomem *base;
|
int ret, irq;
|
|
hdmi_dev = cec_notifier_parse_hdmi_phandle(&pdev->dev);
|
if (IS_ERR(hdmi_dev))
|
return PTR_ERR(hdmi_dev);
|
|
ao_cec = devm_kzalloc(&pdev->dev, sizeof(*ao_cec), GFP_KERNEL);
|
if (!ao_cec)
|
return -ENOMEM;
|
|
ao_cec->data = of_device_get_match_data(&pdev->dev);
|
if (!ao_cec->data) {
|
dev_err(&pdev->dev, "failed to get match data\n");
|
return -ENODEV;
|
}
|
|
spin_lock_init(&ao_cec->cec_reg_lock);
|
ao_cec->pdev = pdev;
|
|
ao_cec->adap = cec_allocate_adapter(&meson_ao_cec_g12a_ops, ao_cec,
|
"meson_g12a_ao_cec",
|
CEC_CAP_DEFAULTS |
|
CEC_CAP_CONNECTOR_INFO,
|
CEC_MAX_LOG_ADDRS);
|
if (IS_ERR(ao_cec->adap))
|
return PTR_ERR(ao_cec->adap);
|
|
ao_cec->adap->owner = THIS_MODULE;
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
base = devm_ioremap_resource(&pdev->dev, res);
|
if (IS_ERR(base)) {
|
ret = PTR_ERR(base);
|
goto out_probe_adapter;
|
}
|
|
ao_cec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
|
&meson_ao_cec_g12a_regmap_conf);
|
if (IS_ERR(ao_cec->regmap)) {
|
ret = PTR_ERR(ao_cec->regmap);
|
goto out_probe_adapter;
|
}
|
|
ao_cec->regmap_cec = devm_regmap_init(&pdev->dev, NULL, ao_cec,
|
&meson_ao_cec_g12a_cec_regmap_conf);
|
if (IS_ERR(ao_cec->regmap_cec)) {
|
ret = PTR_ERR(ao_cec->regmap_cec);
|
goto out_probe_adapter;
|
}
|
|
irq = platform_get_irq(pdev, 0);
|
ret = devm_request_threaded_irq(&pdev->dev, irq,
|
meson_ao_cec_g12a_irq,
|
meson_ao_cec_g12a_irq_thread,
|
0, NULL, ao_cec);
|
if (ret) {
|
dev_err(&pdev->dev, "irq request failed\n");
|
goto out_probe_adapter;
|
}
|
|
ao_cec->oscin = devm_clk_get(&pdev->dev, "oscin");
|
if (IS_ERR(ao_cec->oscin)) {
|
dev_err(&pdev->dev, "oscin clock request failed\n");
|
ret = PTR_ERR(ao_cec->oscin);
|
goto out_probe_adapter;
|
}
|
|
ret = meson_ao_cec_g12a_setup_clk(ao_cec);
|
if (ret)
|
goto out_probe_adapter;
|
|
ret = clk_prepare_enable(ao_cec->core);
|
if (ret) {
|
dev_err(&pdev->dev, "core clock enable failed\n");
|
goto out_probe_adapter;
|
}
|
|
device_reset_optional(&pdev->dev);
|
|
platform_set_drvdata(pdev, ao_cec);
|
|
ao_cec->notify = cec_notifier_cec_adap_register(hdmi_dev, NULL,
|
ao_cec->adap);
|
if (!ao_cec->notify) {
|
ret = -ENOMEM;
|
goto out_probe_core_clk;
|
}
|
|
ret = cec_register_adapter(ao_cec->adap, &pdev->dev);
|
if (ret < 0)
|
goto out_probe_notify;
|
|
/* Setup Hardware */
|
regmap_write(ao_cec->regmap, CECB_GEN_CNTL_REG, CECB_GEN_CNTL_RESET);
|
|
return 0;
|
|
out_probe_notify:
|
cec_notifier_cec_adap_unregister(ao_cec->notify, ao_cec->adap);
|
|
out_probe_core_clk:
|
clk_disable_unprepare(ao_cec->core);
|
|
out_probe_adapter:
|
cec_delete_adapter(ao_cec->adap);
|
|
dev_err(&pdev->dev, "CEC controller registration failed\n");
|
|
return ret;
|
}
|
|
static int meson_ao_cec_g12a_remove(struct platform_device *pdev)
|
{
|
struct meson_ao_cec_g12a_device *ao_cec = platform_get_drvdata(pdev);
|
|
clk_disable_unprepare(ao_cec->core);
|
|
cec_notifier_cec_adap_unregister(ao_cec->notify, ao_cec->adap);
|
|
cec_unregister_adapter(ao_cec->adap);
|
|
return 0;
|
}
|
|
static const struct meson_ao_cec_g12a_data ao_cec_g12a_data = {
|
.ctrl2_setup = false,
|
};
|
|
static const struct meson_ao_cec_g12a_data ao_cec_sm1_data = {
|
.ctrl2_setup = true,
|
};
|
|
static const struct of_device_id meson_ao_cec_g12a_of_match[] = {
|
{
|
.compatible = "amlogic,meson-g12a-ao-cec",
|
.data = &ao_cec_g12a_data,
|
},
|
{
|
.compatible = "amlogic,meson-sm1-ao-cec",
|
.data = &ao_cec_sm1_data,
|
},
|
{ /* sentinel */ }
|
};
|
MODULE_DEVICE_TABLE(of, meson_ao_cec_g12a_of_match);
|
|
static struct platform_driver meson_ao_cec_g12a_driver = {
|
.probe = meson_ao_cec_g12a_probe,
|
.remove = meson_ao_cec_g12a_remove,
|
.driver = {
|
.name = "meson-ao-cec-g12a",
|
.of_match_table = of_match_ptr(meson_ao_cec_g12a_of_match),
|
},
|
};
|
|
module_platform_driver(meson_ao_cec_g12a_driver);
|
|
MODULE_DESCRIPTION("Meson AO CEC G12A Controller driver");
|
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
|
MODULE_LICENSE("GPL");
|
