/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* cec-pin-priv.h - internal cec-pin header
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*
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* Copyright 2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
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*/
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#ifndef LINUX_CEC_PIN_PRIV_H
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#define LINUX_CEC_PIN_PRIV_H
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#include <linux/types.h>
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#include <linux/atomic.h>
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#include <media/cec-pin.h>
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enum cec_pin_state {
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/* CEC is off */
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CEC_ST_OFF,
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/* CEC is idle, waiting for Rx or Tx */
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CEC_ST_IDLE,
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/* Tx states */
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/* Pending Tx, waiting for Signal Free Time to expire */
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CEC_ST_TX_WAIT,
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/* Low-drive was detected, wait for bus to go high */
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CEC_ST_TX_WAIT_FOR_HIGH,
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/* Drive CEC low for the start bit */
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CEC_ST_TX_START_BIT_LOW,
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/* Drive CEC high for the start bit */
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CEC_ST_TX_START_BIT_HIGH,
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/* Generate a start bit period that is too short */
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CEC_ST_TX_START_BIT_HIGH_SHORT,
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/* Generate a start bit period that is too long */
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CEC_ST_TX_START_BIT_HIGH_LONG,
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/* Drive CEC low for the start bit using the custom timing */
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CEC_ST_TX_START_BIT_LOW_CUSTOM,
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/* Drive CEC high for the start bit using the custom timing */
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CEC_ST_TX_START_BIT_HIGH_CUSTOM,
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/* Drive CEC low for the 0 bit */
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CEC_ST_TX_DATA_BIT_0_LOW,
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/* Drive CEC high for the 0 bit */
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CEC_ST_TX_DATA_BIT_0_HIGH,
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/* Generate a bit period that is too short */
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CEC_ST_TX_DATA_BIT_0_HIGH_SHORT,
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/* Generate a bit period that is too long */
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CEC_ST_TX_DATA_BIT_0_HIGH_LONG,
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/* Drive CEC low for the 1 bit */
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CEC_ST_TX_DATA_BIT_1_LOW,
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/* Drive CEC high for the 1 bit */
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CEC_ST_TX_DATA_BIT_1_HIGH,
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/* Generate a bit period that is too short */
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CEC_ST_TX_DATA_BIT_1_HIGH_SHORT,
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/* Generate a bit period that is too long */
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CEC_ST_TX_DATA_BIT_1_HIGH_LONG,
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/*
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* Wait for start of sample time to check for Ack bit or first
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* four initiator bits to check for Arbitration Lost.
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*/
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CEC_ST_TX_DATA_BIT_1_HIGH_PRE_SAMPLE,
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/* Wait for end of bit period after sampling */
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CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE,
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/* Generate a bit period that is too short */
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CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_SHORT,
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/* Generate a bit period that is too long */
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CEC_ST_TX_DATA_BIT_1_HIGH_POST_SAMPLE_LONG,
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/* Drive CEC low for a data bit using the custom timing */
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CEC_ST_TX_DATA_BIT_LOW_CUSTOM,
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/* Drive CEC high for a data bit using the custom timing */
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CEC_ST_TX_DATA_BIT_HIGH_CUSTOM,
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/* Drive CEC low for a standalone pulse using the custom timing */
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CEC_ST_TX_PULSE_LOW_CUSTOM,
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/* Drive CEC high for a standalone pulse using the custom timing */
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CEC_ST_TX_PULSE_HIGH_CUSTOM,
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/* Start low drive */
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CEC_ST_TX_LOW_DRIVE,
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/* Rx states */
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/* Start bit low detected */
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CEC_ST_RX_START_BIT_LOW,
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/* Start bit high detected */
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CEC_ST_RX_START_BIT_HIGH,
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/* Wait for bit sample time */
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CEC_ST_RX_DATA_SAMPLE,
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/* Wait for earliest end of bit period after sampling */
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CEC_ST_RX_DATA_POST_SAMPLE,
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/* Wait for CEC to go low (i.e. end of bit period) */
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CEC_ST_RX_DATA_WAIT_FOR_LOW,
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/* Drive CEC low to send 0 Ack bit */
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CEC_ST_RX_ACK_LOW,
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/* End of 0 Ack time, wait for earliest end of bit period */
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CEC_ST_RX_ACK_LOW_POST,
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/* Wait for CEC to go high (i.e. end of bit period */
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CEC_ST_RX_ACK_HIGH_POST,
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/* Wait for earliest end of bit period and end of message */
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CEC_ST_RX_ACK_FINISH,
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/* Start low drive */
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CEC_ST_RX_LOW_DRIVE,
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/* Monitor pin using interrupts */
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CEC_ST_RX_IRQ,
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/* Total number of pin states */
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CEC_PIN_STATES
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};
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/* Error Injection */
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/* Error injection modes */
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#define CEC_ERROR_INJ_MODE_OFF 0
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#define CEC_ERROR_INJ_MODE_ONCE 1
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#define CEC_ERROR_INJ_MODE_ALWAYS 2
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#define CEC_ERROR_INJ_MODE_TOGGLE 3
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#define CEC_ERROR_INJ_MODE_MASK 3ULL
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/* Receive error injection options */
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#define CEC_ERROR_INJ_RX_NACK_OFFSET 0
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#define CEC_ERROR_INJ_RX_LOW_DRIVE_OFFSET 2
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#define CEC_ERROR_INJ_RX_ADD_BYTE_OFFSET 4
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#define CEC_ERROR_INJ_RX_REMOVE_BYTE_OFFSET 6
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#define CEC_ERROR_INJ_RX_ARB_LOST_OFFSET 8
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#define CEC_ERROR_INJ_RX_MASK 0xffffULL
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/* Transmit error injection options */
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#define CEC_ERROR_INJ_TX_NO_EOM_OFFSET 16
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#define CEC_ERROR_INJ_TX_EARLY_EOM_OFFSET 18
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#define CEC_ERROR_INJ_TX_SHORT_BIT_OFFSET 20
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#define CEC_ERROR_INJ_TX_LONG_BIT_OFFSET 22
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#define CEC_ERROR_INJ_TX_CUSTOM_BIT_OFFSET 24
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#define CEC_ERROR_INJ_TX_SHORT_START_OFFSET 26
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#define CEC_ERROR_INJ_TX_LONG_START_OFFSET 28
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#define CEC_ERROR_INJ_TX_CUSTOM_START_OFFSET 30
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#define CEC_ERROR_INJ_TX_LAST_BIT_OFFSET 32
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#define CEC_ERROR_INJ_TX_ADD_BYTES_OFFSET 34
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#define CEC_ERROR_INJ_TX_REMOVE_BYTE_OFFSET 36
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#define CEC_ERROR_INJ_TX_LOW_DRIVE_OFFSET 38
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#define CEC_ERROR_INJ_TX_MASK 0xffffffffffff0000ULL
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#define CEC_ERROR_INJ_RX_LOW_DRIVE_ARG_IDX 0
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#define CEC_ERROR_INJ_RX_ARB_LOST_ARG_IDX 1
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#define CEC_ERROR_INJ_TX_ADD_BYTES_ARG_IDX 2
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#define CEC_ERROR_INJ_TX_SHORT_BIT_ARG_IDX 3
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#define CEC_ERROR_INJ_TX_LONG_BIT_ARG_IDX 4
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#define CEC_ERROR_INJ_TX_CUSTOM_BIT_ARG_IDX 5
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#define CEC_ERROR_INJ_TX_LAST_BIT_ARG_IDX 6
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#define CEC_ERROR_INJ_TX_LOW_DRIVE_ARG_IDX 7
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#define CEC_ERROR_INJ_NUM_ARGS 8
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/* Special CEC op values */
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#define CEC_ERROR_INJ_OP_ANY 0x00000100
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/* The default for the low/high time of the custom pulse */
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#define CEC_TIM_CUSTOM_DEFAULT 1000
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#define CEC_NUM_PIN_EVENTS 128
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#define CEC_PIN_EVENT_FL_IS_HIGH (1 << 0)
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#define CEC_PIN_EVENT_FL_DROPPED (1 << 1)
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#define CEC_PIN_IRQ_UNCHANGED 0
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#define CEC_PIN_IRQ_DISABLE 1
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#define CEC_PIN_IRQ_ENABLE 2
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struct cec_pin {
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struct cec_adapter *adap;
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const struct cec_pin_ops *ops;
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struct task_struct *kthread;
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wait_queue_head_t kthread_waitq;
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struct hrtimer timer;
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ktime_t ts;
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unsigned int wait_usecs;
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u16 la_mask;
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bool enabled;
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bool monitor_all;
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bool rx_eom;
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bool enable_irq_failed;
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enum cec_pin_state state;
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struct cec_msg tx_msg;
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u32 tx_bit;
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bool tx_nacked;
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u32 tx_signal_free_time;
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bool tx_toggle;
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struct cec_msg rx_msg;
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u32 rx_bit;
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bool rx_toggle;
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u32 rx_start_bit_low_too_short_cnt;
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u64 rx_start_bit_low_too_short_ts;
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u32 rx_start_bit_low_too_short_delta;
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u32 rx_start_bit_too_short_cnt;
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u64 rx_start_bit_too_short_ts;
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u32 rx_start_bit_too_short_delta;
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u32 rx_start_bit_too_long_cnt;
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u32 rx_data_bit_too_short_cnt;
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u64 rx_data_bit_too_short_ts;
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u32 rx_data_bit_too_short_delta;
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u32 rx_data_bit_too_long_cnt;
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u32 rx_low_drive_cnt;
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struct cec_msg work_rx_msg;
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u8 work_tx_status;
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ktime_t work_tx_ts;
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atomic_t work_irq_change;
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atomic_t work_pin_num_events;
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unsigned int work_pin_events_wr;
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unsigned int work_pin_events_rd;
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ktime_t work_pin_ts[CEC_NUM_PIN_EVENTS];
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u8 work_pin_events[CEC_NUM_PIN_EVENTS];
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bool work_pin_events_dropped;
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u32 work_pin_events_dropped_cnt;
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ktime_t timer_ts;
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u32 timer_cnt;
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u32 timer_100ms_overruns;
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u32 timer_300ms_overruns;
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u32 timer_max_overrun;
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u32 timer_sum_overrun;
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u32 tx_custom_low_usecs;
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u32 tx_custom_high_usecs;
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bool tx_ignore_nack_until_eom;
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bool tx_custom_pulse;
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bool tx_generated_poll;
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bool tx_post_eom;
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u8 tx_extra_bytes;
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u32 tx_low_drive_cnt;
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#ifdef CONFIG_CEC_PIN_ERROR_INJ
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u64 error_inj[CEC_ERROR_INJ_OP_ANY + 1];
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u8 error_inj_args[CEC_ERROR_INJ_OP_ANY + 1][CEC_ERROR_INJ_NUM_ARGS];
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#endif
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};
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void cec_pin_start_timer(struct cec_pin *pin);
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#ifdef CONFIG_CEC_PIN_ERROR_INJ
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bool cec_pin_error_inj_parse_line(struct cec_adapter *adap, char *line);
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int cec_pin_error_inj_show(struct cec_adapter *adap, struct seq_file *sf);
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u16 cec_pin_rx_error_inj(struct cec_pin *pin);
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u16 cec_pin_tx_error_inj(struct cec_pin *pin);
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#endif
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#endif
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