/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _I8042_SNIRM_H
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#define _I8042_SNIRM_H
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#include <asm/sni.h>
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/*
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* Names.
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*/
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#define I8042_KBD_PHYS_DESC "onboard/serio0"
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#define I8042_AUX_PHYS_DESC "onboard/serio1"
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#define I8042_MUX_PHYS_DESC "onboard/serio%d"
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/*
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* IRQs.
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*/
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static int i8042_kbd_irq;
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static int i8042_aux_irq;
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#define I8042_KBD_IRQ i8042_kbd_irq
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#define I8042_AUX_IRQ i8042_aux_irq
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static void __iomem *kbd_iobase;
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#define I8042_COMMAND_REG (kbd_iobase + 0x64UL)
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#define I8042_DATA_REG (kbd_iobase + 0x60UL)
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static inline int i8042_read_data(void)
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{
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return readb(kbd_iobase + 0x60UL);
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}
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static inline int i8042_read_status(void)
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{
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return readb(kbd_iobase + 0x64UL);
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}
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static inline void i8042_write_data(int val)
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{
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writeb(val, kbd_iobase + 0x60UL);
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}
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static inline void i8042_write_command(int val)
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{
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writeb(val, kbd_iobase + 0x64UL);
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}
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static inline int i8042_platform_init(void)
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{
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/* RM200 is strange ... */
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if (sni_brd_type == SNI_BRD_RM200) {
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kbd_iobase = ioremap(0x16000000, 4);
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i8042_kbd_irq = 33;
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i8042_aux_irq = 44;
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} else {
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kbd_iobase = ioremap(0x14000000, 4);
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i8042_kbd_irq = 1;
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i8042_aux_irq = 12;
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}
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if (!kbd_iobase)
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return -ENOMEM;
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return 0;
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}
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static inline void i8042_platform_exit(void)
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{
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}
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#endif /* _I8042_SNIRM_H */
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