/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) STMicroelectronics SA 2017
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*
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* Authors: Philippe Cornu <philippe.cornu@st.com>
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* Yannick Fertre <yannick.fertre@st.com>
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* Fabien Dessenne <fabien.dessenne@st.com>
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* Mickael Reulier <mickael.reulier@st.com>
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*/
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#ifndef _LTDC_H_
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#define _LTDC_H_
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struct ltdc_caps {
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u32 hw_version; /* hardware version */
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u32 nb_layers; /* number of supported layers */
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u32 reg_ofs; /* register offset for applicable regs */
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u32 bus_width; /* bus width (32 or 64 bits) */
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const u32 *pix_fmt_hw; /* supported pixel formats */
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bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */
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int pad_max_freq_hz; /* max frequency supported by pad */
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int nb_irq; /* number of hardware interrupts */
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};
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#define LTDC_MAX_LAYER 4
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struct fps_info {
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unsigned int counter;
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ktime_t last_timestamp;
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};
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struct ltdc_device {
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void __iomem *regs;
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struct clk *pixel_clk; /* lcd pixel clock */
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struct mutex err_lock; /* protecting error_status */
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struct ltdc_caps caps;
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u32 error_status;
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u32 irq_status;
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struct fps_info plane_fpsi[LTDC_MAX_LAYER];
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struct drm_atomic_state *suspend_state;
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};
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int ltdc_load(struct drm_device *ddev);
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void ltdc_unload(struct drm_device *ddev);
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void ltdc_suspend(struct drm_device *ddev);
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int ltdc_resume(struct drm_device *ddev);
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#endif
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