// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics SA 2017
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*
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* Authors: Philippe Cornu <philippe.cornu@st.com>
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* Yannick Fertre <yannick.fertre@st.com>
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*/
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/regulator/consumer.h>
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#include <video/mipi_display.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_modes.h>
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#include <drm/drm_panel.h>
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/*** Manufacturer Command Set ***/
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#define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */
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#define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */
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#define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
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#define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
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#define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
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#define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
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/* CMD2 P0 commands (Display Options and Power) */
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#define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
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#define MCS_SGOPCTR 0x16 /* Source Bias Current */
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#define MCS_SDCTR 0x1A /* Source Output Delay Time */
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#define MCS_INVCTR 0x1B /* Inversion Type */
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#define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */
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#define MCS_SETAVDD 0x27 /* PFM Control for AVDD Output */
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#define MCS_SETAVEE 0x29 /* PFM Control for AVEE Output */
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#define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */
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#define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */
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#define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */
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#define MCS_VCMCTR 0x46 /* VCOM Output Level Control */
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#define MCS_SETVGN 0x52 /* VG M/S N Control */
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#define MCS_SETVGP 0x54 /* VG M/S P Control */
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#define MCS_SW_CTRL 0x5F /* Interface Control for PFM and MIPI */
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/* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
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#define GOA_VSTV1 0x00
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#define GOA_VSTV2 0x07
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#define GOA_VCLK1 0x0E
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#define GOA_VCLK2 0x17
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#define GOA_VCLK_OPT1 0x20
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#define GOA_BICLK1 0x2A
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#define GOA_BICLK2 0x37
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#define GOA_BICLK3 0x44
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#define GOA_BICLK4 0x4F
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#define GOA_BICLK_OPT1 0x5B
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#define GOA_BICLK_OPT2 0x60
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#define MCS_GOA_GPO1 0x6D
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#define MCS_GOA_GPO2 0x71
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#define MCS_GOA_EQ 0x74
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#define MCS_GOA_CLK_GALLON 0x7C
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#define MCS_GOA_FS_SEL0 0x7E
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#define MCS_GOA_FS_SEL1 0x87
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#define MCS_GOA_FS_SEL2 0x91
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#define MCS_GOA_FS_SEL3 0x9B
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#define MCS_GOA_BS_SEL0 0xAC
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#define MCS_GOA_BS_SEL1 0xB5
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#define MCS_GOA_BS_SEL2 0xBF
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#define MCS_GOA_BS_SEL3 0xC9
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#define MCS_GOA_BS_SEL4 0xD3
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/* CMD2 P3 commands (Gamma) */
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#define MCS_GAMMA_VP 0x60 /* Gamma VP1~VP16 */
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#define MCS_GAMMA_VN 0x70 /* Gamma VN1~VN16 */
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struct rm68200 {
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struct device *dev;
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struct drm_panel panel;
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struct gpio_desc *reset_gpio;
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struct regulator *supply;
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bool prepared;
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bool enabled;
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};
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static const struct drm_display_mode default_mode = {
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.clock = 52582,
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.hdisplay = 720,
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.hsync_start = 720 + 38,
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.hsync_end = 720 + 38 + 8,
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.htotal = 720 + 38 + 8 + 38,
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.vdisplay = 1280,
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.vsync_start = 1280 + 12,
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.vsync_end = 1280 + 12 + 4,
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.vtotal = 1280 + 12 + 4 + 12,
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.flags = 0,
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.width_mm = 68,
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.height_mm = 122,
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};
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static inline struct rm68200 *panel_to_rm68200(struct drm_panel *panel)
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{
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return container_of(panel, struct rm68200, panel);
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}
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static void rm68200_dcs_write_buf(struct rm68200 *ctx, const void *data,
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size_t len)
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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int err;
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err = mipi_dsi_dcs_write_buffer(dsi, data, len);
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if (err < 0)
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dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write buffer failed: %d\n", err);
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}
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static void rm68200_dcs_write_cmd(struct rm68200 *ctx, u8 cmd, u8 value)
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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int err;
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err = mipi_dsi_dcs_write(dsi, cmd, &value, 1);
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if (err < 0)
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dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write failed: %d\n", err);
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}
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#define dcs_write_seq(ctx, seq...) \
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({ \
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static const u8 d[] = { seq }; \
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\
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rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \
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})
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/*
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* This panel is not able to auto-increment all cmd addresses so for some of
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* them, we need to send them one by one...
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*/
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#define dcs_write_cmd_seq(ctx, cmd, seq...) \
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({ \
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static const u8 d[] = { seq }; \
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unsigned int i; \
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\
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for (i = 0; i < ARRAY_SIZE(d) ; i++) \
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rm68200_dcs_write_cmd(ctx, cmd + i, d[i]); \
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})
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static void rm68200_init_sequence(struct rm68200 *ctx)
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{
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/* Enter CMD2 with page 0 */
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dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
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dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
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dcs_write_seq(ctx, MCS_BT2CTR, 0xE5);
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dcs_write_seq(ctx, MCS_SETAVDD, 0x0A);
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dcs_write_seq(ctx, MCS_SETAVEE, 0x0A);
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dcs_write_seq(ctx, MCS_SGOPCTR, 0x52);
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dcs_write_seq(ctx, MCS_BT3CTR, 0x53);
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dcs_write_seq(ctx, MCS_BT4CTR, 0x5A);
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dcs_write_seq(ctx, MCS_INVCTR, 0x00);
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dcs_write_seq(ctx, MCS_STBCTR, 0x0A);
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dcs_write_seq(ctx, MCS_SDCTR, 0x06);
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dcs_write_seq(ctx, MCS_VCMCTR, 0x56);
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dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00);
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dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00);
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dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
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dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
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dcs_write_seq(ctx, GOA_VSTV1, 0x05);
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dcs_write_seq(ctx, 0x02, 0x0B);
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dcs_write_seq(ctx, 0x03, 0x0F);
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dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50);
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dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
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0x50);
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dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
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0x00, 0x85, 0x08);
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dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
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0x00, 0x85, 0x08);
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dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00);
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dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08);
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dcs_write_seq(ctx, 0x2D, 0x01);
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dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
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0x00);
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dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
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dcs_write_seq(ctx, 0x3D, 0x40);
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dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
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dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00);
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dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00);
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dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00);
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dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
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dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
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dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
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dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
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dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
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0x00, 0x00);
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dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
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dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
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0x16, 0x12, 0x08, 0x3F);
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dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
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0x0A, 0x0E, 0x3F, 0x3F, 0x00);
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dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
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0x05, 0x01, 0x3F, 0x3F, 0x0F);
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dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
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0x3F);
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dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
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dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F);
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dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
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0x15, 0x11, 0x0F, 0x3F);
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dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
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0x0D, 0x09, 0x3F, 0x3F, 0x07);
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dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
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0x02, 0x06, 0x3F, 0x3F, 0x08);
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dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
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0x3F, 0x3F, 0x0E, 0x10, 0x14);
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dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
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dcs_write_seq(ctx, 0xDC, 0x02);
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dcs_write_seq(ctx, 0xDE, 0x12);
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dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
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dcs_write_seq(ctx, 0x01, 0x75);
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dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
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dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
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0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
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0x12, 0x0C, 0x00);
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dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
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0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
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0x12, 0x0C, 0x00);
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/* Exit CMD2 */
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dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
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}
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static int rm68200_disable(struct drm_panel *panel)
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{
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struct rm68200 *ctx = panel_to_rm68200(panel);
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if (!ctx->enabled)
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return 0;
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ctx->enabled = false;
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return 0;
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}
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static int rm68200_unprepare(struct drm_panel *panel)
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{
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struct rm68200 *ctx = panel_to_rm68200(panel);
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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int ret;
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if (!ctx->prepared)
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return 0;
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ret = mipi_dsi_dcs_set_display_off(dsi);
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if (ret)
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dev_warn(panel->dev, "failed to set display off: %d\n", ret);
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ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
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if (ret)
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dev_warn(panel->dev, "failed to enter sleep mode: %d\n", ret);
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msleep(120);
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if (ctx->reset_gpio) {
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gpiod_set_value_cansleep(ctx->reset_gpio, 1);
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msleep(20);
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}
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regulator_disable(ctx->supply);
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ctx->prepared = false;
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return 0;
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}
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static int rm68200_prepare(struct drm_panel *panel)
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{
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struct rm68200 *ctx = panel_to_rm68200(panel);
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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int ret;
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if (ctx->prepared)
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return 0;
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ret = regulator_enable(ctx->supply);
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if (ret < 0) {
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dev_err(ctx->dev, "failed to enable supply: %d\n", ret);
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return ret;
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}
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if (ctx->reset_gpio) {
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gpiod_set_value_cansleep(ctx->reset_gpio, 1);
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msleep(20);
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gpiod_set_value_cansleep(ctx->reset_gpio, 0);
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msleep(100);
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}
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rm68200_init_sequence(ctx);
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ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
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if (ret)
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return ret;
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msleep(125);
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ret = mipi_dsi_dcs_set_display_on(dsi);
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if (ret)
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return ret;
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msleep(20);
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ctx->prepared = true;
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return 0;
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}
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static int rm68200_enable(struct drm_panel *panel)
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{
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struct rm68200 *ctx = panel_to_rm68200(panel);
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if (ctx->enabled)
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return 0;
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ctx->enabled = true;
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return 0;
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}
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static int rm68200_get_modes(struct drm_panel *panel,
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struct drm_connector *connector)
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{
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struct drm_display_mode *mode;
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mode = drm_mode_duplicate(connector->dev, &default_mode);
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if (!mode) {
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dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
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default_mode.hdisplay, default_mode.vdisplay,
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drm_mode_vrefresh(&default_mode));
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return -ENOMEM;
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}
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drm_mode_set_name(mode);
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mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
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drm_mode_probed_add(connector, mode);
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connector->display_info.width_mm = mode->width_mm;
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connector->display_info.height_mm = mode->height_mm;
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return 1;
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}
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static const struct drm_panel_funcs rm68200_drm_funcs = {
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.disable = rm68200_disable,
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.unprepare = rm68200_unprepare,
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.prepare = rm68200_prepare,
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.enable = rm68200_enable,
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.get_modes = rm68200_get_modes,
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};
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static int rm68200_probe(struct mipi_dsi_device *dsi)
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{
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struct device *dev = &dsi->dev;
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struct rm68200 *ctx;
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int ret;
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ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
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if (IS_ERR(ctx->reset_gpio)) {
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ret = PTR_ERR(ctx->reset_gpio);
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dev_err(dev, "cannot get reset GPIO: %d\n", ret);
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return ret;
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}
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ctx->supply = devm_regulator_get(dev, "power");
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if (IS_ERR(ctx->supply)) {
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ret = PTR_ERR(ctx->supply);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "cannot get regulator: %d\n", ret);
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return ret;
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}
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mipi_dsi_set_drvdata(dsi, ctx);
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ctx->dev = dev;
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dsi->lanes = 2;
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dsi->format = MIPI_DSI_FMT_RGB888;
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dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
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MIPI_DSI_MODE_LPM;
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drm_panel_init(&ctx->panel, dev, &rm68200_drm_funcs,
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DRM_MODE_CONNECTOR_DSI);
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ret = drm_panel_of_backlight(&ctx->panel);
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if (ret)
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return ret;
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drm_panel_add(&ctx->panel);
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ret = mipi_dsi_attach(dsi);
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if (ret < 0) {
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dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
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drm_panel_remove(&ctx->panel);
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return ret;
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}
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return 0;
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}
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static int rm68200_remove(struct mipi_dsi_device *dsi)
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{
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struct rm68200 *ctx = mipi_dsi_get_drvdata(dsi);
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mipi_dsi_detach(dsi);
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drm_panel_remove(&ctx->panel);
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return 0;
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}
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static const struct of_device_id raydium_rm68200_of_match[] = {
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{ .compatible = "raydium,rm68200" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, raydium_rm68200_of_match);
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static struct mipi_dsi_driver raydium_rm68200_driver = {
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.probe = rm68200_probe,
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.remove = rm68200_remove,
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.driver = {
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.name = "panel-raydium-rm68200",
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.of_match_table = raydium_rm68200_of_match,
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},
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};
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module_mipi_dsi_driver(raydium_rm68200_driver);
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MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
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MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
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MODULE_DESCRIPTION("DRM Driver for Raydium RM68200 MIPI DSI panel");
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MODULE_LICENSE("GPL v2");
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