// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*
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*/
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/ {
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compatible = "rockchip,linux", "rockchip,rk3326";
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aliases {
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mmc0 = &emmc;
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mmc1 = &sdmmc;
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mmc2 = &sdio;
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};
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootwait";
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};
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fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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rockchip,wake-irq = <0>;
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/* If enable uart uses irq instead of fiq */
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rockchip,irq-mode-enable = <1>;
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rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "okay";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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drm_logo: drm-logo@00000000 {
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compatible = "rockchip,drm-logo";
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reg = <0x0 0x0 0x0 0x0>;
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};
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ramoops: ramoops@110000 {
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compatible = "ramoops";
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reg = <0x0 0x110000 0x0 0xf0000>;
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record-size = <0x20000>;
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console-size = <0x80000>;
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ftrace-size = <0x00000>;
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pmsg-size = <0x50000>;
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};
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};
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};
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&cpu0_opp_table {
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rockchip,avs = <1>;
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};
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&display_subsystem {
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status = "disabled";
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logo-memory-region = <&drm_logo>;
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route {
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route_lvds: route-lvds {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopb_out_lvds>;
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};
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route_dsi: route-dsi {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopb_out_dsi>;
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};
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route_rgb: route-rgb {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopb_out_rgb>;
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};
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};
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};
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&rng {
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status = "okay";
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};
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&video_phy {
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status = "okay";
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};
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