/dts-v1/;
|
|
/ {
|
compatible = "rockchip,rk3588-evb7-lp4-v10", "rockchip,rk3588";
|
interrupt-parent = <0x1>;
|
#address-cells = <0x2>;
|
#size-cells = <0x2>;
|
model = "Rockchip RK3588 EVB7 LP4 V10 Board";
|
|
aliases {
|
csi2dcphy0 = "/csi2-dcphy0";
|
csi2dcphy1 = "/csi2-dcphy1";
|
csi2dphy0 = "/csi2-dphy0";
|
csi2dphy1 = "/csi2-dphy1";
|
csi2dphy2 = "/csi2-dphy2";
|
csi2dphy3 = "/csi2-dphy3";
|
csi2dphy4 = "/csi2-dphy4";
|
csi2dphy5 = "/csi2-dphy5";
|
dsi0 = "/dsi@fde20000";
|
dsi1 = "/dsi@fde30000";
|
ethernet1 = "/ethernet@fe1c0000";
|
gpio0 = "/pinctrl/gpio@fd8a0000";
|
gpio1 = "/pinctrl/gpio@fec20000";
|
gpio2 = "/pinctrl/gpio@fec30000";
|
gpio3 = "/pinctrl/gpio@fec40000";
|
gpio4 = "/pinctrl/gpio@fec50000";
|
i2c0 = "/i2c@fd880000";
|
i2c1 = "/i2c@fea90000";
|
i2c2 = "/i2c@feaa0000";
|
i2c3 = "/i2c@feab0000";
|
i2c4 = "/i2c@feac0000";
|
i2c5 = "/i2c@fead0000";
|
i2c6 = "/i2c@fec80000";
|
i2c7 = "/i2c@fec90000";
|
i2c8 = "/i2c@feca0000";
|
rkcif_mipi_lvds0 = "/rkcif-mipi-lvds";
|
rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1";
|
rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2";
|
rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3";
|
rkvdec0 = "/rkvdec-core@fdc38000";
|
rkvdec1 = "/rkvdec-core@fdc48000";
|
rkvenc0 = "/rkvenc-core@fdbd0000";
|
rkvenc1 = "/rkvenc-core@fdbe0000";
|
jpege0 = "/jpege-core@fdba0000";
|
jpege1 = "/jpege-core@fdba4000";
|
jpege2 = "/jpege-core@fdba8000";
|
jpege3 = "/jpege-core@fdbac000";
|
serial0 = "/serial@fd890000";
|
serial1 = "/serial@feb40000";
|
serial2 = "/serial@feb50000";
|
serial3 = "/serial@feb60000";
|
serial4 = "/serial@feb70000";
|
serial5 = "/serial@feb80000";
|
serial6 = "/serial@feb90000";
|
serial7 = "/serial@feba0000";
|
serial8 = "/serial@febb0000";
|
serial9 = "/serial@febc0000";
|
spi0 = "/spi@feb00000";
|
spi1 = "/spi@feb10000";
|
spi2 = "/spi@feb20000";
|
spi3 = "/spi@feb30000";
|
spi4 = "/spi@fecb0000";
|
spi5 = "/spi@fe2b0000";
|
hdcp0 = "/hdcp@fde40000";
|
hdcp1 = "/hdcp@fde70000";
|
dp0 = "/dp@fde50000";
|
dp1 = "/dp@fde60000";
|
edp0 = "/edp@fdec0000";
|
edp1 = "/edp@fded0000";
|
ethernet0 = "/ethernet@fe1b0000";
|
hdptx0 = "/phy@fed60000";
|
hdptx1 = "/phy@fed70000";
|
hdptxhdmi0 = "/hdmiphy@fed60000";
|
hdptxhdmi1 = "/hdmiphy@fed70000";
|
hdmi0 = "/hdmi@fde80000";
|
hdmi1 = "/hdmi@fdea0000";
|
hdmirx0 = "/hdmirx-controller@fdee0000";
|
rkcif_mipi_lvds4 = "/rkcif-mipi-lvds4";
|
rkcif_mipi_lvds5 = "/rkcif-mipi-lvds5";
|
usbdp0 = "/phy@fed80000";
|
usbdp1 = "/phy@fed90000";
|
mmc0 = "/mmc@fe2e0000";
|
mmc1 = "/mmc@fe2c0000";
|
mmc2 = "/mmc@fe2d0000";
|
};
|
|
clocks {
|
compatible = "simple-bus";
|
#address-cells = <0x2>;
|
#size-cells = <0x2>;
|
ranges;
|
|
spll {
|
compatible = "fixed-clock";
|
#clock-cells = <0x0>;
|
clock-frequency = <0x29d7ab80>;
|
clock-output-names = "spll";
|
phandle = <0x1ec>;
|
};
|
|
xin32k {
|
compatible = "fixed-clock";
|
#clock-cells = <0x0>;
|
clock-frequency = <0x8000>;
|
clock-output-names = "xin32k";
|
phandle = <0x1ed>;
|
};
|
|
xin24m {
|
compatible = "fixed-clock";
|
#clock-cells = <0x0>;
|
clock-frequency = <0x16e3600>;
|
clock-output-names = "xin24m";
|
phandle = <0x1ee>;
|
};
|
|
hclk_vo1@fd7c08ec {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08ec 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x264>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x5>;
|
};
|
|
aclk_vdpu_low_pre@fd7c08b0 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08b0 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x1bc>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1ef>;
|
};
|
|
hclk_vo0@fd7c08dc {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08dc 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x26d>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x4>;
|
};
|
|
hclk_usb@fd7c08a8 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08a8 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x264>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1f0>;
|
};
|
|
hclk_nvm@fd7c087c {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c087c 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x141>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x3>;
|
};
|
|
aclk_usb@fd7c08a8 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08a8 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x263>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x60>;
|
};
|
|
hclk_isp1_pre@fd7c0868 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c0868 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x1e1>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1f1>;
|
};
|
|
aclk_isp1_pre@fd7c0868 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c0868 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x1e0>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1f2>;
|
};
|
|
aclk_rkvdec0_pre@fd7c08a0 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08a0 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x1bc>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1f3>;
|
};
|
|
hclk_rkvdec0_pre@fd7c08a0 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08a0 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x1be>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1f4>;
|
};
|
|
aclk_rkvdec1_pre@fd7c08a4 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08a4 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x1bc>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1f5>;
|
};
|
|
hclk_rkvdec1_pre@fd7c08a4 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08a4 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x1be>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1f6>;
|
};
|
|
aclk_jpeg_decoder_pre@fd7c08b0 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08b0 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x1bc>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1f7>;
|
};
|
|
aclk_rkvenc1_pre@fd7c08c0 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08c0 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x1c5>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1f8>;
|
};
|
|
hclk_rkvenc1_pre@fd7c08c0 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08c0 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x1c4>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1f9>;
|
};
|
|
aclk_hdcp0_pre@fd7c08dc {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08dc 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x26c>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1fa>;
|
};
|
|
aclk_hdcp1_pre@fd7c08ec {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08ec 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x263>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1fb>;
|
};
|
|
pclk_av1_pre@fd7c0910 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c0910 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x1be>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1fc>;
|
};
|
|
aclk_av1_pre@fd7c0910 {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c0910 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x2 0x1bc>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1fd>;
|
};
|
|
hclk_sdio_pre@fd7c092c {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c092c 0x0 0x10>;
|
clock-names = "link";
|
clocks = <0x3>;
|
#power-domain-cells = <0x1>;
|
#clock-cells = <0x0>;
|
phandle = <0x1fe>;
|
};
|
|
pclk_vo0_grf@fd7c08dc {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08dc 0x0 0x4>;
|
clocks = <0x4>;
|
clock-names = "link";
|
#clock-cells = <0x0>;
|
phandle = <0x68>;
|
};
|
|
pclk_vo1_grf@fd7c08ec {
|
compatible = "rockchip,rk3588-clock-gate-link";
|
reg = <0x0 0xfd7c08ec 0x0 0x4>;
|
clocks = <0x5>;
|
clock-names = "link";
|
#clock-cells = <0x0>;
|
phandle = <0x69>;
|
};
|
|
mclkin-i2s0 {
|
compatible = "fixed-clock";
|
#clock-cells = <0x0>;
|
clock-frequency = <0x0>;
|
clock-output-names = "i2s0_mclkin";
|
phandle = <0x1ff>;
|
};
|
|
mclkin-i2s1 {
|
compatible = "fixed-clock";
|
#clock-cells = <0x0>;
|
clock-frequency = <0x0>;
|
clock-output-names = "i2s1_mclkin";
|
phandle = <0x200>;
|
};
|
|
mclkin-i2s2 {
|
compatible = "fixed-clock";
|
#clock-cells = <0x0>;
|
clock-frequency = <0x0>;
|
clock-output-names = "i2s2_mclkin";
|
phandle = <0x201>;
|
};
|
|
mclkin-i2s3 {
|
compatible = "fixed-clock";
|
#clock-cells = <0x0>;
|
clock-frequency = <0x0>;
|
clock-output-names = "i2s3_mclkin";
|
phandle = <0x202>;
|
};
|
|
mclkout-i2s0@fd58c318 {
|
compatible = "rockchip,clk-out";
|
reg = <0x0 0xfd58c318 0x0 0x4>;
|
clocks = <0x2 0x39>;
|
#clock-cells = <0x0>;
|
clock-output-names = "i2s0_mclkout_to_io";
|
rockchip,bit-shift = <0x0>;
|
rockchip,bit-set-to-disable;
|
phandle = <0x14e>;
|
};
|
|
mclkout-i2s1@fd58c318 {
|
compatible = "rockchip,clk-out";
|
reg = <0x0 0xfd58c318 0x0 0x4>;
|
clocks = <0x2 0x291>;
|
#clock-cells = <0x0>;
|
clock-output-names = "i2s1_mclkout_to_io";
|
rockchip,bit-shift = <0x1>;
|
rockchip,bit-set-to-disable;
|
phandle = <0x203>;
|
};
|
|
mclkout-i2s1@fd58a000 {
|
compatible = "rockchip,clk-out";
|
reg = <0x0 0xfd58a000 0x0 0x4>;
|
clocks = <0x2 0x291>;
|
#clock-cells = <0x0>;
|
clock-output-names = "i2s1m1_mclkout_to_io";
|
rockchip,bit-shift = <0x6>;
|
phandle = <0x204>;
|
};
|
|
mclkout-i2s2@fd58c318 {
|
compatible = "rockchip,clk-out";
|
reg = <0x0 0xfd58c318 0x0 0x4>;
|
clocks = <0x2 0x28>;
|
#clock-cells = <0x0>;
|
clock-output-names = "i2s2_mclkout_to_io";
|
rockchip,bit-shift = <0x2>;
|
rockchip,bit-set-to-disable;
|
phandle = <0x205>;
|
};
|
|
mclkout-i2s3@fd58c318 {
|
compatible = "rockchip,clk-out";
|
reg = <0x0 0xfd58c318 0x0 0x4>;
|
clocks = <0x2 0x2e>;
|
#clock-cells = <0x0>;
|
clock-output-names = "i2s3_mclkout_to_io";
|
rockchip,bit-shift = <0x7>;
|
rockchip,bit-set-to-disable;
|
phandle = <0x206>;
|
};
|
};
|
|
cpus {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
cpu-map {
|
|
cluster0 {
|
|
core0 {
|
cpu = <0x6>;
|
};
|
|
core1 {
|
cpu = <0x7>;
|
};
|
|
core2 {
|
cpu = <0x8>;
|
};
|
|
core3 {
|
cpu = <0x9>;
|
};
|
};
|
|
cluster1 {
|
|
core0 {
|
cpu = <0xa>;
|
};
|
|
core1 {
|
cpu = <0xb>;
|
};
|
};
|
|
cluster2 {
|
|
core0 {
|
cpu = <0xc>;
|
};
|
|
core1 {
|
cpu = <0xd>;
|
};
|
};
|
};
|
|
cpu@0 {
|
device_type = "cpu";
|
compatible = "arm,cortex-a55";
|
reg = <0x0>;
|
enable-method = "psci";
|
capacity-dmips-mhz = <0x212>;
|
clocks = <0xe 0x0>;
|
operating-points-v2 = <0xf>;
|
cpu-idle-states = <0x10>;
|
i-cache-size = <0x8000>;
|
i-cache-line-size = <0x40>;
|
i-cache-sets = <0x80>;
|
d-cache-size = <0x8000>;
|
d-cache-line-size = <0x40>;
|
d-cache-sets = <0x80>;
|
next-level-cache = <0x11>;
|
#cooling-cells = <0x2>;
|
dynamic-power-coefficient = <0x64>;
|
cpu-supply = <0x12>;
|
mem-supply = <0x12>;
|
phandle = <0x6>;
|
};
|
|
cpu@100 {
|
device_type = "cpu";
|
compatible = "arm,cortex-a55";
|
reg = <0x100>;
|
enable-method = "psci";
|
capacity-dmips-mhz = <0x212>;
|
clocks = <0xe 0x0>;
|
operating-points-v2 = <0xf>;
|
cpu-idle-states = <0x10>;
|
i-cache-size = <0x8000>;
|
i-cache-line-size = <0x40>;
|
i-cache-sets = <0x80>;
|
d-cache-size = <0x8000>;
|
d-cache-line-size = <0x40>;
|
d-cache-sets = <0x80>;
|
next-level-cache = <0x13>;
|
phandle = <0x7>;
|
};
|
|
cpu@200 {
|
device_type = "cpu";
|
compatible = "arm,cortex-a55";
|
reg = <0x200>;
|
enable-method = "psci";
|
capacity-dmips-mhz = <0x212>;
|
clocks = <0xe 0x0>;
|
operating-points-v2 = <0xf>;
|
cpu-idle-states = <0x10>;
|
i-cache-size = <0x8000>;
|
i-cache-line-size = <0x40>;
|
i-cache-sets = <0x80>;
|
d-cache-size = <0x8000>;
|
d-cache-line-size = <0x40>;
|
d-cache-sets = <0x80>;
|
next-level-cache = <0x14>;
|
phandle = <0x8>;
|
};
|
|
cpu@300 {
|
device_type = "cpu";
|
compatible = "arm,cortex-a55";
|
reg = <0x300>;
|
enable-method = "psci";
|
capacity-dmips-mhz = <0x212>;
|
clocks = <0xe 0x0>;
|
operating-points-v2 = <0xf>;
|
cpu-idle-states = <0x10>;
|
i-cache-size = <0x8000>;
|
i-cache-line-size = <0x40>;
|
i-cache-sets = <0x80>;
|
d-cache-size = <0x8000>;
|
d-cache-line-size = <0x40>;
|
d-cache-sets = <0x80>;
|
next-level-cache = <0x15>;
|
phandle = <0x9>;
|
};
|
|
cpu@400 {
|
device_type = "cpu";
|
compatible = "arm,cortex-a76";
|
reg = <0x400>;
|
enable-method = "psci";
|
capacity-dmips-mhz = <0x400>;
|
clocks = <0xe 0x2>;
|
operating-points-v2 = <0x16>;
|
cpu-idle-states = <0x10>;
|
i-cache-size = <0x10000>;
|
i-cache-line-size = <0x40>;
|
i-cache-sets = <0x100>;
|
d-cache-size = <0x10000>;
|
d-cache-line-size = <0x40>;
|
d-cache-sets = <0x100>;
|
next-level-cache = <0x17>;
|
#cooling-cells = <0x2>;
|
dynamic-power-coefficient = <0x12c>;
|
cpu-supply = <0x18>;
|
mem-supply = <0x18>;
|
phandle = <0xa>;
|
};
|
|
cpu@500 {
|
device_type = "cpu";
|
compatible = "arm,cortex-a76";
|
reg = <0x500>;
|
enable-method = "psci";
|
capacity-dmips-mhz = <0x400>;
|
clocks = <0xe 0x2>;
|
operating-points-v2 = <0x16>;
|
cpu-idle-states = <0x10>;
|
i-cache-size = <0x10000>;
|
i-cache-line-size = <0x40>;
|
i-cache-sets = <0x100>;
|
d-cache-size = <0x10000>;
|
d-cache-line-size = <0x40>;
|
d-cache-sets = <0x100>;
|
next-level-cache = <0x19>;
|
phandle = <0xb>;
|
};
|
|
cpu@600 {
|
device_type = "cpu";
|
compatible = "arm,cortex-a76";
|
reg = <0x600>;
|
enable-method = "psci";
|
capacity-dmips-mhz = <0x400>;
|
clocks = <0xe 0x3>;
|
operating-points-v2 = <0x1a>;
|
cpu-idle-states = <0x10>;
|
i-cache-size = <0x10000>;
|
i-cache-line-size = <0x40>;
|
i-cache-sets = <0x100>;
|
d-cache-size = <0x10000>;
|
d-cache-line-size = <0x40>;
|
d-cache-sets = <0x100>;
|
next-level-cache = <0x1b>;
|
#cooling-cells = <0x2>;
|
dynamic-power-coefficient = <0x12c>;
|
cpu-supply = <0x1c>;
|
mem-supply = <0x1c>;
|
phandle = <0xc>;
|
};
|
|
cpu@700 {
|
device_type = "cpu";
|
compatible = "arm,cortex-a76";
|
reg = <0x700>;
|
enable-method = "psci";
|
capacity-dmips-mhz = <0x400>;
|
clocks = <0xe 0x3>;
|
operating-points-v2 = <0x1a>;
|
cpu-idle-states = <0x10>;
|
i-cache-size = <0x10000>;
|
i-cache-line-size = <0x40>;
|
i-cache-sets = <0x100>;
|
d-cache-size = <0x10000>;
|
d-cache-line-size = <0x40>;
|
d-cache-sets = <0x100>;
|
next-level-cache = <0x1d>;
|
phandle = <0xd>;
|
};
|
|
idle-states {
|
entry-method = "psci";
|
|
cpu-sleep {
|
compatible = "arm,idle-state";
|
local-timer-stop;
|
arm,psci-suspend-param = <0x10000>;
|
entry-latency-us = <0x64>;
|
exit-latency-us = <0x78>;
|
min-residency-us = <0x3e8>;
|
phandle = <0x10>;
|
};
|
};
|
|
l2-cache-l0 {
|
compatible = "cache";
|
cache-size = <0x20000>;
|
cache-line-size = <0x40>;
|
cache-sets = <0x200>;
|
next-level-cache = <0x1e>;
|
phandle = <0x11>;
|
};
|
|
l2-cache-l1 {
|
compatible = "cache";
|
cache-size = <0x20000>;
|
cache-line-size = <0x40>;
|
cache-sets = <0x200>;
|
next-level-cache = <0x1e>;
|
phandle = <0x13>;
|
};
|
|
l2-cache-l2 {
|
compatible = "cache";
|
cache-size = <0x20000>;
|
cache-line-size = <0x40>;
|
cache-sets = <0x200>;
|
next-level-cache = <0x1e>;
|
phandle = <0x14>;
|
};
|
|
l2-cache-l3 {
|
compatible = "cache";
|
cache-size = <0x20000>;
|
cache-line-size = <0x40>;
|
cache-sets = <0x200>;
|
next-level-cache = <0x1e>;
|
phandle = <0x15>;
|
};
|
|
l2-cache-b0 {
|
compatible = "cache";
|
cache-size = <0x80000>;
|
cache-line-size = <0x40>;
|
cache-sets = <0x400>;
|
next-level-cache = <0x1e>;
|
phandle = <0x17>;
|
};
|
|
l2-cache-b1 {
|
compatible = "cache";
|
cache-size = <0x80000>;
|
cache-line-size = <0x40>;
|
cache-sets = <0x400>;
|
next-level-cache = <0x1e>;
|
phandle = <0x19>;
|
};
|
|
l2-cache-b2 {
|
compatible = "cache";
|
cache-size = <0x80000>;
|
cache-line-size = <0x40>;
|
cache-sets = <0x400>;
|
next-level-cache = <0x1e>;
|
phandle = <0x1b>;
|
};
|
|
l2-cache-b3 {
|
compatible = "cache";
|
cache-size = <0x80000>;
|
cache-line-size = <0x40>;
|
cache-sets = <0x400>;
|
next-level-cache = <0x1e>;
|
phandle = <0x1d>;
|
};
|
|
l3-cache {
|
compatible = "cache";
|
cache-size = <0x300000>;
|
cache-line-size = <0x40>;
|
cache-sets = <0x1000>;
|
phandle = <0x1e>;
|
};
|
};
|
|
cluster0-opp-table {
|
compatible = "operating-points-v2";
|
opp-shared;
|
nvmem-cells = <0x1f 0x20 0x21>;
|
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
|
rockchip,supported-hw;
|
rockchip,opp-shared-dsu;
|
rockchip,pvtm-hw = <0x6>;
|
rockchip,pvtm-voltage-sel-hw = <0x0 0x555 0x0 0x556 0x56b 0x1 0x56c 0x581 0x2 0x582 0x597 0x3 0x598 0x5ad 0x4 0x5ae 0x5c3 0x5 0x5c4 0x270f 0x6>;
|
rockchip,pvtm-voltage-sel = <0x0 0x582 0x0 0x583 0x59a 0x1 0x59b 0x5b2 0x2 0x5b3 0x5ca 0x3 0x5cb 0x5e2 0x4 0x5e3 0x5fa 0x5 0x5fb 0x270f 0x6>;
|
rockchip,pvtm-pvtpll;
|
rockchip,pvtm-offset = <0x64>;
|
rockchip,pvtm-sample-time = <0x44c>;
|
rockchip,pvtm-freq = <0x159b40>;
|
rockchip,pvtm-volt = <0xb71b0>;
|
rockchip,pvtm-ref-temp = <0x19>;
|
rockchip,pvtm-temp-prop = <0xf4 0xf4>;
|
rockchip,pvtm-thermal-zone = "soc-thermal";
|
rockchip,grf = <0x22>;
|
rockchip,dsu-grf = <0x23>;
|
volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>;
|
low-volt-mem-read-margin = <0x4>;
|
intermediate-threshold-freq = <0xf6180>;
|
rockchip,reboot-freq = <0x159b40>;
|
rockchip,temp-hysteresis = <0x1388>;
|
rockchip,low-temp = <0x2710>;
|
rockchip,low-temp-min-volt = <0xb71b0>;
|
rockchip,high-temp = <0x14c08>;
|
rockchip,high-temp-max-freq = <0x188940>;
|
phandle = <0xf>;
|
|
opp-408000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x18519600>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-600000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x23c34600>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-816000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x30a32c00>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1008000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x3c14dc00>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1200000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x47868c00>;
|
opp-microvolt = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>;
|
opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>;
|
opp-microvolt-L2 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>;
|
opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>;
|
opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
|
opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
|
opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1416000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x54667200>;
|
opp-microvolt = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>;
|
opp-microvolt-L1 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
opp-microvolt-L2 = <0xb40dc 0xb40dc 0xe7ef0 0xb40dc 0xb40dc 0xe7ef0>;
|
opp-microvolt-L3 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>;
|
opp-microvolt-L4 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>;
|
opp-microvolt-L5 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>;
|
opp-microvolt-L6 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
opp-suspend;
|
};
|
|
opp-1608000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x5fd82200>;
|
opp-microvolt = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>;
|
opp-microvolt-L1 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>;
|
opp-microvolt-L2 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>;
|
opp-microvolt-L3 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>;
|
opp-microvolt-L4 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>;
|
opp-microvolt-L5 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>;
|
opp-microvolt-L6 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1800000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x6b49d200>;
|
opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>;
|
opp-microvolt-L1 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>;
|
opp-microvolt-L2 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>;
|
opp-microvolt-L3 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>;
|
opp-microvolt-L4 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>;
|
opp-microvolt-L5 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>;
|
opp-microvolt-L6 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-408000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x18519600>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-600000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x23c34600>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-816000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x30a32c00>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-1008000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x3c14dc00>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-1200000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x47868c00>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-1296000000 {
|
opp-supported-hw = <0x4 0xffff>;
|
opp-hz = <0x0 0x4d3f6400>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
opp-microvolt-L0 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>;
|
opp-microvolt-L1 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-1416000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x54667200>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
opp-microvolt-L0 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>;
|
opp-microvolt-L1 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>;
|
opp-microvolt-L2 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
opp-suspend;
|
};
|
|
opp-j-m-1608000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x5fd82200>;
|
opp-microvolt = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>;
|
opp-microvolt-L1 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>;
|
opp-microvolt-L2 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>;
|
opp-microvolt-L3 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>;
|
opp-microvolt-L4 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>;
|
opp-microvolt-L5 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>;
|
opp-microvolt-L6 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-1704000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x6590fa00>;
|
opp-microvolt = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>;
|
opp-microvolt-L1 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>;
|
opp-microvolt-L2 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>;
|
opp-microvolt-L3 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>;
|
opp-microvolt-L4 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>;
|
opp-microvolt-L5 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>;
|
opp-microvolt-L6 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
};
|
|
cluster1-opp-table {
|
compatible = "operating-points-v2";
|
opp-shared;
|
nvmem-cells = <0x24 0x25 0x21>;
|
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
|
rockchip,supported-hw;
|
rockchip,pvtm-hw = <0x6>;
|
rockchip,pvtm-voltage-sel-hw = <0x0 0x603 0x0 0x604 0x61c 0x1 0x61d 0x635 0x2 0x636 0x64e 0x3 0x64f 0x66c 0x4 0x66d 0x68a 0x5 0x68b 0x6a8 0x6 0x6a9 0x270f 0x7>;
|
rockchip,pvtm-voltage-sel = <0x0 0x63b 0x0 0x63c 0x64f 0x1 0x650 0x668 0x2 0x669 0x68b 0x3 0x68c 0x6ae 0x4 0x6af 0x6cf 0x5 0x6d0 0x6f0 0x6 0x6f1 0x270f 0x7>;
|
rockchip,pvtm-pvtpll;
|
rockchip,pvtm-offset = <0x18>;
|
rockchip,pvtm-sample-time = <0x44c>;
|
rockchip,pvtm-freq = <0x188940>;
|
rockchip,pvtm-volt = <0xb71b0>;
|
rockchip,pvtm-ref-temp = <0x19>;
|
rockchip,pvtm-temp-prop = <0x10e 0x10e>;
|
rockchip,pvtm-thermal-zone = "soc-thermal";
|
rockchip,pvtm-low-len-sel = <0x3>;
|
rockchip,grf = <0x26>;
|
volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>;
|
low-volt-mem-read-margin = <0x4>;
|
intermediate-threshold-freq = <0xf6180>;
|
rockchip,idle-threshold-freq = <0x21b100>;
|
rockchip,reboot-freq = <0x1b7740>;
|
rockchip,temp-hysteresis = <0x1388>;
|
rockchip,low-temp = <0x2710>;
|
rockchip,low-temp-min-volt = <0xb71b0>;
|
rockchip,high-temp = <0x14c08>;
|
rockchip,high-temp-max-freq = <0x21b100>;
|
phandle = <0x16>;
|
|
opp-408000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x18519600>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
opp-suspend;
|
};
|
|
opp-600000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x23c34600>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-816000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x30a32c00>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1008000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x3c14dc00>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1200000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x47868c00>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1416000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x54667200>;
|
opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
|
opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
|
opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
|
opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
|
opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>;
|
opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1608000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x5fd82200>;
|
opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
|
opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>;
|
opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>;
|
opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
|
opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
|
opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
|
opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1800000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x6b49d200>;
|
opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
|
opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
|
opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>;
|
opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>;
|
opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>;
|
opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>;
|
opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>;
|
opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-2016000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x7829b800>;
|
opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
|
opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
|
opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>;
|
opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>;
|
opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>;
|
opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>;
|
opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
|
opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-2208000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x839b6800>;
|
opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>;
|
opp-microvolt-L1 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>;
|
opp-microvolt-L2 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>;
|
opp-microvolt-L3 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>;
|
opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>;
|
opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>;
|
opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
|
opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-2256000000 {
|
opp-supported-hw = <0xf9 0x13>;
|
opp-hz = <0x0 0x8677d400>;
|
opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-2304000000 {
|
opp-supported-hw = <0xf9 0x24>;
|
opp-hz = <0x0 0x89544000>;
|
opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-2352000000 {
|
opp-supported-hw = <0xf9 0x48>;
|
opp-hz = <0x0 0x8c30ac00>;
|
opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-2400000000 {
|
opp-supported-hw = <0xf9 0x80>;
|
opp-hz = <0x0 0x8f0d1800>;
|
opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-408000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x18519600>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-600000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x23c34600>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-816000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x30a32c00>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-1008000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x3c14dc00>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-1200000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x47868c00>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-1416000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x54667200>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
opp-microvolt-L0 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
opp-suspend;
|
};
|
|
opp-j-m-1608000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x5fd82200>;
|
opp-microvolt = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>;
|
opp-microvolt-L2 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>;
|
opp-microvolt-L3 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>;
|
opp-microvolt-L4 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
opp-microvolt-L5 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
opp-microvolt-L6 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
opp-microvolt-L7 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-1800000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x6b49d200>;
|
opp-microvolt = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>;
|
opp-microvolt-L1 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>;
|
opp-microvolt-L2 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>;
|
opp-microvolt-L3 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>;
|
opp-microvolt-L4 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>;
|
opp-microvolt-L5 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>;
|
opp-microvolt-L6 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>;
|
opp-microvolt-L7 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-2016000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x7829b800>;
|
opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>;
|
opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>;
|
opp-microvolt-L2 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>;
|
opp-microvolt-L3 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>;
|
opp-microvolt-L4 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>;
|
opp-microvolt-L5 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>;
|
opp-microvolt-L6 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>;
|
opp-microvolt-L7 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
};
|
|
cluster2-opp-table {
|
compatible = "operating-points-v2";
|
opp-shared;
|
nvmem-cells = <0x27 0x28 0x21>;
|
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
|
rockchip,supported-hw;
|
rockchip,pvtm-hw = <0x6>;
|
rockchip,pvtm-voltage-sel-hw = <0x0 0x603 0x0 0x604 0x61c 0x1 0x61d 0x635 0x2 0x636 0x64e 0x3 0x64f 0x66c 0x4 0x66d 0x68a 0x5 0x68b 0x6a8 0x6 0x6a9 0x270f 0x7>;
|
rockchip,pvtm-voltage-sel = <0x0 0x63b 0x0 0x63c 0x64f 0x1 0x650 0x668 0x2 0x669 0x68b 0x3 0x68c 0x6ae 0x4 0x6af 0x6cf 0x5 0x6d0 0x6f0 0x6 0x6f1 0x270f 0x7>;
|
rockchip,pvtm-pvtpll;
|
rockchip,pvtm-offset = <0x18>;
|
rockchip,pvtm-sample-time = <0x44c>;
|
rockchip,pvtm-freq = <0x188940>;
|
rockchip,pvtm-volt = <0xb71b0>;
|
rockchip,pvtm-ref-temp = <0x19>;
|
rockchip,pvtm-temp-prop = <0x10e 0x10e>;
|
rockchip,pvtm-thermal-zone = "soc-thermal";
|
rockchip,pvtm-low-len-sel = <0x3>;
|
rockchip,grf = <0x29>;
|
volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>;
|
low-volt-mem-read-margin = <0x4>;
|
intermediate-threshold-freq = <0xf6180>;
|
rockchip,idle-threshold-freq = <0x21b100>;
|
rockchip,reboot-freq = <0x1b7740>;
|
rockchip,temp-hysteresis = <0x1388>;
|
rockchip,low-temp = <0x2710>;
|
rockchip,low-temp-min-volt = <0xb71b0>;
|
rockchip,high-temp = <0x14c08>;
|
rockchip,high-temp-max-freq = <0x21b100>;
|
phandle = <0x1a>;
|
|
opp-408000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x18519600>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
opp-suspend;
|
};
|
|
opp-600000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x23c34600>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-816000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x30a32c00>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1008000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x3c14dc00>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1200000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x47868c00>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1416000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x54667200>;
|
opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
|
opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
|
opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
|
opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
|
opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>;
|
opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1608000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x5fd82200>;
|
opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
|
opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>;
|
opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>;
|
opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>;
|
opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>;
|
opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
|
opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-1800000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x6b49d200>;
|
opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
|
opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
|
opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>;
|
opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>;
|
opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>;
|
opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>;
|
opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>;
|
opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-2016000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x7829b800>;
|
opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
|
opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
|
opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>;
|
opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>;
|
opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>;
|
opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>;
|
opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>;
|
opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-2208000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x839b6800>;
|
opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>;
|
opp-microvolt-L3 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>;
|
opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>;
|
opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>;
|
opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>;
|
opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-2256000000 {
|
opp-supported-hw = <0xf9 0x13>;
|
opp-hz = <0x0 0x8677d400>;
|
opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-2304000000 {
|
opp-supported-hw = <0xf9 0x24>;
|
opp-hz = <0x0 0x89544000>;
|
opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-2352000000 {
|
opp-supported-hw = <0xf9 0x48>;
|
opp-hz = <0x0 0x8c30ac00>;
|
opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-2400000000 {
|
opp-supported-hw = <0xf9 0x80>;
|
opp-hz = <0x0 0x8f0d1800>;
|
opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-408000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x18519600>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-600000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x23c34600>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-816000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x30a32c00>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-1008000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x3c14dc00>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-1200000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x47868c00>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-1416000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x54667200>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
opp-microvolt-L0 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
opp-suspend;
|
};
|
|
opp-j-m-1608000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x5fd82200>;
|
opp-microvolt = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>;
|
opp-microvolt-L2 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>;
|
opp-microvolt-L3 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>;
|
opp-microvolt-L4 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
opp-microvolt-L5 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
opp-microvolt-L6 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
opp-microvolt-L7 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-1800000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x6b49d200>;
|
opp-microvolt = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>;
|
opp-microvolt-L1 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>;
|
opp-microvolt-L2 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>;
|
opp-microvolt-L3 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>;
|
opp-microvolt-L4 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>;
|
opp-microvolt-L5 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>;
|
opp-microvolt-L6 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>;
|
opp-microvolt-L7 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
|
opp-j-m-2016000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x7829b800>;
|
opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>;
|
opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>;
|
opp-microvolt-L2 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>;
|
opp-microvolt-L3 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>;
|
opp-microvolt-L4 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>;
|
opp-microvolt-L5 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>;
|
opp-microvolt-L6 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>;
|
opp-microvolt-L7 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>;
|
clock-latency-ns = <0x9c40>;
|
};
|
};
|
|
arm-pmu {
|
compatible = "arm,armv8-pmuv3";
|
interrupts = <0x1 0x7 0x8>;
|
interrupt-affinity = <0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd>;
|
phandle = <0x207>;
|
};
|
|
cpuinfo {
|
compatible = "rockchip,cpuinfo";
|
nvmem-cells = <0x2a 0x2b 0x2c>;
|
nvmem-cell-names = "id", "cpu-version", "cpu-code";
|
};
|
|
csi2-dcphy0 {
|
compatible = "rockchip,rk3588-csi2-dphy";
|
rockchip,hw = <0x2d 0x2e>;
|
phys = <0x2f 0x30>;
|
phy-names = "dcphy0", "dcphy1";
|
status = "disabled";
|
phandle = <0x208>;
|
};
|
|
csi2-dcphy1 {
|
compatible = "rockchip,rk3588-csi2-dphy";
|
rockchip,hw = <0x2d 0x2e>;
|
phys = <0x2f 0x30>;
|
phy-names = "dcphy0", "dcphy1";
|
status = "disabled";
|
phandle = <0x209>;
|
};
|
|
csi2-dphy0 {
|
compatible = "rockchip,rk3588-csi2-dphy";
|
rockchip,hw = <0x2d 0x2e>;
|
phys = <0x2f 0x30>;
|
phy-names = "dcphy0", "dcphy1";
|
status = "disabled";
|
phandle = <0x20a>;
|
};
|
|
csi2-dphy1 {
|
compatible = "rockchip,rk3588-csi2-dphy";
|
rockchip,hw = <0x2d 0x2e>;
|
phys = <0x2f 0x30>;
|
phy-names = "dcphy0", "dcphy1";
|
status = "disabled";
|
phandle = <0x20b>;
|
};
|
|
csi2-dphy2 {
|
compatible = "rockchip,rk3588-csi2-dphy";
|
rockchip,hw = <0x2d 0x2e>;
|
phys = <0x2f 0x30>;
|
phy-names = "dcphy0", "dcphy1";
|
status = "disabled";
|
phandle = <0x20c>;
|
};
|
|
csi2-dphy3 {
|
compatible = "rockchip,rk3588-csi2-dphy";
|
rockchip,hw = <0x2d 0x2e>;
|
phys = <0x2f 0x30>;
|
phy-names = "dcphy0", "dcphy1";
|
status = "disabled";
|
phandle = <0x20d>;
|
};
|
|
csi2-dphy4 {
|
compatible = "rockchip,rk3588-csi2-dphy";
|
rockchip,hw = <0x2d 0x2e>;
|
phys = <0x2f 0x30>;
|
phy-names = "dcphy0", "dcphy1";
|
status = "disabled";
|
phandle = <0x20e>;
|
};
|
|
csi2-dphy5 {
|
compatible = "rockchip,rk3588-csi2-dphy";
|
rockchip,hw = <0x2d 0x2e>;
|
phys = <0x2f 0x30>;
|
phy-names = "dcphy0", "dcphy1";
|
status = "disabled";
|
phandle = <0x20f>;
|
};
|
|
display-subsystem {
|
compatible = "rockchip,display-subsystem";
|
ports = <0x31>;
|
memory-region = <0x32>;
|
memory-region-names = "drm-logo";
|
phandle = <0x210>;
|
|
route {
|
|
route-dp0 {
|
status = "disabled";
|
logo,uboot = "logo.bmp";
|
logo,kernel = "logo_kernel.bmp";
|
logo,mode = "center";
|
charge_logo,mode = "center";
|
connect = <0x33>;
|
phandle = <0x211>;
|
};
|
|
route-dsi0 {
|
status = "disabled";
|
logo,uboot = "logo.bmp";
|
logo,kernel = "logo_kernel.bmp";
|
logo,mode = "center";
|
charge_logo,mode = "center";
|
connect = <0x34>;
|
phandle = <0x212>;
|
};
|
|
route-dsi1 {
|
status = "disabled";
|
logo,uboot = "logo.bmp";
|
logo,kernel = "logo_kernel.bmp";
|
logo,mode = "center";
|
charge_logo,mode = "center";
|
connect = <0x35>;
|
phandle = <0x213>;
|
};
|
|
route-edp0 {
|
status = "disabled";
|
logo,uboot = "logo.bmp";
|
logo,kernel = "logo_kernel.bmp";
|
logo,mode = "center";
|
charge_logo,mode = "center";
|
connect = <0x36>;
|
phandle = <0x214>;
|
};
|
|
route-edp1 {
|
status = "okay";
|
logo,uboot = "logo.bmp";
|
logo,kernel = "logo_kernel.bmp";
|
logo,mode = "center";
|
charge_logo,mode = "center";
|
connect = <0x37>;
|
phandle = <0x215>;
|
};
|
|
route-hdmi0 {
|
status = "okay";
|
logo,uboot = "logo.bmp";
|
logo,kernel = "logo_kernel.bmp";
|
logo,mode = "center";
|
charge_logo,mode = "center";
|
connect = <0x38>;
|
phandle = <0x216>;
|
};
|
|
route-rgb {
|
status = "disabled";
|
logo,uboot = "logo.bmp";
|
logo,kernel = "logo_kernel.bmp";
|
logo,mode = "center";
|
charge_logo,mode = "center";
|
connect = <0x39>;
|
phandle = <0x217>;
|
};
|
|
route-dp1 {
|
status = "disabled";
|
logo,uboot = "logo.bmp";
|
logo,kernel = "logo_kernel.bmp";
|
logo,mode = "center";
|
charge_logo,mode = "center";
|
connect = <0x3a>;
|
phandle = <0x218>;
|
};
|
|
route-hdmi1 {
|
status = "disabled";
|
logo,uboot = "logo.bmp";
|
logo,kernel = "logo_kernel.bmp";
|
logo,mode = "center";
|
charge_logo,mode = "center";
|
connect = <0x3b>;
|
phandle = <0x219>;
|
};
|
};
|
};
|
|
dmc {
|
compatible = "rockchip,rk3588-dmc";
|
interrupts = <0x0 0x49 0x4>;
|
interrupt-names = "complete";
|
devfreq-events = <0x3c>;
|
clocks = <0xe 0x4>;
|
clock-names = "dmc_clk";
|
operating-points-v2 = <0x3d>;
|
upthreshold = <0x19>;
|
downdifferential = <0x14>;
|
system-status-level = <0x1 0x4 0x8 0x8 0x2 0x1 0x10 0x4 0x10000 0x4 0x80000 0x4 0x1000 0x8 0x4000 0x8 0x2000 0x8 0xc00 0x8 0x40000 0x8>;
|
auto-freq-en = <0x1>;
|
status = "okay";
|
center-supply = <0x3e>;
|
mem-supply = <0x3f>;
|
phandle = <0x21a>;
|
};
|
|
dmc-opp-table {
|
compatible = "operating-points-v2";
|
nvmem-cells = <0x40 0x41 0x21>;
|
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
|
rockchip,supported-hw;
|
rockchip,leakage-voltage-sel = <0x1 0x1f 0x0 0x20 0x2c 0x1 0x2d 0x39 0x2 0x3a 0xfe 0x3>;
|
rockchip,temp-hysteresis = <0x1388>;
|
rockchip,low-temp = <0x2710>;
|
rockchip,low-temp-min-volt = <0xb71b0>;
|
phandle = <0x3d>;
|
|
opp-528000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x1f78a400>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xd59f8 0xb1008 0xb1008 0xb71b0>;
|
opp-microvolt-L1 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xb71b0>;
|
opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xb71b0>;
|
opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa4cb8 0xa4cb8 0xb71b0>;
|
};
|
|
opp-1068000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x3fa86300>;
|
opp-microvolt = <0xb1008 0xb1008 0xd59f8 0xb40dc 0xb40dc 0xb71b0>;
|
opp-microvolt-L1 = <0xaae60 0xaae60 0xd59f8 0xadf34 0xadf34 0xb71b0>;
|
opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xb71b0>;
|
opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xb71b0>;
|
};
|
|
opp-1560000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x5cfbb600>;
|
opp-microvolt = <0xc3500 0xc3500 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
|
opp-microvolt-L1 = <0xbd358 0xbd358 0xd59f8 0xb1008 0xb1008 0xb71b0>;
|
opp-microvolt-L2 = <0xb71b0 0xb71b0 0xd59f8 0xadf34 0xadf34 0xb71b0>;
|
opp-microvolt-L3 = <0xb1008 0xb1008 0xd59f8 0xaae60 0xaae60 0xb71b0>;
|
};
|
|
opp-2750000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0xa3e9ab80>;
|
opp-microvolt = <0xd59f8 0xd59f8 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
|
opp-microvolt-L1 = <0xcf850 0xcf850 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
|
opp-microvolt-L2 = <0xcc77c 0xcc77c 0xd59f8 0xb1008 0xb1008 0xb71b0>;
|
opp-microvolt-L3 = <0xc96a8 0xc8320 0xd59f8 0xaae60 0xaae60 0xb71b0>;
|
};
|
|
opp-j-m-528000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x1f78a400>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
|
};
|
|
opp-j-m-1068000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x3fa86300>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
|
};
|
|
opp-j-m-1560000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x5cfbb600>;
|
opp-microvolt = <0xc3500 0xc3500 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
|
opp-microvolt-L1 = <0xbd358 0xbd358 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
|
opp-microvolt-L2 = <0xb71b0 0xb71b0 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
|
opp-microvolt-L3 = <0xb71b0 0xb71b0 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
|
};
|
|
opp-j-m-2750000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0xa3e9ab80>;
|
opp-microvolt = <0xd59f8 0xd59f8 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
|
opp-microvolt-L1 = <0xcf850 0xcf850 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
|
opp-microvolt-L2 = <0xcc77c 0xcc77c 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
|
opp-microvolt-L3 = <0xc96a8 0xc8320 0xd59f8 0xb71b0 0xb71b0 0xb71b0>;
|
};
|
};
|
|
firmware {
|
|
scmi {
|
compatible = "arm,scmi-smc";
|
shmem = <0x42>;
|
arm,smc-id = <0x82000010>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
phandle = <0x21b>;
|
|
protocol@14 {
|
reg = <0x14>;
|
#clock-cells = <0x1>;
|
assigned-clocks = <0xe 0x0 0xe 0x2 0xe 0x3>;
|
assigned-clock-rates = <0x30a32c00 0x30a32c00 0x30a32c00>;
|
phandle = <0xe>;
|
};
|
|
protocol@16 {
|
reg = <0x16>;
|
#reset-cells = <0x1>;
|
phandle = <0x11b>;
|
};
|
};
|
|
sdei {
|
compatible = "arm,sdei-1.0";
|
method = "smc";
|
phandle = <0x21c>;
|
};
|
|
optee {
|
compatible = "linaro,optee-tz";
|
method = "smc";
|
phandle = <0x21d>;
|
};
|
};
|
|
jpege-ccu {
|
compatible = "rockchip,vpu-jpege-ccu";
|
status = "okay";
|
phandle = <0xb0>;
|
};
|
|
mipi-dcphy-dummy {
|
status = "disabled";
|
phandle = <0x21e>;
|
};
|
|
mipi0-csi2 {
|
compatible = "rockchip,rk3588-mipi-csi2";
|
rockchip,hw = <0x43 0x44 0x45 0x46 0x47 0x48>;
|
status = "disabled";
|
phandle = <0x21f>;
|
};
|
|
mipi1-csi2 {
|
compatible = "rockchip,rk3588-mipi-csi2";
|
rockchip,hw = <0x43 0x44 0x45 0x46 0x47 0x48>;
|
status = "disabled";
|
phandle = <0x220>;
|
};
|
|
mipi2-csi2 {
|
compatible = "rockchip,rk3588-mipi-csi2";
|
rockchip,hw = <0x43 0x44 0x45 0x46 0x47 0x48>;
|
status = "disabled";
|
phandle = <0x221>;
|
};
|
|
mipi3-csi2 {
|
compatible = "rockchip,rk3588-mipi-csi2";
|
rockchip,hw = <0x43 0x44 0x45 0x46 0x47 0x48>;
|
status = "disabled";
|
phandle = <0x222>;
|
};
|
|
mipi4-csi2 {
|
compatible = "rockchip,rk3588-mipi-csi2";
|
rockchip,hw = <0x43 0x44 0x45 0x46 0x47 0x48>;
|
status = "disabled";
|
phandle = <0x223>;
|
};
|
|
mipi5-csi2 {
|
compatible = "rockchip,rk3588-mipi-csi2";
|
rockchip,hw = <0x43 0x44 0x45 0x46 0x47 0x48>;
|
status = "disabled";
|
phandle = <0x224>;
|
};
|
|
mpp-srv {
|
compatible = "rockchip,mpp-service";
|
rockchip,taskqueue-count = <0xc>;
|
rockchip,resetgroup-count = <0x1>;
|
status = "okay";
|
phandle = <0xab>;
|
};
|
|
psci {
|
compatible = "arm,psci-1.0";
|
method = "smc";
|
};
|
|
rkcif-dvp {
|
compatible = "rockchip,rkcif-dvp";
|
rockchip,hw = <0x49>;
|
iommus = <0x4a>;
|
status = "disabled";
|
phandle = <0x4b>;
|
};
|
|
rkcif-dvp-sditf {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4b>;
|
status = "disabled";
|
phandle = <0x225>;
|
};
|
|
rkcif-mipi-lvds {
|
compatible = "rockchip,rkcif-mipi-lvds";
|
rockchip,hw = <0x49>;
|
iommus = <0x4a>;
|
status = "disabled";
|
phandle = <0x4c>;
|
};
|
|
rkcif-mipi-lvds-sditf {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4c>;
|
status = "disabled";
|
phandle = <0x226>;
|
};
|
|
rkcif-mipi-lvds-sditf-vir1 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4c>;
|
status = "disabled";
|
phandle = <0x227>;
|
};
|
|
rkcif-mipi-lvds-sditf-vir2 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4c>;
|
status = "disabled";
|
phandle = <0x228>;
|
};
|
|
rkcif-mipi-lvds-sditf-vir3 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4c>;
|
status = "disabled";
|
phandle = <0x229>;
|
};
|
|
rkcif-mipi-lvds1 {
|
compatible = "rockchip,rkcif-mipi-lvds";
|
rockchip,hw = <0x49>;
|
iommus = <0x4a>;
|
status = "disabled";
|
phandle = <0x4d>;
|
};
|
|
rkcif-mipi-lvds1-sditf {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4d>;
|
status = "disabled";
|
phandle = <0x22a>;
|
};
|
|
rkcif-mipi-lvds1-sditf-vir1 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4d>;
|
status = "disabled";
|
phandle = <0x22b>;
|
};
|
|
rkcif-mipi-lvds1-sditf-vir2 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4d>;
|
status = "disabled";
|
phandle = <0x22c>;
|
};
|
|
rkcif-mipi-lvds1-sditf-vir3 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4d>;
|
status = "disabled";
|
phandle = <0x22d>;
|
};
|
|
rkcif-mipi-lvds2 {
|
compatible = "rockchip,rkcif-mipi-lvds";
|
rockchip,hw = <0x49>;
|
iommus = <0x4a>;
|
status = "disabled";
|
phandle = <0x4e>;
|
};
|
|
rkcif-mipi-lvds2-sditf {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4e>;
|
status = "disabled";
|
phandle = <0x22e>;
|
};
|
|
rkcif-mipi-lvds2-sditf-vir1 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4e>;
|
status = "disabled";
|
phandle = <0x22f>;
|
};
|
|
rkcif-mipi-lvds2-sditf-vir2 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4e>;
|
status = "disabled";
|
phandle = <0x230>;
|
};
|
|
rkcif-mipi-lvds2-sditf-vir3 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4e>;
|
status = "disabled";
|
phandle = <0x231>;
|
};
|
|
rkcif-mipi-lvds3 {
|
compatible = "rockchip,rkcif-mipi-lvds";
|
rockchip,hw = <0x49>;
|
iommus = <0x4a>;
|
status = "disabled";
|
phandle = <0x4f>;
|
};
|
|
rkcif-mipi-lvds3-sditf {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4f>;
|
status = "disabled";
|
phandle = <0x232>;
|
};
|
|
rkcif-mipi-lvds3-sditf-vir1 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4f>;
|
status = "disabled";
|
phandle = <0x233>;
|
};
|
|
rkcif-mipi-lvds3-sditf-vir2 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4f>;
|
status = "disabled";
|
phandle = <0x234>;
|
};
|
|
rkcif-mipi-lvds3-sditf-vir3 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x4f>;
|
status = "disabled";
|
phandle = <0x235>;
|
};
|
|
rkisp0-vir0 {
|
compatible = "rockchip,rkisp-vir";
|
rockchip,hw = <0x50>;
|
status = "disabled";
|
phandle = <0x236>;
|
};
|
|
rkisp0-vir1 {
|
compatible = "rockchip,rkisp-vir";
|
rockchip,hw = <0x50>;
|
status = "disabled";
|
phandle = <0x237>;
|
};
|
|
rkisp0-vir2 {
|
compatible = "rockchip,rkisp-vir";
|
rockchip,hw = <0x50>;
|
status = "disabled";
|
phandle = <0x238>;
|
};
|
|
rkisp0-vir3 {
|
compatible = "rockchip,rkisp-vir";
|
rockchip,hw = <0x50>;
|
status = "disabled";
|
phandle = <0x239>;
|
};
|
|
rkisp1-vir0 {
|
compatible = "rockchip,rkisp-vir";
|
rockchip,hw = <0x51>;
|
status = "disabled";
|
phandle = <0x23a>;
|
};
|
|
rkisp1-vir1 {
|
compatible = "rockchip,rkisp-vir";
|
rockchip,hw = <0x51>;
|
status = "disabled";
|
phandle = <0x23b>;
|
};
|
|
rkisp1-vir2 {
|
compatible = "rockchip,rkisp-vir";
|
rockchip,hw = <0x51>;
|
status = "disabled";
|
phandle = <0x23c>;
|
};
|
|
rkisp1-vir3 {
|
compatible = "rockchip,rkisp-vir";
|
rockchip,hw = <0x51>;
|
status = "disabled";
|
phandle = <0x23d>;
|
};
|
|
rkispp0-vir0 {
|
compatible = "rockchip,rk3588-rkispp-vir";
|
rockchip,hw = <0x52>;
|
status = "disabled";
|
phandle = <0x23e>;
|
};
|
|
rkispp1-vir0 {
|
compatible = "rockchip,rk3588-rkispp-vir";
|
rockchip,hw = <0x53>;
|
status = "disabled";
|
phandle = <0x23f>;
|
};
|
|
rkvenc-ccu {
|
compatible = "rockchip,rkv-encoder-v2-ccu";
|
status = "okay";
|
phandle = <0xb6>;
|
};
|
|
rockchip-suspend {
|
compatible = "rockchip,pm-rk3588";
|
status = "okay";
|
rockchip,sleep-debug-en = <0x1>;
|
rockchip,sleep-mode-config = <0x1000608>;
|
rockchip,wakeup-config = <0x100>;
|
phandle = <0x240>;
|
};
|
|
rockchip-system-monitor {
|
compatible = "rockchip,system-monitor";
|
rockchip,thermal-zone = "soc-thermal";
|
phandle = <0x241>;
|
};
|
|
thermal-zones {
|
phandle = <0x242>;
|
|
soc-thermal {
|
polling-delay-passive = <0x14>;
|
polling-delay = <0x3e8>;
|
sustainable-power = <0x834>;
|
thermal-sensors = <0x54 0x0>;
|
phandle = <0x243>;
|
|
trips {
|
|
trip-point-0 {
|
temperature = <0x124f8>;
|
hysteresis = <0x7d0>;
|
type = "passive";
|
phandle = <0x244>;
|
};
|
|
trip-point-1 {
|
temperature = <0x14c08>;
|
hysteresis = <0x7d0>;
|
type = "passive";
|
phandle = <0x55>;
|
};
|
|
soc-crit {
|
temperature = <0x1c138>;
|
hysteresis = <0x7d0>;
|
type = "critical";
|
phandle = <0x245>;
|
};
|
};
|
|
cooling-maps {
|
|
map0 {
|
trip = <0x55>;
|
cooling-device = <0x6 0xffffffff 0xffffffff>;
|
contribution = <0x400>;
|
};
|
|
map1 {
|
trip = <0x55>;
|
cooling-device = <0xa 0xffffffff 0xffffffff>;
|
contribution = <0x400>;
|
};
|
|
map2 {
|
trip = <0x55>;
|
cooling-device = <0xc 0xffffffff 0xffffffff>;
|
contribution = <0x400>;
|
};
|
|
map3 {
|
trip = <0x55>;
|
cooling-device = <0x56 0xffffffff 0xffffffff>;
|
contribution = <0x400>;
|
};
|
};
|
};
|
|
bigcore0-thermal {
|
polling-delay-passive = <0x14>;
|
polling-delay = <0x3e8>;
|
thermal-sensors = <0x54 0x1>;
|
phandle = <0x246>;
|
};
|
|
bigcore1-thermal {
|
polling-delay-passive = <0x14>;
|
polling-delay = <0x3e8>;
|
thermal-sensors = <0x54 0x2>;
|
phandle = <0x247>;
|
};
|
|
littlecore-thermal {
|
polling-delay-passive = <0x14>;
|
polling-delay = <0x3e8>;
|
thermal-sensors = <0x54 0x3>;
|
phandle = <0x248>;
|
};
|
|
center-thermal {
|
polling-delay-passive = <0x14>;
|
polling-delay = <0x3e8>;
|
thermal-sensors = <0x54 0x4>;
|
phandle = <0x249>;
|
};
|
|
gpu-thermal {
|
polling-delay-passive = <0x14>;
|
polling-delay = <0x3e8>;
|
thermal-sensors = <0x54 0x5>;
|
phandle = <0x24a>;
|
};
|
|
npu-thermal {
|
polling-delay-passive = <0x14>;
|
polling-delay = <0x3e8>;
|
thermal-sensors = <0x54 0x6>;
|
phandle = <0x24b>;
|
};
|
};
|
|
timer {
|
compatible = "arm,armv8-timer";
|
interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04 0x1 0xb 0xf04 0x1 0xa 0xf04>;
|
};
|
|
sram@10f000 {
|
compatible = "mmio-sram";
|
reg = <0x0 0x10f000 0x0 0x100>;
|
#address-cells = <0x1>;
|
#size-cells = <0x1>;
|
ranges = <0x0 0x0 0x10f000 0x100>;
|
|
sram@0 {
|
compatible = "arm,scmi-shmem";
|
reg = <0x0 0x100>;
|
phandle = <0x42>;
|
};
|
};
|
|
gpu@fb000000 {
|
compatible = "arm,mali-bifrost";
|
reg = <0x0 0xfb000000 0x0 0x200000>;
|
interrupts = <0x0 0x5e 0x4 0x0 0x5d 0x4 0x0 0x5c 0x4>;
|
interrupt-names = "GPU", "MMU", "JOB";
|
clocks = <0xe 0x5 0x2 0x115 0x2 0x116 0x2 0x114>;
|
clock-names = "clk_mali", "clk_gpu_coregroup", "clk_gpu_stacks", "clk_gpu";
|
assigned-clocks = <0xe 0x5>;
|
assigned-clock-rates = <0xbebc200>;
|
power-domains = <0x57 0xc>;
|
operating-points-v2 = <0x58>;
|
#cooling-cells = <0x2>;
|
dynamic-power-coefficient = <0xba6>;
|
upthreshold = <0x1e>;
|
downdifferential = <0xa>;
|
status = "okay";
|
mali-supply = <0x59>;
|
mem-supply = <0x59>;
|
phandle = <0x56>;
|
};
|
|
gpu-opp-table {
|
compatible = "operating-points-v2";
|
nvmem-cells = <0x5a 0x5b 0x21>;
|
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
|
rockchip,supported-hw;
|
rockchip,pvtm-hw = <0x4>;
|
rockchip,pvtm-voltage-sel-hw = <0x0 0x31f 0x0 0x320 0x333 0x1 0x334 0x34c 0x2 0x34d 0x365 0x3 0x366 0x37e 0x4 0x37f 0x270f 0x5>;
|
rockchip,pvtm-voltage-sel = <0x0 0x32f 0x0 0x330 0x343 0x1 0x344 0x35c 0x2 0x35d 0x375 0x3 0x376 0x38e 0x4 0x38f 0x270f 0x5>;
|
rockchip,pvtm-pvtpll;
|
rockchip,pvtm-offset = <0x1c>;
|
rockchip,pvtm-sample-time = <0x44c>;
|
rockchip,pvtm-freq = <0xc3500>;
|
rockchip,pvtm-volt = <0xb71b0>;
|
rockchip,pvtm-ref-temp = <0x19>;
|
rockchip,pvtm-temp-prop = <0xffffff79 0xffffff79>;
|
rockchip,pvtm-thermal-zone = "gpu-thermal";
|
clocks = <0x2 0x114>;
|
clock-names = "clk";
|
rockchip,grf = <0x5c>;
|
volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>;
|
low-volt-mem-read-margin = <0x4>;
|
intermediate-threshold-freq = <0x61a80>;
|
rockchip,temp-hysteresis = <0x1388>;
|
rockchip,low-temp = <0x2710>;
|
rockchip,low-temp-min-volt = <0xb71b0>;
|
rockchip,high-temp = <0x14c08>;
|
rockchip,high-temp-max-freq = <0xc3500>;
|
phandle = <0x58>;
|
|
opp-300000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x11e1a300>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
};
|
|
opp-400000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x17d78400>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
};
|
|
opp-500000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x1dcd6500>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
};
|
|
opp-600000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x23c34600>;
|
opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
};
|
|
opp-700000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x29b92700>;
|
opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
|
opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
|
opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
};
|
|
opp-800000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x2faf0800>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
opp-microvolt-L1 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
|
opp-microvolt-L2 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>;
|
opp-microvolt-L3 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>;
|
opp-microvolt-L4 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
|
opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
|
};
|
|
opp-900000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x35a4e900>;
|
opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
|
opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
|
opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>;
|
opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>;
|
opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
|
};
|
|
opp-1000000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x3b9aca00>;
|
opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>;
|
opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>;
|
opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>;
|
opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>;
|
opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
|
opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
|
};
|
|
opp-j-m-300000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x11e1a300>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-j-m-400000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x17d78400>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-j-m-500000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x1dcd6500>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-j-m-600000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x23c34600>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-j-m-700000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x29b92700>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-j-850000000 {
|
opp-supported-hw = <0x4 0xffff>;
|
opp-hz = <0x0 0x32a9f880>;
|
opp-microvolt = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
|
opp-microvolt-L1 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>;
|
opp-microvolt-L2 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>;
|
opp-microvolt-L3 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
opp-microvolt-L5 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-m-800000000 {
|
opp-supported-hw = <0x2 0xffff>;
|
opp-hz = <0x0 0x2faf0800>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-m-900000000 {
|
opp-supported-hw = <0x2 0xffff>;
|
opp-hz = <0x0 0x35a4e900>;
|
opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
|
opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
|
opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>;
|
opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>;
|
opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
opp-microvolt-L5 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-m-1000000000 {
|
opp-supported-hw = <0x2 0xffff>;
|
opp-hz = <0x0 0x3b9aca00>;
|
opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>;
|
opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>;
|
opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>;
|
opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>;
|
opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
|
opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
|
};
|
};
|
|
usbdrd3_0 {
|
compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
|
clocks = <0x2 0x1a3 0x2 0x1a2 0x2 0x1a1>;
|
clock-names = "ref", "suspend", "bus";
|
#address-cells = <0x2>;
|
#size-cells = <0x2>;
|
ranges;
|
status = "okay";
|
phandle = <0x24c>;
|
|
usb@fc000000 {
|
compatible = "snps,dwc3";
|
reg = <0x0 0xfc000000 0x0 0x400000>;
|
interrupts = <0x0 0xdc 0x4>;
|
power-domains = <0x57 0x1f>;
|
resets = <0x2 0x2a4>;
|
reset-names = "usb3-otg";
|
dr_mode = "host";
|
phys = <0x5d 0x5e>;
|
phy-names = "usb2-phy", "usb3-phy";
|
phy_type = "utmi_wide";
|
snps,dis_enblslpm_quirk;
|
snps,dis-u1-entry-quirk;
|
snps,dis-u2-entry-quirk;
|
snps,dis-u2-freeclk-exists-quirk;
|
snps,dis-del-phy-power-chg-quirk;
|
snps,dis-tx-ipgap-linecheck-quirk;
|
snps,parkmode-disable-hs-quirk;
|
snps,parkmode-disable-ss-quirk;
|
quirk-skip-phy-init;
|
status = "okay";
|
phandle = <0x24d>;
|
};
|
};
|
|
usb@fc800000 {
|
compatible = "rockchip,rk3588-ehci", "generic-ehci";
|
reg = <0x0 0xfc800000 0x0 0x40000>;
|
interrupts = <0x0 0xd7 0x4>;
|
clocks = <0x2 0x19d 0x2 0x19e 0x5f 0x60>;
|
clock-names = "usbhost", "arbiter", "utmi", "alk_usb";
|
companion = <0x61>;
|
phys = <0x62>;
|
phy-names = "usb2-phy";
|
power-domains = <0x57 0x1f>;
|
status = "okay";
|
phandle = <0x24e>;
|
};
|
|
usb@fc840000 {
|
compatible = "generic-ohci";
|
reg = <0x0 0xfc840000 0x0 0x40000>;
|
interrupts = <0x0 0xd8 0x4>;
|
clocks = <0x2 0x19d 0x2 0x19e 0x5f 0x60>;
|
clock-names = "usbhost", "arbiter", "utmi", "alk_usb";
|
phys = <0x62>;
|
phy-names = "usb2-phy";
|
power-domains = <0x57 0x1f>;
|
status = "okay";
|
phandle = <0x61>;
|
};
|
|
usb@fc880000 {
|
compatible = "rockchip,rk3588-ehci", "generic-ehci";
|
reg = <0x0 0xfc880000 0x0 0x40000>;
|
interrupts = <0x0 0xda 0x4>;
|
clocks = <0x2 0x19f 0x2 0x1a0 0x63 0x60>;
|
clock-names = "usbhost", "arbiter", "utmi", "alk_usb";
|
companion = <0x64>;
|
phys = <0x65>;
|
phy-names = "usb2-phy";
|
power-domains = <0x57 0x1f>;
|
status = "okay";
|
phandle = <0x24f>;
|
};
|
|
usb@fc8c0000 {
|
compatible = "generic-ohci";
|
reg = <0x0 0xfc8c0000 0x0 0x40000>;
|
interrupts = <0x0 0xdb 0x4>;
|
clocks = <0x2 0x19f 0x2 0x1a0 0x63 0x60>;
|
clock-names = "usbhost", "arbiter", "utmi", "alk_usb";
|
phys = <0x65>;
|
phy-names = "usb2-phy";
|
power-domains = <0x57 0x1f>;
|
status = "okay";
|
phandle = <0x64>;
|
};
|
|
iommu@fc900000 {
|
compatible = "arm,smmu-v3";
|
reg = <0x0 0xfc900000 0x0 0x200000>;
|
interrupts = <0x0 0x171 0x4 0x0 0x173 0x4 0x0 0x176 0x4 0x0 0x16f 0x4>;
|
interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
|
#iommu-cells = <0x1>;
|
status = "disabled";
|
phandle = <0x250>;
|
};
|
|
iommu@fcb00000 {
|
compatible = "arm,smmu-v3";
|
reg = <0x0 0xfcb00000 0x0 0x200000>;
|
interrupts = <0x0 0x17d 0x4 0x0 0x17f 0x4 0x0 0x182 0x4 0x0 0x17b 0x4>;
|
interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
|
#iommu-cells = <0x1>;
|
status = "disabled";
|
phandle = <0x251>;
|
};
|
|
usbhost3_0 {
|
compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
|
clocks = <0x2 0x179 0x2 0x178 0x2 0x177 0x2 0x17a 0x2 0x166 0x2 0x181>;
|
clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe";
|
#address-cells = <0x2>;
|
#size-cells = <0x2>;
|
ranges;
|
status = "okay";
|
phandle = <0x252>;
|
|
usb@fcd00000 {
|
compatible = "snps,dwc3";
|
reg = <0x0 0xfcd00000 0x0 0x400000>;
|
interrupts = <0x0 0xde 0x4>;
|
resets = <0x2 0x237>;
|
reset-names = "usb3-host";
|
dr_mode = "host";
|
phys = <0x66 0x4>;
|
phy-names = "usb3-phy";
|
phy_type = "utmi_wide";
|
snps,dis_enblslpm_quirk;
|
snps,dis-u2-freeclk-exists-quirk;
|
snps,dis-del-phy-power-chg-quirk;
|
snps,dis-tx-ipgap-linecheck-quirk;
|
snps,dis_rxdet_inp3_quirk;
|
snps,parkmode-disable-hs-quirk;
|
snps,parkmode-disable-ss-quirk;
|
status = "okay";
|
phandle = <0x253>;
|
};
|
};
|
|
syscon@fd588000 {
|
compatible = "rockchip,rk3588-pmu0-grf", "syscon", "simple-mfd";
|
reg = <0x0 0xfd588000 0x0 0x2000>;
|
phandle = <0x254>;
|
|
reboot-mode {
|
compatible = "syscon-reboot-mode";
|
offset = <0x80>;
|
mode-bootloader = <0x5242c301>;
|
mode-charge = <0x5242c30b>;
|
mode-fastboot = <0x5242c309>;
|
mode-loader = <0x5242c301>;
|
mode-normal = <0x5242c300>;
|
mode-recovery = <0x5242c303>;
|
mode-ums = <0x5242c30c>;
|
mode-panic = <0x5242c307>;
|
mode-watchdog = <0x5242c308>;
|
mode-quiescent = <0x5242c30e>;
|
phandle = <0x255>;
|
};
|
};
|
|
syscon@fd58a000 {
|
compatible = "rockchip,rk3588-pmu1-grf", "syscon";
|
reg = <0x0 0xfd58a000 0x0 0x2000>;
|
phandle = <0x102>;
|
};
|
|
syscon@fd58c000 {
|
compatible = "rockchip,rk3588-sys-grf", "syscon", "simple-mfd";
|
reg = <0x0 0xfd58c000 0x0 0x1000>;
|
phandle = <0xbc>;
|
|
rgb {
|
compatible = "rockchip,rk3588-rgb";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x67>;
|
status = "disabled";
|
phandle = <0x256>;
|
|
ports {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
port@0 {
|
reg = <0x0>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
endpoint@2 {
|
reg = <0x2>;
|
remote-endpoint = <0x39>;
|
status = "disabled";
|
phandle = <0xe4>;
|
};
|
};
|
};
|
};
|
};
|
|
syscon@fd590000 {
|
compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
|
reg = <0x0 0xfd590000 0x0 0x100>;
|
phandle = <0x26>;
|
};
|
|
syscon@fd592000 {
|
compatible = "rockchip,rk3588-bigcore1-grf", "syscon";
|
reg = <0x0 0xfd592000 0x0 0x100>;
|
phandle = <0x29>;
|
};
|
|
syscon@fd594000 {
|
compatible = "rockchip,rk3588-litcore-grf", "syscon";
|
reg = <0x0 0xfd594000 0x0 0x100>;
|
phandle = <0x22>;
|
};
|
|
syscon@fd598000 {
|
compatible = "rockchip,rk3588-dsu-grf", "syscon";
|
reg = <0x0 0xfd598000 0x0 0x100>;
|
phandle = <0x23>;
|
};
|
|
syscon@fd5a0000 {
|
compatible = "rockchip,rk3588-gpu-grf", "syscon";
|
reg = <0x0 0xfd5a0000 0x0 0x100>;
|
phandle = <0x5c>;
|
};
|
|
syscon@fd5a2000 {
|
compatible = "rockchip,rk3588-npu-grf", "syscon";
|
reg = <0x0 0xfd5a2000 0x0 0x100>;
|
phandle = <0xa9>;
|
};
|
|
syscon@fd5a4000 {
|
compatible = "rockchip,rk3588-vop-grf", "syscon";
|
reg = <0x0 0xfd5a4000 0x0 0x2000>;
|
phandle = <0xcb>;
|
};
|
|
syscon@fd5a6000 {
|
compatible = "rockchip,rk3588-vo-grf", "syscon";
|
reg = <0x0 0xfd5a6000 0x0 0x2000>;
|
clocks = <0x68>;
|
phandle = <0xf2>;
|
};
|
|
syscon@fd5a8000 {
|
compatible = "rockchip,rk3588-vo-grf", "syscon";
|
reg = <0x0 0xfd5a8000 0x0 0x100>;
|
clocks = <0x69>;
|
phandle = <0xcc>;
|
};
|
|
syscon@fd5ac000 {
|
compatible = "rockchip,rk3588-usb-grf", "syscon";
|
reg = <0x0 0xfd5ac000 0x0 0x4000>;
|
phandle = <0x6a>;
|
};
|
|
syscon@fd5b0000 {
|
compatible = "rockchip,rk3588-php-grf", "syscon";
|
reg = <0x0 0xfd5b0000 0x0 0x1000>;
|
phandle = <0x6c>;
|
};
|
|
syscon@fd5b4000 {
|
compatible = "rockchip,mipi-dphy-grf", "syscon";
|
reg = <0x0 0xfd5b4000 0x0 0x1000>;
|
phandle = <0x18c>;
|
};
|
|
syscon@fd5b5000 {
|
compatible = "rockchip,mipi-dphy-grf", "syscon";
|
reg = <0x0 0xfd5b5000 0x0 0x1000>;
|
phandle = <0x18d>;
|
};
|
|
syscon@fd5bc000 {
|
compatible = "rockchip,pipe-phy-grf", "syscon";
|
reg = <0x0 0xfd5bc000 0x0 0x100>;
|
phandle = <0x18e>;
|
};
|
|
syscon@fd5c4000 {
|
compatible = "rockchip,pipe-phy-grf", "syscon";
|
reg = <0x0 0xfd5c4000 0x0 0x100>;
|
phandle = <0x18f>;
|
};
|
|
syscon@fd5c8000 {
|
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
reg = <0x0 0xfd5c8000 0x0 0x4000>;
|
phandle = <0x188>;
|
};
|
|
syscon@fd5d0000 {
|
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
reg = <0x0 0xfd5d0000 0x0 0x4000>;
|
#address-cells = <0x1>;
|
#size-cells = <0x1>;
|
phandle = <0x187>;
|
|
usb2-phy@0 {
|
compatible = "rockchip,rk3588-usb2phy";
|
reg = <0x0 0x10>;
|
interrupts = <0x0 0x189 0x4>;
|
resets = <0x2 0xc0047 0x2 0x488>;
|
reset-names = "phy", "apb";
|
clocks = <0x2 0x2b5>;
|
clock-names = "phyclk";
|
clock-output-names = "usb480m_phy0";
|
#clock-cells = <0x0>;
|
rockchip,usbctrl-grf = <0x6a>;
|
status = "okay";
|
phandle = <0x189>;
|
|
otg-port {
|
#phy-cells = <0x0>;
|
status = "okay";
|
phy-supply = <0x6b>;
|
phandle = <0x5d>;
|
};
|
};
|
};
|
|
syscon@fd5d8000 {
|
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
reg = <0x0 0xfd5d8000 0x0 0x4000>;
|
#address-cells = <0x1>;
|
#size-cells = <0x1>;
|
phandle = <0x257>;
|
|
usb2-phy@8000 {
|
compatible = "rockchip,rk3588-usb2phy";
|
reg = <0x8000 0x10>;
|
interrupts = <0x0 0x187 0x4>;
|
resets = <0x2 0xc0049 0x2 0x48a>;
|
reset-names = "phy", "apb";
|
clocks = <0x2 0x2b5>;
|
clock-names = "phyclk";
|
clock-output-names = "usb480m_phy2";
|
#clock-cells = <0x0>;
|
status = "okay";
|
phandle = <0x5f>;
|
|
host-port {
|
#phy-cells = <0x0>;
|
status = "okay";
|
phy-supply = <0x6b>;
|
phandle = <0x62>;
|
};
|
};
|
};
|
|
syscon@fd5dc000 {
|
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
reg = <0x0 0xfd5dc000 0x0 0x4000>;
|
#address-cells = <0x1>;
|
#size-cells = <0x1>;
|
phandle = <0x258>;
|
|
usb2-phy@c000 {
|
compatible = "rockchip,rk3588-usb2phy";
|
reg = <0xc000 0x10>;
|
interrupts = <0x0 0x188 0x4>;
|
resets = <0x2 0xc004a 0x2 0x48b>;
|
reset-names = "phy", "apb";
|
clocks = <0x2 0x2b5>;
|
clock-names = "phyclk";
|
clock-output-names = "usb480m_phy3";
|
#clock-cells = <0x0>;
|
status = "okay";
|
phandle = <0x63>;
|
|
host-port {
|
#phy-cells = <0x0>;
|
status = "okay";
|
phy-supply = <0x6b>;
|
phandle = <0x65>;
|
};
|
};
|
};
|
|
syscon@fd5e0000 {
|
compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
|
reg = <0x0 0xfd5e0000 0x0 0x100>;
|
phandle = <0x186>;
|
};
|
|
syscon@fd5e8000 {
|
compatible = "rockchip,mipi-dcphy-grf", "syscon";
|
reg = <0x0 0xfd5e8000 0x0 0x4000>;
|
phandle = <0x18a>;
|
};
|
|
syscon@fd5ec000 {
|
compatible = "rockchip,mipi-dcphy-grf", "syscon";
|
reg = <0x0 0xfd5ec000 0x0 0x4000>;
|
phandle = <0x18b>;
|
};
|
|
syscon@fd5f0000 {
|
compatible = "rockchip,rk3588-ioc", "syscon";
|
reg = <0x0 0xfd5f0000 0x0 0x10000>;
|
phandle = <0x190>;
|
};
|
|
clock-controller@fd7c0000 {
|
compatible = "rockchip,rk3588-cru";
|
rockchip,grf = <0x6c>;
|
reg = <0x0 0xfd7c0000 0x0 0x5c000>;
|
#clock-cells = <0x1>;
|
#reset-cells = <0x1>;
|
assigned-clocks = <0x2 0x9 0x2 0x5 0x2 0x8 0x2 0x7 0x2 0xd8 0x2 0xda 0x2 0xd9 0x2 0x10e 0x2 0x10f 0x2 0x110 0x2 0x299 0x2 0x29a 0x2 0x7b 0x2 0xec 0x2 0x114 0x2 0x208 0x2 0x20e 0x2 0x21f 0x2 0x77>;
|
assigned-clock-rates = <0x4190ab00 0x2ee00000 0x32a9f880 0x46cf7100 0x29d7ab80 0x17d78400 0x1dcd6500 0x2cb41780 0x5f5e100 0x17d78400 0x5f5e100 0xbebc200 0x165a0bc0 0x8f0d180 0xbebc200 0xb71b00 0xb71b00 0x5e69ec0 0x1312d00>;
|
phandle = <0x2>;
|
};
|
|
i2c@fd880000 {
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
reg = <0x0 0xfd880000 0x0 0x1000>;
|
clocks = <0x2 0x287 0x2 0x286>;
|
clock-names = "i2c", "pclk";
|
interrupts = <0x0 0x13d 0x4>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x6d>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
status = "okay";
|
phandle = <0x259>;
|
|
rk8602@42 {
|
compatible = "rockchip,rk8602";
|
reg = <0x42>;
|
vin-supply = <0x6e>;
|
regulator-compatible = "rk860x-reg";
|
regulator-name = "vdd_cpu_big0_s0";
|
regulator-min-microvolt = <0x86470>;
|
regulator-max-microvolt = <0x100590>;
|
regulator-ramp-delay = <0x8fc>;
|
rockchip,suspend-voltage-selector = <0x1>;
|
regulator-boot-on;
|
regulator-always-on;
|
phandle = <0x18>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
|
rk8603@43 {
|
compatible = "rockchip,rk8603";
|
reg = <0x43>;
|
vin-supply = <0x6e>;
|
regulator-compatible = "rk860x-reg";
|
regulator-name = "vdd_cpu_big1_s0";
|
regulator-min-microvolt = <0x86470>;
|
regulator-max-microvolt = <0x100590>;
|
regulator-ramp-delay = <0x8fc>;
|
rockchip,suspend-voltage-selector = <0x1>;
|
regulator-boot-on;
|
regulator-always-on;
|
phandle = <0x1c>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
};
|
|
serial@fd890000 {
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfd890000 0x0 0x100>;
|
interrupts = <0x0 0x14b 0x4>;
|
clocks = <0x2 0x2ae 0x2 0x2af>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <0x2>;
|
reg-io-width = <0x4>;
|
dmas = <0x6f 0x6 0x6f 0x7>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x70>;
|
status = "disabled";
|
phandle = <0x25a>;
|
};
|
|
pwm@fd8b0000 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfd8b0000 0x0 0x10>;
|
interrupts = <0x0 0x158 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x71>;
|
clocks = <0x2 0x2a5 0x2 0x2a4>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x25b>;
|
};
|
|
pwm@fd8b0010 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfd8b0010 0x0 0x10>;
|
interrupts = <0x0 0x158 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x72>;
|
clocks = <0x2 0x2a5 0x2 0x2a4>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x25c>;
|
};
|
|
pwm@fd8b0020 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfd8b0020 0x0 0x10>;
|
interrupts = <0x0 0x158 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x73>;
|
clocks = <0x2 0x2a5 0x2 0x2a4>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x25d>;
|
};
|
|
pwm@fd8b0030 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfd8b0030 0x0 0x10>;
|
interrupts = <0x0 0x158 0x4 0x0 0x159 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x74>;
|
clocks = <0x2 0x2a5 0x2 0x2a4>;
|
clock-names = "pwm", "pclk";
|
status = "okay";
|
phandle = <0x1c5>;
|
};
|
|
power-management@fd8d8000 {
|
compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
|
reg = <0x0 0xfd8d8000 0x0 0x400>;
|
phandle = <0xcd>;
|
|
power-controller {
|
compatible = "rockchip,rk3588-power-controller";
|
#power-domain-cells = <0x1>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
status = "okay";
|
phandle = <0x57>;
|
|
power-domain@8 {
|
reg = <0x8>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
power-domain@9 {
|
reg = <0x9>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
clocks = <0x2 0x12f 0x2 0x131 0x2 0x130 0x2 0x126>;
|
pm_qos = <0x75 0x76 0x77>;
|
|
power-domain@10 {
|
reg = <0xa>;
|
clocks = <0x2 0x12f 0x2 0x131 0x2 0x130>;
|
pm_qos = <0x78>;
|
};
|
|
power-domain@11 {
|
reg = <0xb>;
|
clocks = <0x2 0x12f 0x2 0x131 0x2 0x130>;
|
pm_qos = <0x79>;
|
};
|
};
|
};
|
|
power-domain@12 {
|
reg = <0xc>;
|
clocks = <0x2 0x114 0x2 0x115 0x2 0x116>;
|
pm_qos = <0x7a 0x7b 0x7c 0x7d>;
|
};
|
|
power-domain@13 {
|
reg = <0xd>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
power-domain@14 {
|
reg = <0xe>;
|
clocks = <0x2 0x18f 0x2 0x1be 0x2 0x1bc 0x2 0x190 0x2 0x18e>;
|
pm_qos = <0x7e>;
|
};
|
|
power-domain@15 {
|
reg = <0xf>;
|
clocks = <0x2 0x194 0x2 0x1be 0x2 0x1bc 0x2 0x195>;
|
pm_qos = <0x7f>;
|
};
|
|
power-domain@16 {
|
reg = <0x10>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
clocks = <0x2 0x1c4 0x2 0x1c5>;
|
pm_qos = <0x80 0x81 0x82>;
|
|
power-domain@17 {
|
reg = <0x11>;
|
clocks = <0x2 0x1c9 0x2 0x1c4 0x2 0x1c5 0x2 0x1ca>;
|
pm_qos = <0x83 0x84 0x85>;
|
};
|
};
|
};
|
|
power-domain@21 {
|
reg = <0x15>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
clocks = <0x2 0x1be 0x2 0x1bd 0x2 0x1bc 0x2 0x1bf 0x2 0x1aa 0x2 0x1a9 0x2 0x1ac 0x2 0x1ad 0x2 0x1ae 0x2 0x1af 0x2 0x1b0 0x2 0x1b1 0x2 0x1b2 0x2 0x1b3 0x2 0x1b4 0x2 0x1b5 0x2 0x1b7 0x2 0x1b6>;
|
pm_qos = <0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d>;
|
|
power-domain@23 {
|
reg = <0x17>;
|
clocks = <0x2 0x4b 0x2 0x49 0x2 0x1be>;
|
pm_qos = <0x8e>;
|
};
|
|
power-domain@14 {
|
reg = <0xe>;
|
clocks = <0x2 0x18f 0x2 0x1be 0x2 0x1bc 0x2 0x190>;
|
pm_qos = <0x7e>;
|
};
|
|
power-domain@15 {
|
reg = <0xf>;
|
clocks = <0x2 0x194 0x2 0x1be 0x2 0x1bc>;
|
pm_qos = <0x7f>;
|
};
|
|
power-domain@22 {
|
reg = <0x16>;
|
clocks = <0x2 0x1ba 0x2 0x1b9>;
|
pm_qos = <0x8f>;
|
};
|
};
|
|
power-domain@24 {
|
reg = <0x18>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
clocks = <0x2 0x26e 0x2 0x26d 0x2 0x270>;
|
pm_qos = <0x90 0x91>;
|
|
power-domain@25 {
|
reg = <0x19>;
|
clocks = <0x2 0x1f6 0x2 0x1f7 0x2 0x1f5 0x2 0x1f3 0x2 0x1ee 0x2 0x1ed 0x2 0x26d>;
|
pm_qos = <0x92>;
|
};
|
};
|
|
power-domain@26 {
|
reg = <0x1a>;
|
clocks = <0x2 0x22e 0x2 0x22f 0x2 0x22d 0x2 0x218 0x2 0x217 0x2 0x22b 0x2 0x264>;
|
pm_qos = <0x93 0x94>;
|
};
|
|
power-domain@27 {
|
reg = <0x1b>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
clocks = <0x2 0x1e1 0x2 0x1e2 0x2 0x1df 0x2 0x1de 0x2 0x1e5 0x2 0x1e4>;
|
pm_qos = <0x95 0x96 0x97 0x98>;
|
|
power-domain@28 {
|
reg = <0x1c>;
|
clocks = <0x2 0x121 0x2 0x120 0x2 0x1e1 0x2 0x1e2>;
|
pm_qos = <0x99 0x9a>;
|
};
|
|
power-domain@29 {
|
reg = <0x1d>;
|
clocks = <0x2 0x1d6 0x2 0x1d5 0x2 0x1d9 0x2 0x1d8 0x2 0x1e2>;
|
pm_qos = <0x9b 0x9c>;
|
};
|
};
|
|
power-domain@30 {
|
reg = <0x1e>;
|
clocks = <0x2 0x189 0x2 0x18a>;
|
pm_qos = <0x9d>;
|
};
|
|
power-domain@31 {
|
reg = <0x1f>;
|
clocks = <0x2 0x166 0x2 0x1a1 0x2 0x1a4 0x2 0x19d 0x2 0x19e 0x2 0x19f 0x2 0x1a0>;
|
pm_qos = <0x9e 0x9f 0xa0 0xa1>;
|
};
|
|
power-domain@33 {
|
reg = <0x21>;
|
clocks = <0x2 0x166 0x2 0x169 0x2 0x16a>;
|
};
|
|
power-domain@34 {
|
reg = <0x22>;
|
clocks = <0x2 0x166 0x2 0x169 0x2 0x16a>;
|
};
|
|
power-domain@37 {
|
reg = <0x25>;
|
clocks = <0x2 0x199 0x2 0x140>;
|
pm_qos = <0xa2>;
|
};
|
|
power-domain@38 {
|
reg = <0x26>;
|
clocks = <0x2 0x3c 0x2 0x3d>;
|
};
|
|
power-domain@40 {
|
reg = <0x28>;
|
pm_qos = <0xa3>;
|
};
|
};
|
};
|
|
pvtm@fda40000 {
|
compatible = "rockchip,rk3588-bigcore0-pvtm";
|
reg = <0x0 0xfda40000 0x0 0x100>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
pvtm@0 {
|
reg = <0x0>;
|
clocks = <0x2 0x2c6 0x2 0x15>;
|
clock-names = "clk", "pclk";
|
};
|
};
|
|
pvtm@fda50000 {
|
compatible = "rockchip,rk3588-bigcore1-pvtm";
|
reg = <0x0 0xfda50000 0x0 0x100>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
pvtm@1 {
|
reg = <0x1>;
|
clocks = <0x2 0x2c8 0x2 0x17>;
|
clock-names = "clk", "pclk";
|
};
|
};
|
|
pvtm@fda60000 {
|
compatible = "rockchip,rk3588-litcore-pvtm";
|
reg = <0x0 0xfda60000 0x0 0x100>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
pvtm@2 {
|
reg = <0x2>;
|
clocks = <0x2 0x2ca 0x2 0x1b>;
|
clock-names = "clk", "pclk";
|
};
|
};
|
|
pvtm@fdaf0000 {
|
compatible = "rockchip,rk3588-npu-pvtm";
|
reg = <0x0 0xfdaf0000 0x0 0x100>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
pvtm@3 {
|
reg = <0x3>;
|
clocks = <0x2 0x12b 0x2 0x129>;
|
clock-names = "clk", "pclk";
|
resets = <0x2 0x1de 0x2 0x1dc>;
|
reset-names = "rts", "rst-p";
|
};
|
};
|
|
pvtm@fdb30000 {
|
compatible = "rockchip,rk3588-gpu-pvtm";
|
reg = <0x0 0xfdb30000 0x0 0x100>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
pvtm@4 {
|
reg = <0x4>;
|
clocks = <0x2 0x118>;
|
clock-names = "clk";
|
resets = <0x2 0x430 0x2 0x42f>;
|
reset-names = "rts", "rst-p";
|
};
|
};
|
|
npu@fdab0000 {
|
compatible = "rockchip,rk3588-rknpu";
|
reg = <0x0 0xfdab0000 0x0 0x10000 0x0 0xfdac0000 0x0 0x10000 0x0 0xfdad0000 0x0 0x10000>;
|
interrupts = <0x0 0x6e 0x4 0x0 0x6f 0x4 0x0 0x70 0x4>;
|
interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq";
|
clocks = <0xe 0x6 0x2 0x12d 0x2 0x122 0x2 0x124 0x2 0x12e 0x2 0x123 0x2 0x125 0x2 0x131>;
|
clock-names = "clk_npu", "aclk0", "aclk1", "aclk2", "hclk0", "hclk1", "hclk2", "pclk";
|
assigned-clocks = <0xe 0x6>;
|
assigned-clock-rates = <0xbebc200>;
|
resets = <0x2 0x1e6 0x2 0x1b0 0x2 0x1c0 0x2 0x1e8 0x2 0x1b2 0x2 0x1c2>;
|
reset-names = "srst_a0", "srst_a1", "srst_a2", "srst_h0", "srst_h1", "srst_h2";
|
power-domains = <0x57 0x9 0x57 0xa 0x57 0xb>;
|
power-domain-names = "npu0", "npu1", "npu2";
|
operating-points-v2 = <0xa4>;
|
iommus = <0xa5>;
|
status = "okay";
|
rknpu-supply = <0xa6>;
|
mem-supply = <0xa6>;
|
phandle = <0x25e>;
|
};
|
|
npu-opp-table {
|
compatible = "operating-points-v2";
|
nvmem-cells = <0xa7 0xa8 0x21>;
|
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
|
rockchip,supported-hw;
|
rockchip,pvtm-hw = <0x6>;
|
rockchip,pvtm-voltage-sel-hw = <0x0 0x31f 0x0 0x320 0x333 0x1 0x334 0x34c 0x2 0x34d 0x365 0x3 0x366 0x37e 0x4 0x37f 0x270f 0x5>;
|
rockchip,pvtm-voltage-sel = <0x0 0x32f 0x0 0x330 0x343 0x1 0x344 0x35c 0x2 0x35d 0x375 0x3 0x376 0x38e 0x4 0x38f 0x270f 0x5>;
|
rockchip,pvtm-pvtpll;
|
rockchip,pvtm-offset = <0x50>;
|
rockchip,pvtm-sample-time = <0x44c>;
|
rockchip,pvtm-freq = <0xc3500>;
|
rockchip,pvtm-volt = <0xb71b0>;
|
rockchip,pvtm-ref-temp = <0x19>;
|
rockchip,pvtm-temp-prop = <0xffffff8f 0xffffff8f>;
|
rockchip,pvtm-thermal-zone = "npu-thermal";
|
clocks = <0x2 0x12a>;
|
clock-names = "pclk";
|
rockchip,grf = <0xa9>;
|
volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>;
|
low-volt-mem-read-margin = <0x4>;
|
intermediate-threshold-freq = <0x7a120>;
|
rockchip,init-freq = <0xf4240>;
|
rockchip,temp-hysteresis = <0x1388>;
|
rockchip,low-temp = <0x2710>;
|
rockchip,low-temp-min-volt = <0xb71b0>;
|
rockchip,high-temp = <0x14c08>;
|
rockchip,high-temp-max-freq = <0xc3500>;
|
phandle = <0xa4>;
|
|
opp-300000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x11e1a300>;
|
opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
|
opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
|
opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
};
|
|
opp-400000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x17d78400>;
|
opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
|
opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
|
opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
};
|
|
opp-500000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x1dcd6500>;
|
opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
|
opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
|
opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
};
|
|
opp-600000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x23c34600>;
|
opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
|
opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
|
opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
};
|
|
opp-700000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x29b92700>;
|
opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
|
opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>;
|
opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>;
|
};
|
|
opp-800000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x2faf0800>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
opp-microvolt-L2 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
|
opp-microvolt-L3 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>;
|
opp-microvolt-L4 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>;
|
opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>;
|
};
|
|
opp-900000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x35a4e900>;
|
opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
|
opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
|
opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>;
|
opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>;
|
opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>;
|
};
|
|
opp-1000000000 {
|
opp-supported-hw = <0xf9 0xffff>;
|
opp-hz = <0x0 0x3b9aca00>;
|
opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>;
|
opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>;
|
opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>;
|
opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>;
|
opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
|
opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
|
};
|
|
opp-j-m-300000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x11e1a300>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-j-m-400000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x17d78400>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-j-m-500000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x1dcd6500>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-j-m-600000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x23c34600>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-j-m-700000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x29b92700>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-j-m-800000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x2faf0800>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
|
opp-j-m-950000000 {
|
opp-supported-hw = <0x6 0xffff>;
|
opp-hz = <0x0 0x389fd980>;
|
opp-microvolt = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>;
|
opp-microvolt-L1 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>;
|
opp-microvolt-L2 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>;
|
opp-microvolt-L3 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
|
opp-microvolt-L4 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>;
|
opp-microvolt-L5 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>;
|
};
|
};
|
|
iommu@fdab9000 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdab9000 0x0 0x100 0x0 0xfdaba000 0x0 0x100 0x0 0xfdaca000 0x0 0x100 0x0 0xfdada000 0x0 0x100>;
|
interrupts = <0x0 0x6e 0x4 0x0 0x6f 0x4 0x0 0x70 0x4>;
|
interrupt-names = "npu0_mmu", "npu1_mmu", "npu2_mmu";
|
clocks = <0x2 0x12d 0x2 0x122 0x2 0x124 0x2 0x12e 0x2 0x123 0x2 0x125>;
|
clock-names = "aclk0", "aclk1", "aclk2", "iface0", "iface1", "iface2";
|
#iommu-cells = <0x0>;
|
status = "okay";
|
phandle = <0xa5>;
|
};
|
|
vepu@fdb50000 {
|
compatible = "rockchip,vpu-encoder-v2";
|
reg = <0x0 0xfdb50000 0x0 0x400>;
|
interrupts = <0x0 0x78 0x4>;
|
interrupt-names = "irq_vepu";
|
clocks = <0x2 0x1c0 0x2 0x1c1>;
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
rockchip,normal-rates = <0x2367b880 0x0>;
|
assigned-clocks = <0x2 0x1c0>;
|
assigned-clock-rates = <0x2367b880>;
|
resets = <0x2 0x2c8 0x2 0x2c9>;
|
reset-names = "shared_video_a", "shared_video_h";
|
rockchip,skip-pmu-idle-request;
|
rockchip,disable-auto-freq;
|
iommus = <0xaa>;
|
rockchip,srv = <0xab>;
|
rockchip,taskqueue-node = <0x0>;
|
rockchip,resetgroup-node = <0x0>;
|
power-domains = <0x57 0x15>;
|
status = "okay";
|
phandle = <0x25f>;
|
};
|
|
vdpu@fdb50400 {
|
compatible = "rockchip,vpu-decoder-v2";
|
reg = <0x0 0xfdb50400 0x0 0x400>;
|
interrupts = <0x0 0x77 0x4>;
|
interrupt-names = "irq_vdpu";
|
clocks = <0x2 0x1c0 0x2 0x1c1>;
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
rockchip,normal-rates = <0x2367b880 0x0>;
|
assigned-clocks = <0x2 0x1c0>;
|
assigned-clock-rates = <0x2367b880>;
|
resets = <0x2 0x2c8 0x2 0x2c9>;
|
reset-names = "shared_video_a", "shared_video_h";
|
rockchip,skip-pmu-idle-request;
|
rockchip,disable-auto-freq;
|
iommus = <0xaa>;
|
rockchip,srv = <0xab>;
|
rockchip,taskqueue-node = <0x0>;
|
rockchip,resetgroup-node = <0x0>;
|
power-domains = <0x57 0x15>;
|
status = "okay";
|
phandle = <0x260>;
|
};
|
|
iommu@fdb50800 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdb50800 0x0 0x40>;
|
interrupts = <0x0 0x76 0x4>;
|
interrupt-names = "irq_vdpu_mmu";
|
clocks = <0x2 0x1c0 0x2 0x1c1>;
|
clock-names = "aclk", "iface";
|
power-domains = <0x57 0x15>;
|
#iommu-cells = <0x0>;
|
status = "okay";
|
phandle = <0xaa>;
|
};
|
|
avsd-plus@fdb51000 {
|
compatible = "rockchip,avs-plus-decoder";
|
reg = <0x0 0xfdb51000 0x0 0x200>;
|
interrupts = <0x0 0x77 0x4>;
|
interrupt-names = "irq_avsd";
|
clocks = <0x2 0x1c0 0x2 0x1c1>;
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
rockchip,normal-rates = <0x2367b880 0x0>;
|
assigned-clocks = <0x2 0x1c0>;
|
assigned-clock-rates = <0x2367b880>;
|
resets = <0x2 0x2c8 0x2 0x2c9>;
|
reset-names = "shared_video_a", "shared_video_h";
|
rockchip,skip-pmu-idle-request;
|
rockchip,disable-auto-freq;
|
iommus = <0xaa>;
|
power-domains = <0x57 0x15>;
|
rockchip,srv = <0xab>;
|
rockchip,taskqueue-node = <0x0>;
|
rockchip,resetgroup-node = <0x0>;
|
status = "okay";
|
phandle = <0x261>;
|
};
|
|
rga@fdb60000 {
|
compatible = "rockchip,rga3_core0";
|
reg = <0x0 0xfdb60000 0x0 0x1000>;
|
interrupts = <0x0 0x72 0x4>;
|
interrupt-names = "rga3_core0_irq";
|
clocks = <0x2 0x1ba 0x2 0x1b9 0x2 0x1bb>;
|
clock-names = "aclk_rga3_0", "hclk_rga3_0", "clk_rga3_0";
|
power-domains = <0x57 0x16>;
|
iommus = <0xac>;
|
status = "okay";
|
phandle = <0x262>;
|
};
|
|
iommu@fdb60f00 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdb60f00 0x0 0x100>;
|
interrupts = <0x0 0x72 0x4>;
|
interrupt-names = "rga3_0_mmu";
|
clocks = <0x2 0x1ba 0x2 0x1b9>;
|
clock-names = "aclk", "iface";
|
power-domains = <0x57 0x16>;
|
#iommu-cells = <0x0>;
|
status = "okay";
|
phandle = <0xac>;
|
};
|
|
rga@fdb70000 {
|
compatible = "rockchip,rga3_core1";
|
reg = <0x0 0xfdb70000 0x0 0x1000>;
|
interrupts = <0x0 0x73 0x4>;
|
interrupt-names = "rga3_core1_irq";
|
clocks = <0x2 0x18a 0x2 0x189 0x2 0x18b>;
|
clock-names = "aclk_rga3_1", "hclk_rga3_1", "clk_rga3_1";
|
power-domains = <0x57 0x1e>;
|
iommus = <0xad>;
|
status = "okay";
|
phandle = <0x263>;
|
};
|
|
iommu@fdb70f00 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdb70f00 0x0 0x100>;
|
interrupts = <0x0 0x73 0x4>;
|
interrupt-names = "rga3_1_mmu";
|
clocks = <0x2 0x18a 0x2 0x189>;
|
clock-names = "aclk", "iface";
|
power-domains = <0x57 0x1e>;
|
#iommu-cells = <0x0>;
|
status = "okay";
|
phandle = <0xad>;
|
};
|
|
rga@fdb80000 {
|
compatible = "rockchip,rga2_core0";
|
reg = <0x0 0xfdb80000 0x0 0x1000>;
|
interrupts = <0x0 0x74 0x4>;
|
interrupt-names = "rga2_irq";
|
clocks = <0x2 0x1b7 0x2 0x1b6 0x2 0x1b8>;
|
clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
|
power-domains = <0x57 0x15>;
|
status = "okay";
|
phandle = <0x264>;
|
};
|
|
jpegd@fdb90000 {
|
compatible = "rockchip,rkv-jpeg-decoder-v1";
|
reg = <0x0 0xfdb90000 0x0 0x400>;
|
interrupts = <0x0 0x81 0x4>;
|
interrupt-names = "irq_jpegd";
|
clocks = <0x2 0x1b4 0x2 0x1b5>;
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
rockchip,normal-rates = <0x23c34600 0x0>;
|
assigned-clocks = <0x2 0x1b4>;
|
assigned-clock-rates = <0x23c34600>;
|
resets = <0x2 0x2d2 0x2 0x2d3>;
|
reset-names = "video_a", "video_h";
|
rockchip,skip-pmu-idle-request;
|
iommus = <0xae>;
|
rockchip,srv = <0xab>;
|
rockchip,taskqueue-node = <0x1>;
|
power-domains = <0x57 0x15>;
|
status = "okay";
|
phandle = <0x265>;
|
};
|
|
iommu@fdb90480 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdb90480 0x0 0x40>;
|
interrupts = <0x0 0x82 0x4>;
|
interrupt-names = "irq_jpegd_mmu";
|
clocks = <0x2 0x1b4 0x2 0x1b5>;
|
clock-names = "aclk", "iface";
|
power-domains = <0x57 0x15>;
|
#iommu-cells = <0x0>;
|
status = "okay";
|
phandle = <0xae>;
|
};
|
|
jpege-core@fdba0000 {
|
compatible = "rockchip,vpu-jpege-core";
|
reg = <0x0 0xfdba0000 0x0 0x400>;
|
interrupts = <0x0 0x7a 0x4>;
|
interrupt-names = "irq_jpege0";
|
clocks = <0x2 0x1ac 0x2 0x1ad>;
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
rockchip,normal-rates = <0x2367b880 0x0>;
|
assigned-clocks = <0x2 0x1ac>;
|
assigned-clock-rates = <0x2367b880>;
|
resets = <0x2 0x2ca 0x2 0x2cb>;
|
reset-names = "video_a", "video_h";
|
rockchip,skip-pmu-idle-request;
|
rockchip,disable-auto-freq;
|
iommus = <0xaf>;
|
rockchip,srv = <0xab>;
|
rockchip,taskqueue-node = <0x2>;
|
rockchip,ccu = <0xb0>;
|
power-domains = <0x57 0x15>;
|
status = "okay";
|
phandle = <0x266>;
|
};
|
|
iommu@fdba0800 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdba0800 0x0 0x40>;
|
interrupts = <0x0 0x79 0x4>;
|
interrupt-names = "irq_jpege0_mmu";
|
clocks = <0x2 0x1ac 0x2 0x1ad>;
|
clock-names = "aclk", "iface";
|
power-domains = <0x57 0x15>;
|
#iommu-cells = <0x0>;
|
status = "okay";
|
phandle = <0xaf>;
|
};
|
|
jpege-core@fdba4000 {
|
compatible = "rockchip,vpu-jpege-core";
|
reg = <0x0 0xfdba4000 0x0 0x400>;
|
interrupts = <0x0 0x7c 0x4>;
|
interrupt-names = "irq_jpege1";
|
clocks = <0x2 0x1ae 0x2 0x1af>;
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
rockchip,normal-rates = <0x2367b880 0x0>;
|
assigned-clocks = <0x2 0x1ae>;
|
assigned-clock-rates = <0x2367b880>;
|
resets = <0x2 0x2cc 0x2 0x2cd>;
|
reset-names = "video_a", "video_h";
|
rockchip,skip-pmu-idle-request;
|
rockchip,disable-auto-freq;
|
iommus = <0xb1>;
|
rockchip,srv = <0xab>;
|
rockchip,taskqueue-node = <0x2>;
|
rockchip,ccu = <0xb0>;
|
power-domains = <0x57 0x15>;
|
status = "okay";
|
phandle = <0x267>;
|
};
|
|
iommu@fdba4800 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdba4800 0x0 0x40>;
|
interrupts = <0x0 0x7b 0x4>;
|
interrupt-names = "irq_jpege1_mmu";
|
clocks = <0x2 0x1ae 0x2 0x1af>;
|
clock-names = "aclk", "iface";
|
power-domains = <0x57 0x15>;
|
#iommu-cells = <0x0>;
|
status = "okay";
|
phandle = <0xb1>;
|
};
|
|
jpege-core@fdba8000 {
|
compatible = "rockchip,vpu-jpege-core";
|
reg = <0x0 0xfdba8000 0x0 0x400>;
|
interrupts = <0x0 0x7e 0x4>;
|
interrupt-names = "irq_jpege2";
|
clocks = <0x2 0x1b0 0x2 0x1b1>;
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
rockchip,normal-rates = <0x2367b880 0x0>;
|
assigned-clocks = <0x2 0x1b0>;
|
assigned-clock-rates = <0x2367b880>;
|
resets = <0x2 0x2ce 0x2 0x2cf>;
|
reset-names = "video_a", "video_h";
|
rockchip,skip-pmu-idle-request;
|
rockchip,disable-auto-freq;
|
iommus = <0xb2>;
|
rockchip,srv = <0xab>;
|
rockchip,taskqueue-node = <0x2>;
|
rockchip,ccu = <0xb0>;
|
power-domains = <0x57 0x15>;
|
status = "okay";
|
phandle = <0x268>;
|
};
|
|
iommu@fdba8800 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdba8800 0x0 0x40>;
|
interrupts = <0x0 0x7d 0x4>;
|
interrupt-names = "irq_jpege2_mmu";
|
clocks = <0x2 0x1b0 0x2 0x1b1>;
|
clock-names = "aclk", "iface";
|
power-domains = <0x57 0x15>;
|
#iommu-cells = <0x0>;
|
status = "okay";
|
phandle = <0xb2>;
|
};
|
|
jpege-core@fdbac000 {
|
compatible = "rockchip,vpu-jpege-core";
|
reg = <0x0 0xfdbac000 0x0 0x400>;
|
interrupts = <0x0 0x80 0x4>;
|
interrupt-names = "irq_jpege3";
|
clocks = <0x2 0x1b2 0x2 0x1b3>;
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
rockchip,normal-rates = <0x2367b880 0x0>;
|
assigned-clocks = <0x2 0x1b2>;
|
assigned-clock-rates = <0x2367b880>;
|
resets = <0x2 0x2d0 0x2 0x2d1>;
|
reset-names = "video_a", "video_h";
|
rockchip,skip-pmu-idle-request;
|
rockchip,disable-auto-freq;
|
iommus = <0xb3>;
|
rockchip,srv = <0xab>;
|
rockchip,taskqueue-node = <0x2>;
|
rockchip,ccu = <0xb0>;
|
power-domains = <0x57 0x15>;
|
status = "okay";
|
phandle = <0x269>;
|
};
|
|
iommu@fdbac800 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdbac800 0x0 0x40>;
|
interrupts = <0x0 0x7f 0x4>;
|
interrupt-names = "irq_jpege3_mmu";
|
clocks = <0x2 0x1b2 0x2 0x1b3>;
|
clock-names = "aclk", "iface";
|
power-domains = <0x57 0x15>;
|
#iommu-cells = <0x0>;
|
status = "okay";
|
phandle = <0xb3>;
|
};
|
|
iep@fdbb0000 {
|
compatible = "rockchip,iep-v2";
|
reg = <0x0 0xfdbb0000 0x0 0x500>;
|
interrupts = <0x0 0x75 0x4>;
|
interrupt-names = "irq_iep";
|
clocks = <0x2 0x1aa 0x2 0x1a9 0x2 0x1ab>;
|
clock-names = "aclk", "hclk", "sclk";
|
rockchip,normal-rates = <0x2367b880 0x0>;
|
assigned-clocks = <0x2 0x1aa>;
|
assigned-clock-rates = <0x2367b880>;
|
resets = <0x2 0x2d5 0x2 0x2d4 0x2 0x2d6>;
|
reset-names = "rst_a", "rst_h", "rst_s";
|
rockchip,skip-pmu-idle-request;
|
rockchip,disable-auto-freq;
|
power-domains = <0x57 0x15>;
|
rockchip,srv = <0xab>;
|
rockchip,taskqueue-node = <0x6>;
|
iommus = <0xb4>;
|
status = "okay";
|
phandle = <0x26a>;
|
};
|
|
iommu@fdbb0800 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdbb0800 0x0 0x100>;
|
interrupts = <0x0 0x75 0x4>;
|
interrupt-names = "irq_iep_mmu";
|
clocks = <0x2 0x1aa 0x2 0x1a9>;
|
clock-names = "aclk", "iface";
|
#iommu-cells = <0x0>;
|
power-domains = <0x57 0x15>;
|
status = "okay";
|
phandle = <0xb4>;
|
};
|
|
rkvenc-core@fdbd0000 {
|
compatible = "rockchip,rkv-encoder-v2-core";
|
reg = <0x0 0xfdbd0000 0x0 0x6000>;
|
interrupts = <0x0 0x65 0x4>;
|
interrupt-names = "irq_rkvenc0";
|
clocks = <0x2 0x1c5 0x2 0x1c4 0x2 0x1c6>;
|
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
|
rockchip,normal-rates = <0x1dcd6500 0x0 0x2faf0800>;
|
assigned-clocks = <0x2 0x1c5 0x2 0x1c6>;
|
assigned-clock-rates = <0x1dcd6500 0x2faf0800>;
|
resets = <0x2 0x2f5 0x2 0x2f4 0x2 0x2f6>;
|
reset-names = "video_a", "video_h", "video_core";
|
rockchip,skip-pmu-idle-request;
|
iommus = <0xb5>;
|
rockchip,srv = <0xab>;
|
rockchip,ccu = <0xb6>;
|
rockchip,taskqueue-node = <0x7>;
|
rockchip,task-capacity = <0x8>;
|
power-domains = <0x57 0x10>;
|
operating-points-v2 = <0xb7>;
|
status = "okay";
|
venc-supply = <0xb8>;
|
mem-supply = <0xb8>;
|
phandle = <0x26b>;
|
};
|
|
iommu@fdbdf000 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdbdf000 0x0 0x40 0x0 0xfdbdf040 0x0 0x40>;
|
interrupts = <0x0 0x63 0x4 0x0 0x64 0x4>;
|
interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1";
|
clocks = <0x2 0x1c5 0x2 0x1c4>;
|
clock-names = "aclk", "iface";
|
rockchip,disable-mmu-reset;
|
rockchip,enable-cmd-retry;
|
rockchip,shootdown-entire;
|
#iommu-cells = <0x0>;
|
power-domains = <0x57 0x10>;
|
status = "okay";
|
phandle = <0xb5>;
|
};
|
|
rkvenc-core@fdbe0000 {
|
compatible = "rockchip,rkv-encoder-v2-core";
|
reg = <0x0 0xfdbe0000 0x0 0x6000>;
|
interrupts = <0x0 0x68 0x4>;
|
interrupt-names = "irq_rkvenc1";
|
clocks = <0x2 0x1ca 0x2 0x1c9 0x2 0x1cb>;
|
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
|
rockchip,normal-rates = <0x1dcd6500 0x0 0x2faf0800>;
|
assigned-clocks = <0x2 0x1ca 0x2 0x1cb>;
|
assigned-clock-rates = <0x1dcd6500 0x2faf0800>;
|
resets = <0x2 0x305 0x2 0x304 0x2 0x306>;
|
reset-names = "video_a", "video_h", "video_core";
|
rockchip,skip-pmu-idle-request;
|
iommus = <0xb9>;
|
rockchip,srv = <0xab>;
|
rockchip,ccu = <0xb6>;
|
rockchip,taskqueue-node = <0x7>;
|
rockchip,task-capacity = <0x8>;
|
power-domains = <0x57 0x11>;
|
operating-points-v2 = <0xb7>;
|
status = "okay";
|
venc-supply = <0xb8>;
|
mem-supply = <0xb8>;
|
phandle = <0x26c>;
|
};
|
|
iommu@fdbef000 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdbef000 0x0 0x40 0x0 0xfdbef040 0x0 0x40>;
|
interrupts = <0x0 0x66 0x4 0x0 0x67 0x4>;
|
interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1";
|
clocks = <0x2 0x1ca 0x2 0x1c9>;
|
lock-names = "aclk", "iface";
|
rockchip,disable-mmu-reset;
|
rockchip,enable-cmd-retry;
|
rockchip,shootdown-entire;
|
#iommu-cells = <0x0>;
|
power-domains = <0x57 0x11>;
|
status = "okay";
|
phandle = <0xb9>;
|
};
|
|
venc-opp-table {
|
compatible = "operating-points-v2";
|
nvmem-cells = <0xba 0xbb>;
|
nvmem-cell-names = "leakage", "opp-info";
|
rockchip,leakage-voltage-sel = <0x1 0xf 0x0 0x10 0x19 0x1 0x1a 0xfe 0x2>;
|
rockchip,grf = <0xbc>;
|
volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>;
|
phandle = <0xb7>;
|
|
opp-800000000 {
|
opp-hz = <0x0 0x2faf0800>;
|
opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
opp-microvolt-L0 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>;
|
opp-microvolt-L1 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>;
|
opp-microvolt-L2 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>;
|
};
|
};
|
|
rkvdec-ccu@fdc30000 {
|
compatible = "rockchip,rkv-decoder-v2-ccu";
|
reg = <0x0 0xfdc30000 0x0 0x100>;
|
reg-names = "ccu";
|
clocks = <0x2 0x18e>;
|
clock-names = "aclk_ccu";
|
assigned-clocks = <0x2 0x18e>;
|
assigned-clock-rates = <0x23c34600>;
|
resets = <0x2 0x282>;
|
reset-names = "video_ccu";
|
rockchip,skip-pmu-idle-request;
|
rockchip,ccu-mode = <0x1>;
|
power-domains = <0x57 0xe>;
|
status = "okay";
|
phandle = <0xbe>;
|
};
|
|
rkvdec-core@fdc38000 {
|
compatible = "rockchip,rkv-decoder-v2";
|
reg = <0x0 0xfdc38100 0x0 0x400 0x0 0xfdc38000 0x0 0x100>;
|
reg-names = "regs", "link";
|
interrupts = <0x0 0x5f 0x4>;
|
interrupt-names = "irq_rkvdec0";
|
clocks = <0x2 0x190 0x2 0x18f 0x2 0x193 0x2 0x191 0x2 0x192>;
|
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac", "clk_hevc_cabac";
|
rockchip,normal-rates = <0x2faf0800 0x0 0x23c34600 0x23c34600 0x3b9aca00>;
|
assigned-clocks = <0x2 0x190 0x2 0x193 0x2 0x191 0x2 0x192>;
|
assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>;
|
resets = <0x2 0x284 0x2 0x283 0x2 0x289 0x2 0x287 0x2 0x288>;
|
reset-names = "video_a", "video_h", "video_core", "video_cabac", "video_hevc_cabac";
|
rockchip,skip-pmu-idle-request;
|
iommus = <0xbd>;
|
rockchip,srv = <0xab>;
|
rockchip,ccu = <0xbe>;
|
rockchip,core-mask = <0x10001>;
|
rockchip,task-capacity = <0x10>;
|
rockchip,taskqueue-node = <0x9>;
|
rockchip,sram = <0xbf>;
|
rockchip,rcb-iova = <0xfff00000 0x100000>;
|
rockchip,rcb-info = <0x88 0x6000 0x89 0xc000 0x8d 0x16000 0x8c 0xc000 0x8b 0x2c000 0x85 0xc000 0x86 0x2000 0x87 0x1100 0x8a 0x3300 0x8e 0x47300>;
|
rockchip,rcb-min-width = <0x200>;
|
power-domains = <0x57 0xe>;
|
status = "okay";
|
phandle = <0x26d>;
|
};
|
|
iommu@fdc38700 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdc38700 0x0 0x40 0x0 0xfdc38740 0x0 0x40>;
|
interrupts = <0x0 0x60 0x4>;
|
interrupt-names = "irq_rkvdec0_mmu";
|
clocks = <0x2 0x190 0x2 0x18f>;
|
clock-names = "aclk", "iface";
|
rockchip,disable-mmu-reset;
|
rockchip,enable-cmd-retry;
|
rockchip,shootdown-entire;
|
rockchip,master-handle-irq;
|
#iommu-cells = <0x0>;
|
power-domains = <0x57 0xe>;
|
status = "okay";
|
phandle = <0xbd>;
|
};
|
|
rkvdec-core@fdc48000 {
|
compatible = "rockchip,rkv-decoder-v2";
|
reg = <0x0 0xfdc48100 0x0 0x400 0x0 0xfdc48000 0x0 0x100>;
|
reg-names = "regs", "link";
|
interrupts = <0x0 0x61 0x4>;
|
interrupt-names = "irq_rkvdec1";
|
clocks = <0x2 0x195 0x2 0x194 0x2 0x198 0x2 0x196 0x2 0x197>;
|
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac", "clk_hevc_cabac";
|
rockchip,normal-rates = <0x2faf0800 0x0 0x23c34600 0x23c34600 0x3b9aca00>;
|
assigned-clocks = <0x2 0x195 0x2 0x198 0x2 0x196 0x2 0x197>;
|
assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>;
|
resets = <0x2 0x293 0x2 0x292 0x2 0x298 0x2 0x296 0x2 0x297>;
|
reset-names = "video_a", "video_h", "video_core", "video_cabac", "video_hevc_cabac";
|
rockchip,skip-pmu-idle-request;
|
iommus = <0xc0>;
|
rockchip,srv = <0xab>;
|
rockchip,ccu = <0xbe>;
|
rockchip,core-mask = <0x20002>;
|
rockchip,task-capacity = <0x10>;
|
rockchip,taskqueue-node = <0x9>;
|
rockchip,sram = <0xc1>;
|
rockchip,rcb-iova = <0xffe00000 0x100000>;
|
rockchip,rcb-info = <0x88 0x6000 0x89 0xc000 0x8d 0x16000 0x8c 0xc000 0x8b 0x2c000 0x85 0xc000 0x86 0x2000 0x87 0x1100 0x8a 0x3300 0x8e 0x47300>;
|
rockchip,rcb-min-width = <0x200>;
|
power-domains = <0x57 0xf>;
|
status = "okay";
|
phandle = <0x26e>;
|
};
|
|
iommu@fdc48700 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdc48700 0x0 0x40 0x0 0xfdc48740 0x0 0x40>;
|
interrupts = <0x0 0x62 0x4>;
|
interrupt-names = "irq_rkvdec1_mmu";
|
clocks = <0x2 0x195 0x2 0x194>;
|
clock-names = "aclk", "iface";
|
rockchip,disable-mmu-reset;
|
rockchip,enable-cmd-retry;
|
rockchip,shootdown-entire;
|
rockchip,master-handle-irq;
|
#iommu-cells = <0x0>;
|
power-domains = <0x57 0xf>;
|
status = "okay";
|
phandle = <0xc0>;
|
};
|
|
av1d@fdc70000 {
|
compatible = "rockchip,av1-decoder";
|
reg = <0x0 0xfdc70000 0x0 0x800 0x0 0xfdc80000 0x0 0x400 0x0 0xfdc90000 0x0 0x400>;
|
reg-names = "vcd", "cache", "afbc";
|
interrupts = <0x0 0x6c 0x4 0x0 0x6b 0x4 0x0 0x6a 0x4>;
|
interrupt-names = "irq_av1d", "irq_cache", "irq_afbc";
|
clocks = <0x2 0x49 0x2 0x4b>;
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
rockchip,normal-rates = <0x17d78400 0x17d78400>;
|
assigned-clocks = <0x2 0x49 0x2 0x4b>;
|
assigned-clock-rates = <0x17d78400 0x17d78400>;
|
resets = <0x2 0x442 0x2 0x445>;
|
reset-names = "video_a", "video_h";
|
iommus = <0xc2>;
|
rockchip,srv = <0xab>;
|
rockchip,taskqueue-node = <0xb>;
|
power-domains = <0x57 0x17>;
|
status = "disabled";
|
phandle = <0x26f>;
|
};
|
|
iommu@fdca0000 {
|
compatible = "rockchip,iommu-av1";
|
reg = <0x0 0xfdca0000 0x0 0x600>;
|
interrupts = <0x0 0x6d 0x4>;
|
interrupt-names = "irq_av1d_mmu";
|
clocks = <0x2 0x49 0x2 0x4b>;
|
clock-names = "aclk", "iface";
|
#iommu-cells = <0x0>;
|
power-domains = <0x57 0x17>;
|
status = "okay";
|
phandle = <0xc2>;
|
};
|
|
rkisp-unite@fdcb0000 {
|
compatible = "rockchip,rk3588-rkisp-unite";
|
reg = <0x0 0xfdcb0000 0x0 0x10000 0x0 0xfdcc0000 0x0 0x10000>;
|
interrupts = <0x0 0x87 0x4 0x0 0x89 0x4 0x0 0x8a 0x4>;
|
interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
|
clocks = <0x2 0x1de 0x2 0x1df 0x2 0x1db 0x2 0x1dc 0x2 0x1dd 0x2 0x120 0x2 0x121 0x2 0x11d 0x2 0x11e 0x2 0x11f>;
|
clock-names = "aclk_isp0", "hclk_isp0", "clk_isp_core0", "clk_isp_core_marvin0", "clk_isp_core_vicap0", "aclk_isp1", "hclk_isp1", "clk_isp_core1", "clk_isp_core_marvin1", "clk_isp_core_vicap1";
|
power-domains = <0x57 0x1c>;
|
iommus = <0xc3>;
|
status = "disabled";
|
phandle = <0x270>;
|
};
|
|
rkisp@fdcb0000 {
|
compatible = "rockchip,rk3588-rkisp";
|
reg = <0x0 0xfdcb0000 0x0 0x7f00>;
|
interrupts = <0x0 0x83 0x4 0x0 0x85 0x4 0x0 0x86 0x4>;
|
interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
|
clocks = <0x2 0x1de 0x2 0x1df 0x2 0x1db 0x2 0x1dc 0x2 0x1dd>;
|
clock-names = "aclk_isp", "hclk_isp", "clk_isp_core", "clk_isp_core_marvin", "clk_isp_core_vicap";
|
power-domains = <0x57 0x1b>;
|
iommus = <0xc4>;
|
status = "disabled";
|
phandle = <0x50>;
|
};
|
|
rkisp-unite-mmu@fdcb7f00 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdcb7f00 0x0 0x100 0x0 0xfdcc7f00 0x0 0x100>;
|
interrupts = <0x0 0x84 0x4 0x0 0x88 0x4>;
|
interrupt-names = "isp0_mmu", "isp1_mmu";
|
clocks = <0x2 0x1de 0x2 0x1df 0x2 0x120 0x2 0x121>;
|
clock-names = "aclk0", "iface0", "aclk1", "iface1";
|
power-domains = <0x57 0x1c>;
|
#iommu-cells = <0x0>;
|
rockchip,disable-mmu-reset;
|
status = "disabled";
|
phandle = <0xc3>;
|
};
|
|
iommu@fdcb7f00 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdcb7f00 0x0 0x100>;
|
interrupts = <0x0 0x84 0x4>;
|
interrupt-names = "isp0_mmu";
|
clocks = <0x2 0x1de 0x2 0x1df>;
|
clock-names = "aclk", "iface";
|
power-domains = <0x57 0x1b>;
|
#iommu-cells = <0x0>;
|
rockchip,disable-mmu-reset;
|
status = "disabled";
|
phandle = <0xc4>;
|
};
|
|
rkisp@fdcc0000 {
|
compatible = "rockchip,rk3588-rkisp";
|
reg = <0x0 0xfdcc0000 0x0 0x7f00>;
|
interrupts = <0x0 0x87 0x4 0x0 0x89 0x4 0x0 0x8a 0x4>;
|
interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
|
clocks = <0x2 0x120 0x2 0x121 0x2 0x11d 0x2 0x11e 0x2 0x11f>;
|
clock-names = "aclk_isp", "hclk_isp", "clk_isp_core", "clk_isp_core_marvin", "clk_isp_core_vicap";
|
power-domains = <0x57 0x1c>;
|
iommus = <0xc5>;
|
status = "disabled";
|
phandle = <0x51>;
|
};
|
|
iommu@fdcc7f00 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdcc7f00 0x0 0x100>;
|
interrupts = <0x0 0x88 0x4>;
|
interrupt-names = "isp1_mmu";
|
clocks = <0x2 0x120 0x2 0x121>;
|
clock-names = "aclk", "iface";
|
power-domains = <0x57 0x1c>;
|
#iommu-cells = <0x0>;
|
rockchip,disable-mmu-reset;
|
status = "disabled";
|
phandle = <0xc5>;
|
};
|
|
rkispp@fdcd0000 {
|
compatible = "rockchip,rk3588-rkispp";
|
reg = <0x0 0xfdcd0000 0x0 0xf00>;
|
interrupts = <0x0 0x8b 0x4>;
|
interrupt-names = "fec_irq";
|
clocks = <0x2 0x1d5 0x2 0x1d6 0x2 0x1d7>;
|
clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
|
assigned-clocks = <0x2 0x1d6>;
|
assigned-clock-rates = <0x5f5e100>;
|
power-domains = <0x57 0x1d>;
|
iommus = <0xc6>;
|
status = "disabled";
|
phandle = <0x52>;
|
};
|
|
iommu@fdcd0f00 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdcd0f00 0x0 0x100>;
|
interrupts = <0x0 0x8c 0x4>;
|
interrupt-names = "fec0_mmu";
|
clocks = <0x2 0x1d5 0x2 0x1d6 0x2 0x1d7>;
|
clock-names = "aclk", "iface", "pclk";
|
power-domains = <0x57 0x1d>;
|
#iommu-cells = <0x0>;
|
rockchip,disable-mmu-reset;
|
status = "disabled";
|
phandle = <0xc6>;
|
};
|
|
rkispp@fdcd8000 {
|
compatible = "rockchip,rk3588-rkispp";
|
reg = <0x0 0xfdcd8000 0x0 0xf00>;
|
interrupts = <0x0 0x8d 0x4>;
|
interrupt-names = "fec_irq";
|
clocks = <0x2 0x1d8 0x2 0x1d9 0x2 0x1da>;
|
clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
|
assigned-clocks = <0x2 0x1d9>;
|
assigned-clock-rates = <0x5f5e100>;
|
power-domains = <0x57 0x1d>;
|
iommus = <0xc7>;
|
status = "disabled";
|
phandle = <0x53>;
|
};
|
|
iommu@fdcd8f00 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdcd8f00 0x0 0x100>;
|
interrupts = <0x0 0x8e 0x4>;
|
interrupt-names = "fec1_mmu";
|
clocks = <0x2 0x1d8 0x2 0x1d9 0x2 0x1da>;
|
clock-names = "aclk", "iface", "pclk";
|
power-domains = <0x57 0x1d>;
|
#iommu-cells = <0x0>;
|
rockchip,disable-mmu-reset;
|
status = "disabled";
|
phandle = <0xc7>;
|
};
|
|
rkcif@fdce0000 {
|
compatible = "rockchip,rk3588-cif";
|
reg = <0x0 0xfdce0000 0x0 0x800>;
|
reg-names = "cif_regs";
|
interrupts = <0x0 0x9b 0x4>;
|
interrupt-names = "cif-intr";
|
clocks = <0x2 0x1e4 0x2 0x1e5 0x2 0x1e3 0x2 0x1cd 0x2 0x1ce>;
|
clock-names = "aclk_cif", "hclk_cif", "dclk_cif", "iclk_host0", "iclk_host1";
|
resets = <0x2 0x317 0x2 0x318 0x2 0x316 0x2 0x334 0x2 0x335 0x2 0x336 0x2 0x337 0x2 0x338 0x2 0x339>;
|
reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", "rst_cif_host0", "rst_cif_host1", "rst_cif_host2", "rst_cif_host3", "rst_cif_host4", "rst_cif_host5";
|
assigned-clocks = <0x2 0x1e3>;
|
assigned-clock-rates = <0x23c34600>;
|
power-domains = <0x57 0x1b>;
|
rockchip,grf = <0xbc>;
|
iommus = <0x4a>;
|
nvmem-cells = <0x21 0xc8 0xc9>;
|
nvmem-cell-names = "specification", "package_low", "package_high";
|
status = "disabled";
|
phandle = <0x49>;
|
};
|
|
iommu@fdce0800 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdce0800 0x0 0x100 0x0 0xfdce0900 0x0 0x100>;
|
interrupts = <0x0 0x71 0x4>;
|
interrupt-names = "cif_mmu";
|
clocks = <0x2 0x1e4 0x2 0x1e5>;
|
clock-names = "aclk", "iface";
|
power-domains = <0x57 0x1b>;
|
rockchip,disable-mmu-reset;
|
#iommu-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x4a>;
|
};
|
|
mipi0-csi2-hw@fdd10000 {
|
compatible = "rockchip,rk3588-mipi-csi2-hw";
|
reg = <0x0 0xfdd10000 0x0 0x10000>;
|
reg-names = "csihost_regs";
|
interrupts = <0x0 0x8f 0x4 0x0 0x90 0x4>;
|
interrupt-names = "csi-intr1", "csi-intr2";
|
clocks = <0x2 0x1cf>;
|
clock-names = "pclk_csi2host";
|
resets = <0x2 0x324>;
|
reset-names = "srst_csihost_p";
|
status = "okay";
|
phandle = <0x43>;
|
};
|
|
mipi1-csi2-hw@fdd20000 {
|
compatible = "rockchip,rk3588-mipi-csi2-hw";
|
reg = <0x0 0xfdd20000 0x0 0x10000>;
|
reg-names = "csihost_regs";
|
interrupts = <0x0 0x91 0x4 0x0 0x92 0x4>;
|
interrupt-names = "csi-intr1", "csi-intr2";
|
clocks = <0x2 0x1d0>;
|
clock-names = "pclk_csi2host";
|
resets = <0x2 0x325>;
|
reset-names = "srst_csihost_p";
|
status = "okay";
|
phandle = <0x44>;
|
};
|
|
mipi2-csi2-hw@fdd30000 {
|
compatible = "rockchip,rk3588-mipi-csi2-hw";
|
reg = <0x0 0xfdd30000 0x0 0x10000>;
|
reg-names = "csihost_regs";
|
interrupts = <0x0 0x93 0x4 0x0 0x94 0x4>;
|
interrupt-names = "csi-intr1", "csi-intr2";
|
clocks = <0x2 0x1d1>;
|
clock-names = "pclk_csi2host";
|
resets = <0x2 0x326>;
|
reset-names = "srst_csihost_p";
|
status = "okay";
|
phandle = <0x45>;
|
};
|
|
mipi3-csi2-hw@fdd40000 {
|
compatible = "rockchip,rk3588-mipi-csi2-hw";
|
reg = <0x0 0xfdd40000 0x0 0x10000>;
|
reg-names = "csihost_regs";
|
interrupts = <0x0 0x95 0x4 0x0 0x96 0x4>;
|
interrupt-names = "csi-intr1", "csi-intr2";
|
clocks = <0x2 0x1d2>;
|
clock-names = "pclk_csi2host";
|
resets = <0x2 0x327>;
|
reset-names = "srst_csihost_p";
|
status = "okay";
|
phandle = <0x46>;
|
};
|
|
mipi4-csi2-hw@fdd50000 {
|
compatible = "rockchip,rk3588-mipi-csi2-hw";
|
reg = <0x0 0xfdd50000 0x0 0x10000>;
|
reg-names = "csihost_regs";
|
interrupts = <0x0 0x97 0x4 0x0 0x98 0x4>;
|
interrupt-names = "csi-intr1", "csi-intr2";
|
clocks = <0x2 0x1d3>;
|
clock-names = "pclk_csi2host";
|
resets = <0x2 0x328>;
|
reset-names = "srst_csihost_p";
|
status = "okay";
|
phandle = <0x47>;
|
};
|
|
mipi5-csi2-hw@fdd60000 {
|
compatible = "rockchip,rk3588-mipi-csi2-hw";
|
reg = <0x0 0xfdd60000 0x0 0x10000>;
|
reg-names = "csihost_regs";
|
interrupts = <0x0 0x99 0x4 0x0 0x9a 0x4>;
|
interrupt-names = "csi-intr1", "csi-intr2";
|
clocks = <0x2 0x1d4>;
|
clock-names = "pclk_csi2host";
|
resets = <0x2 0x329>;
|
reset-names = "srst_csihost_p";
|
status = "okay";
|
phandle = <0x48>;
|
};
|
|
vop@fdd90000 {
|
compatible = "rockchip,rk3588-vop";
|
reg = <0x0 0xfdd90000 0x0 0x4200 0x0 0xfdd95000 0x0 0x1000>;
|
reg-names = "regs", "gamma_lut";
|
interrupts = <0x0 0x9c 0x4>;
|
clocks = <0x2 0x270 0x2 0x26f 0x2 0x274 0x2 0x275 0x2 0x276 0x2 0x277 0x2 0x26e 0x2 0x271 0x2 0x272 0x2 0x273>;
|
clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", "pclk_vop", "dclk_src_vp0", "dclk_src_vp1", "dclk_src_vp2";
|
assigned-clocks = <0x2 0x270>;
|
assigned-clock-rates = <0x2cb41780>;
|
resets = <0x2 0x349 0x2 0x348 0x2 0x34d 0x2 0x350 0x2 0x351 0x2 0x352>;
|
reset-names = "axi", "ahb", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3";
|
iommus = <0xca>;
|
power-domains = <0x57 0x18>;
|
rockchip,grf = <0xbc>;
|
rockchip,vop-grf = <0xcb>;
|
rockchip,vo1-grf = <0xcc>;
|
rockchip,pmu = <0xcd>;
|
status = "okay";
|
phandle = <0x271>;
|
|
ports {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
phandle = <0x31>;
|
|
port@0 {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
reg = <0x0>;
|
rockchip,plane-mask = <0x5>;
|
rockchip,primary-plane = <0x2>;
|
phandle = <0x272>;
|
|
endpoint@0 {
|
reg = <0x0>;
|
remote-endpoint = <0xce>;
|
phandle = <0xf4>;
|
};
|
|
endpoint@1 {
|
reg = <0x1>;
|
remote-endpoint = <0xcf>;
|
phandle = <0x100>;
|
};
|
|
endpoint@2 {
|
reg = <0x2>;
|
remote-endpoint = <0xd0>;
|
phandle = <0x38>;
|
};
|
|
endpoint@3 {
|
reg = <0x3>;
|
remote-endpoint = <0xd1>;
|
phandle = <0x1a2>;
|
};
|
|
endpoint@4 {
|
reg = <0x4>;
|
remote-endpoint = <0xd2>;
|
phandle = <0x1ad>;
|
};
|
|
endpoint@5 {
|
reg = <0x5>;
|
remote-endpoint = <0xd3>;
|
phandle = <0x1aa>;
|
};
|
};
|
|
port@1 {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
reg = <0x1>;
|
rockchip,plane-mask = <0xa>;
|
rockchip,primary-plane = <0x3>;
|
phandle = <0x273>;
|
|
endpoint@0 {
|
reg = <0x0>;
|
remote-endpoint = <0xd4>;
|
phandle = <0x33>;
|
};
|
|
endpoint@1 {
|
reg = <0x1>;
|
remote-endpoint = <0xd5>;
|
phandle = <0x101>;
|
};
|
|
endpoint@2 {
|
reg = <0x2>;
|
remote-endpoint = <0xd6>;
|
phandle = <0xfd>;
|
};
|
|
endpoint@3 {
|
reg = <0x3>;
|
remote-endpoint = <0xd7>;
|
phandle = <0x3a>;
|
};
|
|
endpoint@4 {
|
reg = <0x4>;
|
remote-endpoint = <0xd8>;
|
phandle = <0x1ae>;
|
};
|
|
endpoint@5 {
|
reg = <0x5>;
|
remote-endpoint = <0xd9>;
|
phandle = <0x3b>;
|
};
|
};
|
|
port@2 {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
reg = <0x2>;
|
assigned-clocks = <0x2 0x273>;
|
assigned-clock-parents = <0x2 0x4>;
|
rockchip,plane-mask = <0x140>;
|
rockchip,primary-plane = <0x8>;
|
phandle = <0x274>;
|
|
endpoint@0 {
|
reg = <0x0>;
|
remote-endpoint = <0xda>;
|
phandle = <0xf5>;
|
};
|
|
endpoint@1 {
|
reg = <0x1>;
|
remote-endpoint = <0xdb>;
|
phandle = <0x36>;
|
};
|
|
endpoint@2 {
|
reg = <0x2>;
|
remote-endpoint = <0xdc>;
|
phandle = <0xfe>;
|
};
|
|
endpoint@3 {
|
reg = <0x3>;
|
remote-endpoint = <0xdd>;
|
phandle = <0xe7>;
|
};
|
|
endpoint@4 {
|
reg = <0x4>;
|
remote-endpoint = <0xde>;
|
phandle = <0xec>;
|
};
|
|
endpoint@5 {
|
reg = <0x5>;
|
remote-endpoint = <0xdf>;
|
phandle = <0x1a3>;
|
};
|
|
endpoint@6 {
|
reg = <0x6>;
|
remote-endpoint = <0xe0>;
|
phandle = <0x37>;
|
};
|
|
endpoint@7 {
|
reg = <0x7>;
|
remote-endpoint = <0xe1>;
|
phandle = <0x1ab>;
|
};
|
};
|
|
port@3 {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
reg = <0x3>;
|
rockchip,plane-mask = <0x280>;
|
rockchip,primary-plane = <0x9>;
|
phandle = <0x275>;
|
|
endpoint@0 {
|
reg = <0x0>;
|
remote-endpoint = <0xe2>;
|
phandle = <0x34>;
|
};
|
|
endpoint@1 {
|
reg = <0x1>;
|
remote-endpoint = <0xe3>;
|
phandle = <0x35>;
|
};
|
|
endpoint@2 {
|
reg = <0x2>;
|
remote-endpoint = <0xe4>;
|
phandle = <0x39>;
|
};
|
};
|
};
|
};
|
|
iommu@fdd97e00 {
|
compatible = "rockchip,iommu-v2";
|
reg = <0x0 0xfdd97e00 0x0 0x100 0x0 0xfdd97f00 0x0 0x100>;
|
interrupts = <0x0 0x9c 0x4>;
|
interrupt-names = "vop_mmu";
|
clocks = <0x2 0x270 0x2 0x26f>;
|
clock-names = "aclk", "iface";
|
#iommu-cells = <0x0>;
|
rockchip,disable-device-link-resume;
|
rockchip,shootdown-entire;
|
status = "okay";
|
phandle = <0xca>;
|
};
|
|
spdif-tx@fddb0000 {
|
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
|
reg = <0x0 0xfddb0000 0x0 0x1000>;
|
interrupts = <0x0 0xc3 0x4>;
|
dmas = <0xe5 0x6>;
|
dma-names = "tx";
|
clock-names = "mclk", "hclk";
|
clocks = <0x2 0x209 0x2 0x204>;
|
assigned-clocks = <0x2 0x205>;
|
assigned-clock-parents = <0x2 0x5>;
|
power-domains = <0x57 0x19>;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x1cd>;
|
};
|
|
i2s@fddc0000 {
|
compatible = "rockchip,rk3588-i2s-tdm";
|
reg = <0x0 0xfddc0000 0x0 0x1000>;
|
interrupts = <0x0 0xb8 0x4>;
|
clocks = <0x2 0x1fb 0x2 0x1fb 0x2 0x1f0>;
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
assigned-clocks = <0x2 0x1f9>;
|
assigned-clock-parents = <0x2 0x5>;
|
dmas = <0xe6 0x0>;
|
dma-names = "tx";
|
power-domains = <0x57 0x19>;
|
resets = <0x2 0x38d>;
|
reset-names = "tx-m";
|
rockchip,playback-only;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x276>;
|
};
|
|
spdif-tx@fdde0000 {
|
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
|
reg = <0x0 0xfdde0000 0x0 0x1000>;
|
interrupts = <0x0 0xc4 0x4>;
|
dmas = <0xe5 0x7>;
|
dma-names = "tx";
|
clock-names = "mclk", "hclk";
|
clocks = <0x2 0x257 0x2 0x253>;
|
assigned-clocks = <0x2 0x254>;
|
assigned-clock-parents = <0x2 0x5>;
|
power-domains = <0x57 0x1a>;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x277>;
|
};
|
|
i2s@fddf0000 {
|
compatible = "rockchip,rk3588-i2s-tdm";
|
reg = <0x0 0xfddf0000 0x0 0x1000>;
|
interrupts = <0x0 0xb9 0x4>;
|
clocks = <0x2 0x246 0x2 0x246 0x2 0x248>;
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
assigned-clocks = <0x2 0x243>;
|
assigned-clock-parents = <0x2 0x7>;
|
dmas = <0xe6 0x2>;
|
dma-names = "tx";
|
power-domains = <0x57 0x1a>;
|
resets = <0x2 0x3e8>;
|
reset-names = "tx-m";
|
rockchip,always-on;
|
rockchip,hdmi-path;
|
rockchip,playback-only;
|
#sound-dai-cells = <0x0>;
|
status = "okay";
|
phandle = <0x1c9>;
|
};
|
|
i2s@fddfc000 {
|
compatible = "rockchip,rk3588-i2s-tdm";
|
reg = <0x0 0xfddfc000 0x0 0x1000>;
|
interrupts = <0x0 0xbd 0x4>;
|
clocks = <0x2 0x242 0x2 0x242 0x2 0x23e>;
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
assigned-clocks = <0x2 0x23f>;
|
assigned-clock-parents = <0x2 0x5>;
|
dmas = <0xe6 0x17>;
|
dma-names = "rx";
|
power-domains = <0x57 0x1a>;
|
resets = <0x2 0x413>;
|
reset-names = "rx-m";
|
rockchip,capture-only;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x278>;
|
};
|
|
spdif-rx@fde08000 {
|
compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
|
reg = <0x0 0xfde08000 0x0 0x1000>;
|
interrupts = <0x0 0xc7 0x4>;
|
clocks = <0x2 0x25e 0x2 0x25d>;
|
clock-names = "mclk", "hclk";
|
assigned-clocks = <0x2 0x25e>;
|
assigned-clock-parents = <0x2 0x5>;
|
dmas = <0x6f 0x15>;
|
dma-names = "rx";
|
power-domains = <0x57 0x1a>;
|
resets = <0x2 0x3fd>;
|
reset-names = "spdifrx-m";
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x279>;
|
};
|
|
dsi@fde20000 {
|
compatible = "rockchip,rk3588-mipi-dsi2";
|
reg = <0x0 0xfde20000 0x0 0x10000>;
|
interrupts = <0x0 0xa7 0x4>;
|
clocks = <0x2 0x278 0x2 0x27a>;
|
clock-names = "pclk", "sys_clk";
|
resets = <0x2 0x354>;
|
reset-names = "apb";
|
power-domains = <0x57 0x18>;
|
phys = <0x2f>;
|
phy-names = "dcphy";
|
rockchip,grf = <0xcb>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x27a>;
|
|
ports {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
port@0 {
|
reg = <0x0>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
phandle = <0x27b>;
|
|
endpoint@0 {
|
reg = <0x0>;
|
remote-endpoint = <0xe7>;
|
status = "disabled";
|
phandle = <0xdd>;
|
};
|
|
endpoint@1 {
|
reg = <0x1>;
|
remote-endpoint = <0x34>;
|
status = "okay";
|
phandle = <0xe2>;
|
};
|
};
|
|
port@1 {
|
reg = <0x1>;
|
|
endpoint {
|
remote-endpoint = <0xe8>;
|
phandle = <0xeb>;
|
};
|
};
|
};
|
|
panel@0 {
|
status = "okay";
|
compatible = "simple-panel-dsi";
|
reg = <0x0>;
|
backlight = <0xe9>;
|
reset-delay-ms = <0xc8>;
|
enable-delay-ms = <0x3c>;
|
init-delay-ms = <0x78>;
|
prepare-delay-ms = <0x78>;
|
unprepare-delay-ms = <0x78>;
|
disable-delay-ms = <0x3c>;
|
dsi,flags = <0xa03>;
|
dsi,format = <0x0>;
|
dsi,lanes = <0x4>;
|
panel-init-sequence = <0x390004ff 0x98810315 0x20100 0x15000202 0x150002 0x3531500 0x204d315 0x20500 0x15000206 0xd150002 0x7081500 0x2080015 0x20900 0x1500020a 0x150002 0xb001500 0x20c0015 0x20d00 0x1500020e 0x150002 0xf281500 0x2102815 0x21100 0x15000212 0x150002 0x13001500 0x2140015 0x21500 0x15000216 0x150002 0x17001500 0x2180015 0x21900 0x1500021a 0x150002 0x1b001500 0x21c0015 0x21d00 0x1500021e 0x40150002 0x1f801500 0x2200615 0x22101 0x15000222 0x150002 0x23001500 0x2240015 0x22500 0x15000226 0x150002 0x27001500 0x2283315 0x22933 0x1500022a 0x150002 0x2b001500 0x22c0015 0x22d00 0x1500022e 0x150002 0x2f001500 0x2300015 0x23100 0x15000232 0x150002 0x33001500 0x2340315 0x23500 0x15000236 0x150002 0x37001500 0x2389615 0x23900 0x1500023a 0x150002 0x3b001500 0x23c0015 0x23d00 0x1500023e 0x150002 0x3f001500 0x2400015 0x24100 0x15000242 0x150002 0x43001500 0x2440015 0x25000 0x15000251 0x23150002 0x52451500 0x2536715 0x25489 0x15000255 0xab150002 0x56011500 0x2572315 0x25845 0x15000259 0x67150002 0x5a891500 0x25bab15 0x25ccd 0x1500025d 0xef150002 0x5e001500 0x25f0815 0x26008 0x15000261 0x6150002 0x62061500 0x2630115 0x26401 0x15000265 0x150002 0x66001500 0x2670215 0x26815 0x15000269 0x15150002 0x6a141500 0x26b1415 0x26c0d 0x1500026d 0xd150002 0x6e0c1500 0x26f0c15 0x2700f 0x15000271 0xf150002 0x720e1500 0x2730e15 0x27402 0x15000275 0x8150002 0x76081500 0x2770615 0x27806 0x15000279 0x1150002 0x7a011500 0x27b0015 0x27c00 0x1500027d 0x2150002 0x7e151500 0x27f1515 0x28014 0x15000281 0x14150002 0x820d1500 0x2830d15 0x2840c 0x15000285 0xc150002 0x860f1500 0x2870f15 0x2880e 0x15000289 0xe150002 0x8a023900 0x4ff9881 0x4150002 0xc53a1500 0x26e2b15 0x26f37 0x1500023a 0x24150002 0x8d1a1500 0x287ba15 0x2b2d1 0x15000288 0xb150002 0x38011500 0x2390015 0x2b502 0x15000231 0x25150002 0x3b983900 0x4ff9881 0x1150002 0x220a1500 0x2310015 0x2533d 0x15000255 0x3d150002 0x50851500 0x2518015 0x26006 0x15000262 0x20150002 0xa0001500 0x2a12115 0x2a235 0x150002a3 0x19150002 0xa41e1500 0x2a53315 0x2a627 0x150002a7 0x26150002 0xa8af1500 0x2a91b15 0x2aa27 0x150002ab 0x8d150002 0xac1a1500 0x2ad1b15 0x2ae50 0x150002af 0x26150002 0xb02b1500 0x2b15415 0x2b25e 0x150002b3 0x23150002 0xc0001500 0x2c12115 0x2c235 0x150002c3 0x19150002 0xc41e1500 0x2c53315 0x2c627 0x150002c7 0x26150002 0xc8af1500 0x2c91b15 0x2ca27 0x150002cb 0x8d150002 0xcc1a1500 0x2cd1b15 0x2ce50 0x150002cf 0x26150002 0xd02b1500 0x2d15415 0x2d25e 0x150002d3 0x23390004 0xff988100 0x15780111 0x15050129>;
|
panel-exit-sequence = <0x5000128 0x5000110>;
|
phandle = <0x27c>;
|
|
display-timings {
|
native-mode = <0xea>;
|
phandle = <0x27d>;
|
|
timing0 {
|
clock-frequency = <0x41cdb40>;
|
hactive = <0x320>;
|
vactive = <0x500>;
|
hfront-porch = <0x20>;
|
hsync-len = <0x14>;
|
hback-porch = <0x14>;
|
vfront-porch = <0x10>;
|
vsync-len = <0x5>;
|
vback-porch = <0xc>;
|
hsync-active = <0x0>;
|
vsync-active = <0x0>;
|
de-active = <0x0>;
|
pixelclk-active = <0x1>;
|
phandle = <0xea>;
|
};
|
};
|
|
ports {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
port@0 {
|
reg = <0x0>;
|
|
endpoint {
|
remote-endpoint = <0xeb>;
|
phandle = <0xe8>;
|
};
|
};
|
};
|
};
|
};
|
|
dsi@fde30000 {
|
compatible = "rockchip,rk3588-mipi-dsi2";
|
reg = <0x0 0xfde30000 0x0 0x10000>;
|
interrupts = <0x0 0xa8 0x4>;
|
clocks = <0x2 0x279 0x2 0x27b>;
|
clock-names = "pclk", "sys_clk";
|
resets = <0x2 0x355>;
|
reset-names = "apb";
|
power-domains = <0x57 0x18>;
|
phys = <0x30>;
|
phy-names = "dcphy";
|
rockchip,grf = <0xcb>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x27e>;
|
|
ports {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
port@0 {
|
reg = <0x0>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
phandle = <0x27f>;
|
|
endpoint@0 {
|
reg = <0x0>;
|
remote-endpoint = <0xec>;
|
status = "disabled";
|
phandle = <0xde>;
|
};
|
|
endpoint@1 {
|
reg = <0x1>;
|
remote-endpoint = <0x35>;
|
status = "disabled";
|
phandle = <0xe3>;
|
};
|
};
|
|
port@1 {
|
reg = <0x1>;
|
|
endpoint {
|
remote-endpoint = <0xed>;
|
phandle = <0xf1>;
|
};
|
};
|
};
|
|
panel@0 {
|
status = "okay";
|
compatible = "simple-panel-dsi";
|
reg = <0x0>;
|
backlight = <0xee>;
|
reset-delay-ms = <0xa>;
|
enable-delay-ms = <0xa>;
|
prepare-delay-ms = <0xa>;
|
unprepare-delay-ms = <0xa>;
|
disable-delay-ms = <0xa>;
|
dsi,flags = <0xa03>;
|
dsi,format = <0x0>;
|
dsi,lanes = <0x4>;
|
panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 00 01 29];
|
panel-exit-sequence = <0x5000128 0x5000110>;
|
power-supply = <0xef>;
|
phandle = <0x280>;
|
|
display-timings {
|
native-mode = <0xf0>;
|
phandle = <0x281>;
|
|
timing0 {
|
clock-frequency = <0x7de2900>;
|
hactive = <0x438>;
|
vactive = <0x780>;
|
hfront-porch = <0xf>;
|
hsync-len = <0x4>;
|
hback-porch = <0x1e>;
|
vfront-porch = <0xf>;
|
vsync-len = <0x2>;
|
vback-porch = <0xf>;
|
hsync-active = <0x0>;
|
vsync-active = <0x0>;
|
de-active = <0x0>;
|
pixelclk-active = <0x0>;
|
phandle = <0xf0>;
|
};
|
};
|
|
ports {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
port@0 {
|
reg = <0x0>;
|
|
endpoint {
|
remote-endpoint = <0xf1>;
|
phandle = <0xed>;
|
};
|
};
|
};
|
};
|
};
|
|
hdcp@fde40000 {
|
compatible = "rockchip,rk3588-hdcp";
|
reg = <0x0 0xfde40000 0x0 0x80>;
|
interrupts = <0x0 0x9f 0x4>;
|
clocks = <0x2 0x1ed 0x2 0x1ef 0x2 0x1ee 0x2 0x1ec 0x2 0x1f1 0x2 0x1f2>;
|
clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng";
|
resets = <0x2 0x37f 0x2 0x37d 0x2 0x37c 0x2 0x37b 0x2 0x381>;
|
reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng";
|
power-domains = <0x57 0x19>;
|
rockchip,vo-grf = <0xf2>;
|
status = "disabled";
|
phandle = <0x282>;
|
};
|
|
dp@fde50000 {
|
compatible = "rockchip,rk3588-dp";
|
reg = <0x0 0xfde50000 0x0 0x4000>;
|
interrupts = <0x0 0xa1 0x4>;
|
clocks = <0x2 0x1e6 0x2 0x2cc 0x2 0x1fb 0x2 0x207 0x4 0x2 0x1ea>;
|
clock-names = "apb", "aux", "i2s", "spdif", "hclk", "hdcp";
|
assigned-clocks = <0x2 0x2cc>;
|
assigned-clock-rates = <0xf42400>;
|
resets = <0x2 0x388>;
|
phys = <0xf3>;
|
power-domains = <0x57 0x19>;
|
#sound-dai-cells = <0x1>;
|
status = "disabled";
|
phandle = <0x1ce>;
|
|
ports {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
port@0 {
|
reg = <0x0>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
endpoint@0 {
|
reg = <0x0>;
|
remote-endpoint = <0xf4>;
|
status = "disabled";
|
phandle = <0xce>;
|
};
|
|
endpoint@1 {
|
reg = <0x1>;
|
remote-endpoint = <0x33>;
|
status = "disabled";
|
phandle = <0xd4>;
|
};
|
|
endpoint@2 {
|
reg = <0x2>;
|
remote-endpoint = <0xf5>;
|
status = "disabled";
|
phandle = <0xda>;
|
};
|
};
|
|
port@1 {
|
reg = <0x1>;
|
|
endpoint {
|
phandle = <0x283>;
|
};
|
};
|
};
|
};
|
|
hdcp@fde70000 {
|
compatible = "rockchip,rk3588-hdcp";
|
reg = <0x0 0xfde70000 0x0 0x80>;
|
interrupts = <0x0 0xa0 0x4>;
|
clocks = <0x2 0x217 0x2 0x219 0x2 0x218 0x2 0x216 0x2 0x228 0x2 0x229>;
|
clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng";
|
resets = <0x2 0x3c8 0x2 0x3c6 0x2 0x3c5 0x2 0x3c4 0x2 0x3ca>;
|
reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng";
|
power-domains = <0x57 0x1a>;
|
rockchip,vo-grf = <0xcc>;
|
status = "disabled";
|
phandle = <0x284>;
|
};
|
|
hdmi@fde80000 {
|
compatible = "rockchip,rk3588-dw-hdmi";
|
reg = <0x0 0xfde80000 0x0 0x10000 0x0 0xfde90000 0x0 0x10000>;
|
interrupts = <0x0 0xa9 0x4 0x0 0xaa 0x4 0x0 0xab 0x4 0x0 0xac 0x4 0x0 0x168 0x4>;
|
clocks = <0x2 0x221 0x2 0x265 0x2 0x222 0x2 0x223 0x2 0x246 0x2 0x274 0x2 0x275 0x2 0x276 0x2 0x277 0x5 0xf6>;
|
clock-names = "pclk", "hpd", "earc", "hdmitx_ref", "aud", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", "hclk_vo1", "link_clk";
|
resets = <0x2 0x3d0 0x2 0x49c>;
|
reset-names = "ref", "hdp";
|
power-domains = <0x57 0x1a>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0xf7 0xf8 0xf9 0xfa>;
|
reg-io-width = <0x4>;
|
rockchip,grf = <0xbc>;
|
rockchip,vo1_grf = <0xcc>;
|
phys = <0xfb>;
|
phy-names = "hdmi";
|
#sound-dai-cells = <0x0>;
|
status = "okay";
|
enable-gpios = <0xfc 0x9 0x0>;
|
phandle = <0x1ca>;
|
|
ports {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
port@0 {
|
reg = <0x0>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
phandle = <0x285>;
|
|
endpoint@0 {
|
reg = <0x0>;
|
remote-endpoint = <0x38>;
|
status = "okay";
|
phandle = <0xd0>;
|
};
|
|
endpoint@1 {
|
reg = <0x1>;
|
remote-endpoint = <0xfd>;
|
status = "disabled";
|
phandle = <0xd6>;
|
};
|
|
endpoint@2 {
|
reg = <0x2>;
|
remote-endpoint = <0xfe>;
|
status = "disabled";
|
phandle = <0xdc>;
|
};
|
};
|
};
|
};
|
|
edp@fdec0000 {
|
compatible = "rockchip,rk3588-edp";
|
reg = <0x0 0xfdec0000 0x0 0x1000>;
|
interrupts = <0x0 0xa3 0x4>;
|
clocks = <0x2 0x211 0x2 0x210 0x2 0x212 0x5>;
|
clock-names = "dp", "pclk", "spdif", "hclk";
|
resets = <0x2 0x3e1 0x2 0x3e0>;
|
reset-names = "dp", "apb";
|
phys = <0xff>;
|
phy-names = "dp";
|
power-domains = <0x57 0x1a>;
|
rockchip,grf = <0xcc>;
|
status = "disabled";
|
phandle = <0x286>;
|
|
ports {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
port@0 {
|
reg = <0x0>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
endpoint@0 {
|
reg = <0x0>;
|
remote-endpoint = <0x100>;
|
status = "disabled";
|
phandle = <0xcf>;
|
};
|
|
endpoint@1 {
|
reg = <0x1>;
|
remote-endpoint = <0x101>;
|
status = "disabled";
|
phandle = <0xd5>;
|
};
|
|
endpoint@2 {
|
reg = <0x2>;
|
remote-endpoint = <0x36>;
|
status = "disabled";
|
phandle = <0xdb>;
|
};
|
};
|
|
port@1 {
|
reg = <0x1>;
|
|
endpoint {
|
phandle = <0x287>;
|
};
|
};
|
};
|
};
|
|
qos@fdf35000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf35000 0x0 0x20>;
|
phandle = <0x7a>;
|
};
|
|
qos@fdf35200 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf35200 0x0 0x20>;
|
phandle = <0x7b>;
|
};
|
|
qos@fdf35400 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf35400 0x0 0x20>;
|
phandle = <0x7c>;
|
};
|
|
qos@fdf35600 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf35600 0x0 0x20>;
|
phandle = <0x7d>;
|
};
|
|
qos@fdf36000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf36000 0x0 0x20>;
|
phandle = <0x9d>;
|
};
|
|
qos@fdf39000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf39000 0x0 0x20>;
|
phandle = <0xa2>;
|
};
|
|
qos@fdf3d800 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf3d800 0x0 0x20>;
|
phandle = <0xa3>;
|
};
|
|
qos@fdf3e000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf3e000 0x0 0x20>;
|
phandle = <0x9f>;
|
};
|
|
qos@fdf3e200 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf3e200 0x0 0x20>;
|
phandle = <0x9e>;
|
};
|
|
qos@fdf3e400 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf3e400 0x0 0x20>;
|
phandle = <0xa0>;
|
};
|
|
qos@fdf3e600 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf3e600 0x0 0x20>;
|
phandle = <0xa1>;
|
};
|
|
qos@fdf40000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf40000 0x0 0x20>;
|
phandle = <0x9b>;
|
};
|
|
qos@fdf40200 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf40200 0x0 0x20>;
|
phandle = <0x9c>;
|
};
|
|
qos@fdf40400 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf40400 0x0 0x20>;
|
phandle = <0x95>;
|
};
|
|
qos@fdf40500 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf40500 0x0 0x20>;
|
phandle = <0x96>;
|
};
|
|
qos@fdf40600 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf40600 0x0 0x20>;
|
phandle = <0x97>;
|
};
|
|
qos@fdf40800 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf40800 0x0 0x20>;
|
phandle = <0x98>;
|
};
|
|
qos@fdf41000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf41000 0x0 0x20>;
|
phandle = <0x99>;
|
};
|
|
qos@fdf41100 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf41100 0x0 0x20>;
|
phandle = <0x9a>;
|
};
|
|
qos@fdf60000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf60000 0x0 0x20>;
|
phandle = <0x80>;
|
};
|
|
qos@fdf60200 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf60200 0x0 0x20>;
|
phandle = <0x81>;
|
};
|
|
qos@fdf60400 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf60400 0x0 0x20>;
|
phandle = <0x82>;
|
};
|
|
qos@fdf61000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf61000 0x0 0x20>;
|
phandle = <0x83>;
|
};
|
|
qos@fdf61200 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf61200 0x0 0x20>;
|
phandle = <0x84>;
|
};
|
|
qos@fdf61400 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf61400 0x0 0x20>;
|
phandle = <0x85>;
|
};
|
|
qos@fdf62000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf62000 0x0 0x20>;
|
phandle = <0x7e>;
|
};
|
|
qos@fdf63000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf63000 0x0 0x20>;
|
phandle = <0x7f>;
|
};
|
|
qos@fdf64000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf64000 0x0 0x20>;
|
phandle = <0x8e>;
|
};
|
|
qos@fdf66000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf66000 0x0 0x20>;
|
phandle = <0x86>;
|
};
|
|
qos@fdf66200 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf66200 0x0 0x20>;
|
phandle = <0x87>;
|
};
|
|
qos@fdf66400 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf66400 0x0 0x20>;
|
phandle = <0x88>;
|
};
|
|
qos@fdf66600 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf66600 0x0 0x20>;
|
phandle = <0x89>;
|
};
|
|
qos@fdf66800 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf66800 0x0 0x20>;
|
phandle = <0x8a>;
|
};
|
|
qos@fdf66a00 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf66a00 0x0 0x20>;
|
phandle = <0x8b>;
|
};
|
|
qos@fdf66c00 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf66c00 0x0 0x20>;
|
phandle = <0x8c>;
|
};
|
|
qos@fdf66e00 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf66e00 0x0 0x20>;
|
phandle = <0x8d>;
|
};
|
|
qos@fdf67000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf67000 0x0 0x20>;
|
phandle = <0x8f>;
|
};
|
|
qos@fdf67200 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf67200 0x0 0x20>;
|
phandle = <0x288>;
|
};
|
|
qos@fdf70000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf70000 0x0 0x20>;
|
phandle = <0x78>;
|
};
|
|
qos@fdf71000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf71000 0x0 0x20>;
|
phandle = <0x79>;
|
};
|
|
qos@fdf72000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf72000 0x0 0x20>;
|
phandle = <0x75>;
|
};
|
|
qos@fdf72200 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf72200 0x0 0x20>;
|
phandle = <0x76>;
|
};
|
|
qos@fdf72400 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf72400 0x0 0x20>;
|
phandle = <0x77>;
|
};
|
|
qos@fdf80000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf80000 0x0 0x20>;
|
phandle = <0x92>;
|
};
|
|
qos@fdf81000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf81000 0x0 0x20>;
|
phandle = <0x93>;
|
};
|
|
qos@fdf81200 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf81200 0x0 0x20>;
|
phandle = <0x94>;
|
};
|
|
qos@fdf82000 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf82000 0x0 0x20>;
|
phandle = <0x90>;
|
};
|
|
qos@fdf82200 {
|
compatible = "syscon";
|
reg = <0x0 0xfdf82200 0x0 0x20>;
|
phandle = <0x91>;
|
};
|
|
dfi@fe060000 {
|
compatible = "rockchip,rk3588-dfi";
|
reg = <0x0 0xfe060000 0x0 0x10000>;
|
rockchip,pmu_grf = <0x102>;
|
status = "okay";
|
phandle = <0x3c>;
|
};
|
|
pcie@fe180000 {
|
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
|
#address-cells = <0x3>;
|
#size-cells = <0x2>;
|
bus-range = <0x30 0x3f>;
|
clocks = <0x2 0x151 0x2 0x156 0x2 0x14c 0x2 0x15c 0x2 0x161 0x2 0x2c5>;
|
clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux", "pipe";
|
device_type = "pci";
|
interrupts = <0x0 0xf8 0x4 0x0 0xf7 0x4 0x0 0xf6 0x4 0x0 0xf5 0x4 0x0 0xf4 0x4>;
|
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
#interrupt-cells = <0x1>;
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
interrupt-map = <0x0 0x0 0x0 0x1 0x103 0x0 0x0 0x0 0x0 0x2 0x103 0x1 0x0 0x0 0x0 0x3 0x103 0x2 0x0 0x0 0x0 0x4 0x103 0x3>;
|
linux,pci-domain = <0x3>;
|
num-ib-windows = <0x8>;
|
num-ob-windows = <0x8>;
|
num-viewport = <0x4>;
|
max-link-speed = <0x2>;
|
msi-map = <0x3000 0x104 0x3000 0x1000>;
|
num-lanes = <0x1>;
|
phys = <0x66 0x2>;
|
phy-names = "pcie-phy";
|
ranges = <0x800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000 0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000 0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000 0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
|
reg = <0x0 0xfe180000 0x0 0x10000 0xa 0x40c00000 0x0 0x400000>;
|
reg-names = "pcie-apb", "pcie-dbi";
|
resets = <0x2 0x210 0x2 0x21f>;
|
reset-names = "pcie", "periph";
|
rockchip,pipe-grf = <0x6c>;
|
status = "okay";
|
reset-gpios = <0xfc 0x2 0x0>;
|
vpcie3v3-supply = <0x105>;
|
phandle = <0x289>;
|
|
legacy-interrupt-controller {
|
interrupt-controller;
|
#address-cells = <0x0>;
|
#interrupt-cells = <0x1>;
|
interrupt-parent = <0x1>;
|
interrupts = <0x0 0xf5 0x1>;
|
phandle = <0x103>;
|
};
|
};
|
|
pcie@fe190000 {
|
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
|
#address-cells = <0x3>;
|
#size-cells = <0x2>;
|
bus-range = <0x40 0x4f>;
|
clocks = <0x2 0x152 0x2 0x157 0x2 0x14d 0x2 0x15d 0x2 0x162 0x2 0x182>;
|
clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux", "pipe";
|
device_type = "pci";
|
interrupts = <0x0 0xfd 0x4 0x0 0xfc 0x4 0x0 0xfb 0x4 0x0 0xfa 0x4 0x0 0xf9 0x4>;
|
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
#interrupt-cells = <0x1>;
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
interrupt-map = <0x0 0x0 0x0 0x1 0x106 0x0 0x0 0x0 0x0 0x2 0x106 0x1 0x0 0x0 0x0 0x3 0x106 0x2 0x0 0x0 0x0 0x4 0x106 0x3>;
|
linux,pci-domain = <0x4>;
|
num-ib-windows = <0x8>;
|
num-ob-windows = <0x8>;
|
num-viewport = <0x4>;
|
max-link-speed = <0x2>;
|
msi-map = <0x4000 0x104 0x4000 0x1000>;
|
num-lanes = <0x1>;
|
phys = <0x107 0x2>;
|
phy-names = "pcie-phy";
|
ranges = <0x800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000 0xc3000000 0xa 0x0 0xa 0x0 0x0 0x40000000>;
|
reg = <0x0 0xfe190000 0x0 0x10000 0xa 0x41000000 0x0 0x400000>;
|
reg-names = "pcie-apb", "pcie-dbi";
|
resets = <0x2 0x211 0x2 0x220>;
|
reset-names = "pcie", "periph";
|
rockchip,pipe-grf = <0x6c>;
|
status = "disabled";
|
reset-gpios = <0x108 0x18 0x0>;
|
vpcie3v3-supply = <0x105>;
|
phandle = <0x28a>;
|
|
legacy-interrupt-controller {
|
interrupt-controller;
|
#address-cells = <0x0>;
|
#interrupt-cells = <0x1>;
|
interrupt-parent = <0x1>;
|
interrupts = <0x0 0xfa 0x1>;
|
phandle = <0x106>;
|
};
|
};
|
|
uio@fe1c0000 {
|
compatible = "rockchip,uio-gmac";
|
reg = <0x0 0xfe1c0000 0x0 0x10000>;
|
rockchip,ethernet = <0x109>;
|
status = "disabled";
|
phandle = <0x28b>;
|
};
|
|
ethernet@fe1c0000 {
|
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
reg = <0x0 0xfe1c0000 0x0 0x10000>;
|
interrupts = <0x0 0xea 0x4 0x0 0xe9 0x4>;
|
interrupt-names = "macirq", "eth_wake_irq";
|
rockchip,grf = <0xbc>;
|
rockchip,php_grf = <0x6c>;
|
clocks = <0x2 0x144 0x2 0x145 0x2 0x168 0x2 0x16d 0x2 0x143>;
|
clock-names = "stmmaceth", "clk_mac_ref", "pclk_mac", "aclk_mac", "ptp_ref";
|
resets = <0x2 0x20b>;
|
reset-names = "stmmaceth";
|
power-domains = <0x57 0x21>;
|
snps,mixed-burst;
|
snps,tso;
|
snps,axi-config = <0x10a>;
|
snps,mtl-rx-config = <0x10b>;
|
snps,mtl-tx-config = <0x10c>;
|
status = "okay";
|
phy-mode = "rgmii-rxid";
|
clock_in_out = "output";
|
snps,reset-gpio = <0x108 0xf 0x1>;
|
snps,reset-active-low;
|
snps,reset-delays-us = <0x0 0x4e20 0x186a0>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x10d 0x10e 0x10f 0x110 0x111>;
|
tx_delay = <0x43>;
|
phy-handle = <0x112>;
|
phandle = <0x109>;
|
|
mdio {
|
compatible = "snps,dwmac-mdio";
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
phandle = <0x28c>;
|
|
phy@1 {
|
compatible = "ethernet-phy-ieee802.3-c22";
|
reg = <0x1>;
|
phandle = <0x112>;
|
};
|
};
|
|
stmmac-axi-config {
|
snps,wr_osr_lmt = <0x4>;
|
snps,rd_osr_lmt = <0x8>;
|
snps,blen = <0x0 0x0 0x0 0x0 0x10 0x8 0x4>;
|
phandle = <0x10a>;
|
};
|
|
rx-queues-config {
|
snps,rx-queues-to-use = <0x1>;
|
phandle = <0x10b>;
|
|
queue0 {
|
};
|
};
|
|
tx-queues-config {
|
snps,tx-queues-to-use = <0x1>;
|
phandle = <0x10c>;
|
|
queue0 {
|
};
|
};
|
};
|
|
sata@fe210000 {
|
compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
|
reg = <0x0 0xfe210000 0x0 0x1000>;
|
clocks = <0x2 0x171 0x2 0x16e 0x2 0x174 0x2 0x163 0x2 0x17e>;
|
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
interrupts = <0x0 0x111 0x4>;
|
interrupt-names = "hostc";
|
phys = <0x107 0x1>;
|
phy-names = "sata-phy";
|
ports-implemented = <0x1>;
|
status = "okay";
|
phandle = <0x28d>;
|
};
|
|
sata@fe230000 {
|
compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
|
reg = <0x0 0xfe230000 0x0 0x1000>;
|
clocks = <0x2 0x173 0x2 0x170 0x2 0x176 0x2 0x165 0x2 0x180>;
|
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
interrupts = <0x0 0x113 0x4>;
|
interrupt-names = "hostc";
|
phys = <0x66 0x1>;
|
phy-names = "sata-phy";
|
ports-implemented = <0x1>;
|
status = "okay";
|
phandle = <0x28e>;
|
};
|
|
spi@fe2b0000 {
|
compatible = "rockchip,sfc";
|
reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
interrupts = <0x0 0xce 0x4>;
|
clocks = <0x2 0x13d 0x2 0x13e>;
|
clock-names = "clk_sfc", "hclk_sfc";
|
assigned-clocks = <0x2 0x13d>;
|
assigned-clock-rates = <0x5f5e100>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x28f>;
|
};
|
|
mmc@fe2c0000 {
|
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
|
reg = <0x0 0xfe2c0000 0x0 0x4000>;
|
interrupts = <0x0 0xcb 0x4>;
|
clocks = <0xe 0x17 0xe 0x9 0x2 0x2c2 0x2 0x2c3>;
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
fifo-depth = <0x100>;
|
max-frequency = <0x8f0d180>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x113 0x114 0x115 0x116>;
|
power-domains = <0x57 0x28>;
|
status = "okay";
|
no-sdio;
|
no-mmc;
|
bus-width = <0x4>;
|
cap-mmc-highspeed;
|
cap-sd-highspeed;
|
disable-wp;
|
sd-uhs-sdr104;
|
vqmmc-supply = <0x117>;
|
vmmc-supply = <0x118>;
|
phandle = <0x290>;
|
};
|
|
mmc@fe2d0000 {
|
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
|
reg = <0x0 0xfe2d0000 0x0 0x4000>;
|
interrupts = <0x0 0xcc 0x4>;
|
clocks = <0x2 0x199 0x2 0x19a 0x2 0x2c0 0x2 0x2c1>;
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
fifo-depth = <0x100>;
|
max-frequency = <0x8f0d180>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x119>;
|
power-domains = <0x57 0x25>;
|
status = "okay";
|
no-sd;
|
no-mmc;
|
bus-width = <0x4>;
|
disable-wp;
|
cap-sd-highspeed;
|
cap-sdio-irq;
|
keep-power-in-suspend;
|
mmc-pwrseq = <0x11a>;
|
non-removable;
|
sd-uhs-sdr104;
|
phandle = <0x291>;
|
};
|
|
mmc@fe2e0000 {
|
compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci";
|
reg = <0x0 0xfe2e0000 0x0 0x10000>;
|
interrupts = <0x0 0xcd 0x4>;
|
assigned-clocks = <0x2 0x13b 0x2 0x13c 0x2 0x13a>;
|
assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>;
|
clocks = <0x2 0x13a 0x2 0x138 0x2 0x139 0x2 0x13b 0x2 0x13c>;
|
clock-names = "core", "bus", "axi", "block", "timer";
|
resets = <0x2 0x1f6 0x2 0x1f4 0x2 0x1f5 0x2 0x1f7 0x2 0x1f8>;
|
reset-names = "core", "bus", "axi", "block", "timer";
|
max-frequency = <0xbebc200>;
|
status = "okay";
|
bus-width = <0x8>;
|
no-sdio;
|
no-sd;
|
non-removable;
|
mmc-hs400-1_8v;
|
mmc-hs400-enhanced-strobe;
|
full-pwr-cycle-in-suspend;
|
phandle = <0x292>;
|
};
|
|
crypto@fe370000 {
|
compatible = "rockchip,rk3588-crypto";
|
reg = <0x0 0xfe370000 0x0 0x2000>;
|
interrupts = <0x0 0xd1 0x4>;
|
clocks = <0xe 0xb 0xe 0xc 0xe 0x14 0xe 0x15>;
|
clock-names = "aclk", "hclk", "sclk", "pka";
|
resets = <0x11b 0xf>;
|
reset-names = "crypto-rst";
|
status = "disabled";
|
phandle = <0x293>;
|
};
|
|
rng@fe378000 {
|
compatible = "rockchip,trngv1";
|
reg = <0x0 0xfe378000 0x0 0x200>;
|
interrupts = <0x0 0x190 0x4>;
|
clocks = <0xe 0xc>;
|
clock-names = "hclk_trng";
|
resets = <0x11b 0x30>;
|
reset-names = "reset";
|
status = "okay";
|
phandle = <0x294>;
|
};
|
|
i2s@fe470000 {
|
compatible = "rockchip,rk3588-i2s-tdm";
|
reg = <0x0 0xfe470000 0x0 0x1000>;
|
interrupts = <0x0 0xb4 0x4>;
|
clocks = <0x2 0x33 0x2 0x37 0x2 0x30>;
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
assigned-clocks = <0x2 0x31 0x2 0x35>;
|
assigned-clock-parents = <0x2 0x5 0x2 0x5>;
|
dmas = <0x6f 0x0 0x6f 0x1>;
|
dma-names = "tx", "rx";
|
power-domains = <0x57 0x26>;
|
resets = <0x2 0x77 0x2 0x7a>;
|
reset-names = "tx-m", "rx-m";
|
rockchip,clk-trcm = <0x1>;
|
pinctrl-names = "default", "idle", "clk";
|
pinctrl-0 = <0x11c 0x11d 0x11e 0x11f>;
|
pinctrl-1 = <0x120>;
|
pinctrl-2 = <0x11c 0x11d>;
|
#sound-dai-cells = <0x0>;
|
status = "okay";
|
phandle = <0x1d7>;
|
};
|
|
i2s@fe480000 {
|
compatible = "rockchip,rk3588-i2s-tdm";
|
reg = <0x0 0xfe480000 0x0 0x1000>;
|
interrupts = <0x0 0xb5 0x4>;
|
clocks = <0x2 0x28c 0x2 0x290 0x2 0x288>;
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
dmas = <0x6f 0x2 0x6f 0x3>;
|
dma-names = "tx", "rx";
|
resets = <0x2 0xc002a 0x2 0xc002d>;
|
reset-names = "tx-m", "rx-m";
|
rockchip,clk-trcm = <0x1>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x121 0x122 0x123 0x124 0x125 0x126 0x127 0x128 0x129 0x12a>;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x295>;
|
};
|
|
i2s@fe490000 {
|
compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
|
reg = <0x0 0xfe490000 0x0 0x1000>;
|
interrupts = <0x0 0xb6 0x4>;
|
clocks = <0x2 0x27 0x2 0x22>;
|
clock-names = "i2s_clk", "i2s_hclk";
|
assigned-clocks = <0x2 0x24>;
|
assigned-clock-parents = <0x2 0x5>;
|
dmas = <0xe5 0x0 0xe5 0x1>;
|
dma-names = "tx", "rx";
|
power-domains = <0x57 0x26>;
|
rockchip,clk-trcm = <0x1>;
|
pinctrl-names = "default", "idle", "clk";
|
pinctrl-0 = <0x12b 0x12c 0x12d 0x12e>;
|
pinctrl-1 = <0x12f>;
|
pinctrl-2 = <0x130 0x131>;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
rockchip,bclk-fs = <0x20>;
|
phandle = <0x1c7>;
|
};
|
|
i2s@fe4a0000 {
|
compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
|
reg = <0x0 0xfe4a0000 0x0 0x1000>;
|
interrupts = <0x0 0xb7 0x4>;
|
clocks = <0x2 0x2d 0x2 0x23>;
|
clock-names = "i2s_clk", "i2s_hclk";
|
assigned-clocks = <0x2 0x2a>;
|
assigned-clock-parents = <0x2 0x5>;
|
dmas = <0xe5 0x2 0xe5 0x3>;
|
dma-names = "tx", "rx";
|
power-domains = <0x57 0x26>;
|
rockchip,clk-trcm = <0x1>;
|
pinctrl-names = "default", "idle", "clk";
|
pinctrl-0 = <0x132 0x133>;
|
pinctrl-1 = <0x134>;
|
pinctrl-2 = <0x135 0x136>;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x296>;
|
};
|
|
pdm@fe4b0000 {
|
compatible = "rockchip,rk3588-pdm";
|
reg = <0x0 0xfe4b0000 0x0 0x1000>;
|
clocks = <0x2 0x29f 0x2 0x29e>;
|
clock-names = "pdm_clk", "pdm_hclk";
|
dmas = <0x6f 0x4>;
|
dma-names = "rx";
|
pinctrl-names = "default", "idle", "clk";
|
pinctrl-0 = <0x137 0x138 0x139 0x13a>;
|
pinctrl-1 = <0x13b>;
|
pinctrl-2 = <0x13c 0x13d>;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x297>;
|
};
|
|
pdm@fe4c0000 {
|
compatible = "rockchip,rk3588-pdm";
|
reg = <0x0 0xfe4c0000 0x0 0x1000>;
|
clocks = <0x2 0x3b 0x2 0x3a>;
|
clock-names = "pdm_clk", "pdm_hclk";
|
assigned-clocks = <0x2 0x3b>;
|
assigned-clock-parents = <0x2 0x5>;
|
dmas = <0xe5 0x4>;
|
dma-names = "rx";
|
power-domains = <0x57 0x26>;
|
pinctrl-names = "default", "idle", "clk";
|
pinctrl-0 = <0x13e 0x13f 0x140 0x141>;
|
pinctrl-1 = <0x142>;
|
pinctrl-2 = <0x143 0x144>;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x298>;
|
};
|
|
vad@fe4d0000 {
|
compatible = "rockchip,rk3588-vad";
|
reg = <0x0 0xfe4d0000 0x0 0x1000>;
|
reg-names = "vad";
|
clocks = <0x2 0x2a0>;
|
clock-names = "hclk";
|
interrupts = <0x0 0xca 0x4>;
|
rockchip,audio-src = <0x0>;
|
rockchip,det-channel = <0x0>;
|
rockchip,mode = <0x0>;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x299>;
|
};
|
|
spdif-tx@fe4e0000 {
|
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
|
reg = <0x0 0xfe4e0000 0x0 0x1000>;
|
interrupts = <0x0 0xc1 0x4>;
|
dmas = <0x6f 0x5>;
|
dma-names = "tx";
|
clock-names = "mclk", "hclk";
|
clocks = <0x2 0x41 0x2 0x3e>;
|
assigned-clocks = <0x2 0x3f>;
|
assigned-clock-parents = <0x2 0x5>;
|
power-domains = <0x57 0x26>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x145>;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x1d1>;
|
};
|
|
spdif-tx@fe4f0000 {
|
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
|
reg = <0x0 0xfe4f0000 0x0 0x1000>;
|
interrupts = <0x0 0xc2 0x4>;
|
dmas = <0xe5 0x5>;
|
dma-names = "tx";
|
clock-names = "mclk", "hclk";
|
clocks = <0x2 0x47 0x2 0x44>;
|
assigned-clocks = <0x2 0x45>;
|
assigned-clock-parents = <0x2 0x5>;
|
power-domains = <0x57 0x26>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x146>;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x1d3>;
|
};
|
|
codec-digital@fe500000 {
|
compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1";
|
reg = <0x0 0xfe500000 0x0 0x1000>;
|
clocks = <0x2 0x29 0x2 0x2f>;
|
clock-names = "dac", "pclk";
|
power-domains = <0x57 0x26>;
|
resets = <0x2 0x84>;
|
reset-names = "reset";
|
rockchip,grf = <0xbc>;
|
rockchip,pwm-output-mode;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x147>;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x29a>;
|
};
|
|
hwspinlock@fe5a0000 {
|
compatible = "rockchip,hwspinlock";
|
reg = <0x0 0xfe5a0000 0x0 0x100>;
|
#hwlock-cells = <0x1>;
|
phandle = <0x29b>;
|
};
|
|
interrupt-controller@fe600000 {
|
compatible = "arm,gic-v3";
|
#interrupt-cells = <0x3>;
|
#address-cells = <0x2>;
|
#size-cells = <0x2>;
|
ranges;
|
interrupt-controller;
|
reg = <0x0 0xfe600000 0x0 0x10000 0x0 0xfe680000 0x0 0x100000>;
|
interrupts = <0x1 0x9 0x4>;
|
phandle = <0x1>;
|
|
msi-controller@fe640000 {
|
compatible = "arm,gic-v3-its";
|
msi-controller;
|
#msi-cells = <0x1>;
|
reg = <0x0 0xfe640000 0x0 0x20000>;
|
phandle = <0x104>;
|
};
|
|
msi-controller@fe660000 {
|
compatible = "arm,gic-v3-its";
|
msi-controller;
|
#msi-cells = <0x1>;
|
reg = <0x0 0xfe660000 0x0 0x20000>;
|
phandle = <0x1b4>;
|
};
|
};
|
|
dma-controller@fea10000 {
|
compatible = "arm,pl330", "arm,primecell";
|
reg = <0x0 0xfea10000 0x0 0x4000>;
|
interrupts = <0x0 0x56 0x4 0x0 0x57 0x4>;
|
clocks = <0x2 0x78>;
|
clock-names = "apb_pclk";
|
#dma-cells = <0x1>;
|
arm,pl330-periph-burst;
|
phandle = <0x6f>;
|
};
|
|
dma-controller@fea30000 {
|
compatible = "arm,pl330", "arm,primecell";
|
reg = <0x0 0xfea30000 0x0 0x4000>;
|
interrupts = <0x0 0x58 0x4 0x0 0x59 0x4>;
|
clocks = <0x2 0x79>;
|
clock-names = "apb_pclk";
|
#dma-cells = <0x1>;
|
arm,pl330-periph-burst;
|
phandle = <0xe5>;
|
};
|
|
can@fea50000 {
|
compatible = "rockchip,can-2.0";
|
reg = <0x0 0xfea50000 0x0 0x1000>;
|
interrupts = <0x0 0x155 0x4>;
|
clocks = <0x2 0x70 0x2 0x6f>;
|
clock-names = "baudclk", "apb_pclk";
|
resets = <0x2 0xb9 0x2 0xb8>;
|
reset-names = "can", "can-apb";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x148>;
|
tx-fifo-depth = <0x1>;
|
rx-fifo-depth = <0x6>;
|
status = "okay";
|
phandle = <0x29c>;
|
};
|
|
can@fea60000 {
|
compatible = "rockchip,can-2.0";
|
reg = <0x0 0xfea60000 0x0 0x1000>;
|
interrupts = <0x0 0x156 0x4>;
|
clocks = <0x2 0x72 0x2 0x71>;
|
clock-names = "baudclk", "apb_pclk";
|
resets = <0x2 0xbb 0x2 0xba>;
|
reset-names = "can", "can-apb";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x149>;
|
tx-fifo-depth = <0x1>;
|
rx-fifo-depth = <0x6>;
|
status = "okay";
|
phandle = <0x29d>;
|
};
|
|
can@fea70000 {
|
compatible = "rockchip,can-2.0";
|
reg = <0x0 0xfea70000 0x0 0x1000>;
|
interrupts = <0x0 0x157 0x4>;
|
clocks = <0x2 0x74 0x2 0x73>;
|
clock-names = "baudclk", "apb_pclk";
|
resets = <0x2 0xbd 0x2 0xbc>;
|
reset-names = "can", "can-apb";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x14a>;
|
tx-fifo-depth = <0x1>;
|
rx-fifo-depth = <0x6>;
|
status = "disabled";
|
phandle = <0x29e>;
|
};
|
|
decompress@fea80000 {
|
compatible = "rockchip,hw-decompress";
|
reg = <0x0 0xfea80000 0x0 0x1000>;
|
interrupts = <0x0 0x55 0x4>;
|
clocks = <0x2 0x75 0x2 0x77 0x2 0x76>;
|
clock-names = "aclk", "dclk", "pclk";
|
resets = <0x2 0x118>;
|
reset-names = "dresetn";
|
status = "disabled";
|
phandle = <0x29f>;
|
};
|
|
i2c@fea90000 {
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
reg = <0x0 0xfea90000 0x0 0x1000>;
|
clocks = <0x2 0x8d 0x2 0x85>;
|
clock-names = "i2c", "pclk";
|
interrupts = <0x0 0x13e 0x4>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x14b>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
status = "okay";
|
phandle = <0x2a0>;
|
|
rk8602@42 {
|
compatible = "rockchip,rk8602";
|
reg = <0x42>;
|
vin-supply = <0x6e>;
|
regulator-compatible = "rk860x-reg";
|
regulator-name = "vdd_npu_s0";
|
regulator-min-microvolt = <0x86470>;
|
regulator-max-microvolt = <0xe7ef0>;
|
regulator-ramp-delay = <0x8fc>;
|
rockchip,suspend-voltage-selector = <0x1>;
|
regulator-boot-on;
|
regulator-always-on;
|
phandle = <0xa6>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
};
|
|
i2c@feaa0000 {
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
reg = <0x0 0xfeaa0000 0x0 0x1000>;
|
clocks = <0x2 0x8e 0x2 0x86>;
|
clock-names = "i2c", "pclk";
|
interrupts = <0x0 0x13f 0x4>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x14c>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x2a1>;
|
};
|
|
i2c@feab0000 {
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
reg = <0x0 0xfeab0000 0x0 0x1000>;
|
clocks = <0x2 0x8f 0x2 0x87>;
|
clock-names = "i2c", "pclk";
|
interrupts = <0x0 0x140 0x4>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x14d>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
status = "okay";
|
phandle = <0x2a2>;
|
|
es8316@10 {
|
compatible = "everest,es8316";
|
reg = <0x10>;
|
clocks = <0x14e>;
|
clock-names = "mclk";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x14f>;
|
#sound-dai-cells = <0x0>;
|
phandle = <0x1d8>;
|
};
|
};
|
|
i2c@feac0000 {
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
reg = <0x0 0xfeac0000 0x0 0x1000>;
|
clocks = <0x2 0x90 0x2 0x88>;
|
clock-names = "i2c", "pclk";
|
interrupts = <0x0 0x141 0x4>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x150>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x2a3>;
|
|
light@47 {
|
compatible = "ls_stk3332";
|
status = "disabled";
|
reg = <0x47>;
|
type = <0x5>;
|
irq_enable = <0x0>;
|
als_threshold_high = <0x64>;
|
als_threshold_low = <0xa>;
|
als_ctrl_gain = <0x2>;
|
poll_delay_ms = <0x64>;
|
phandle = <0x2a4>;
|
};
|
|
proximity@47 {
|
compatible = "ps_stk3332";
|
status = "disabled";
|
reg = <0x47>;
|
type = <0x6>;
|
ps_threshold_high = <0x200>;
|
ps_threshold_low = <0x100>;
|
ps_ctrl_gain = <0x3>;
|
ps_led_current = <0x4>;
|
poll_delay_ms = <0x64>;
|
phandle = <0x2a5>;
|
};
|
|
icm_acc@68 {
|
status = "okay";
|
compatible = "icm42607_acc";
|
reg = <0x68>;
|
irq-gpio = <0xfc 0x12 0x1>;
|
irq_enable = <0x0>;
|
poll_delay_ms = <0x1e>;
|
type = <0x2>;
|
layout = <0x0>;
|
phandle = <0x2a6>;
|
};
|
|
icm_gyro@68 {
|
status = "okay";
|
compatible = "icm42607_gyro";
|
reg = <0x68>;
|
poll_delay_ms = <0x1e>;
|
type = <0x4>;
|
layout = <0x0>;
|
phandle = <0x2a7>;
|
};
|
};
|
|
i2c@fead0000 {
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
reg = <0x0 0xfead0000 0x0 0x1000>;
|
clocks = <0x2 0x91 0x2 0x89>;
|
clock-names = "i2c", "pclk";
|
interrupts = <0x0 0x142 0x4>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x151>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x2a8>;
|
|
gt1x@14 {
|
compatible = "goodix,gt1x";
|
reg = <0x14>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x152>;
|
goodix,rst-gpio = <0x108 0x11 0x0>;
|
goodix,irq-gpio = <0x108 0x10 0x8>;
|
power-supply = <0xef>;
|
phandle = <0x2a9>;
|
};
|
};
|
|
timer@feae0000 {
|
compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
|
reg = <0x0 0xfeae0000 0x0 0x20>;
|
interrupts = <0x0 0x121 0x4>;
|
clocks = <0x2 0x5c 0x2 0x5f>;
|
clock-names = "pclk", "timer";
|
phandle = <0x2aa>;
|
};
|
|
watchdog@feaf0000 {
|
compatible = "snps,dw-wdt";
|
reg = <0x0 0xfeaf0000 0x0 0x100>;
|
clocks = <0x2 0x6c 0x2 0x6b>;
|
clock-names = "tclk", "pclk";
|
interrupts = <0x0 0x13b 0x4>;
|
status = "disabled";
|
phandle = <0x2ab>;
|
};
|
|
spi@feb00000 {
|
compatible = "rockchip,rk3066-spi";
|
reg = <0x0 0xfeb00000 0x0 0x1000>;
|
interrupts = <0x0 0x146 0x4>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
clocks = <0x2 0xa3 0x2 0x9e>;
|
clock-names = "spiclk", "apb_pclk";
|
dmas = <0x6f 0xe 0x6f 0xf>;
|
dma-names = "tx", "rx";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x153 0x154 0x155>;
|
num-cs = <0x2>;
|
status = "disabled";
|
phandle = <0x2ac>;
|
};
|
|
spi@feb10000 {
|
compatible = "rockchip,rk3066-spi";
|
reg = <0x0 0xfeb10000 0x0 0x1000>;
|
interrupts = <0x0 0x147 0x4>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
clocks = <0x2 0xa4 0x2 0x9f>;
|
clock-names = "spiclk", "apb_pclk";
|
dmas = <0x6f 0x10 0x6f 0x11>;
|
dma-names = "tx", "rx";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x156 0x157 0x158>;
|
num-cs = <0x2>;
|
status = "disabled";
|
phandle = <0x2ad>;
|
};
|
|
spi@feb20000 {
|
compatible = "rockchip,rk3066-spi";
|
reg = <0x0 0xfeb20000 0x0 0x1000>;
|
interrupts = <0x0 0x148 0x4>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
clocks = <0x2 0xa5 0x2 0xa0>;
|
clock-names = "spiclk", "apb_pclk";
|
dmas = <0xe5 0xf 0xe5 0x10>;
|
dma-names = "tx", "rx";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x159 0x15a>;
|
num-cs = <0x1>;
|
status = "okay";
|
assigned-clocks = <0x2 0xa5>;
|
assigned-clock-rates = <0xbebc200>;
|
phandle = <0x2ae>;
|
|
rk806single@0 {
|
compatible = "rockchip,rk806";
|
spi-max-frequency = <0xf4240>;
|
reg = <0x0>;
|
interrupt-parent = <0x15b>;
|
interrupts = <0x7 0x8>;
|
pinctrl-names = "default", "pmic-power-off";
|
pinctrl-0 = <0x15c 0x15d 0x15e 0x15f>;
|
pinctrl-1 = <0x160>;
|
low_voltage_threshold = <0xbb8>;
|
shutdown_voltage_threshold = <0xa8c>;
|
shutdown_temperture_threshold = <0xa0>;
|
hotdie_temperture_threshold = <0x73>;
|
pmic-reset-func = <0x1>;
|
vcc1-supply = <0x6e>;
|
vcc2-supply = <0x6e>;
|
vcc3-supply = <0x6e>;
|
vcc4-supply = <0x6e>;
|
vcc5-supply = <0x6e>;
|
vcc6-supply = <0x6e>;
|
vcc7-supply = <0x6e>;
|
vcc8-supply = <0x6e>;
|
vcc9-supply = <0x6e>;
|
vcc10-supply = <0x6e>;
|
vcc11-supply = <0x161>;
|
vcc12-supply = <0x6e>;
|
vcc13-supply = <0x162>;
|
vcc14-supply = <0x162>;
|
vcca-supply = <0x6e>;
|
phandle = <0x2af>;
|
|
pwrkey {
|
status = "okay";
|
};
|
|
pinctrl_rk806 {
|
gpio-controller;
|
#gpio-cells = <0x2>;
|
phandle = <0x2b0>;
|
|
rk806_dvs1_null {
|
pins = "gpio_pwrctrl2";
|
function = "pin_fun0";
|
phandle = <0x15d>;
|
};
|
|
rk806_dvs1_slp {
|
pins = "gpio_pwrctrl1";
|
function = "pin_fun1";
|
phandle = <0x2b1>;
|
};
|
|
rk806_dvs1_pwrdn {
|
pins = "gpio_pwrctrl1";
|
function = "pin_fun2";
|
phandle = <0x160>;
|
};
|
|
rk806_dvs1_rst {
|
pins = "gpio_pwrctrl1";
|
function = "pin_fun3";
|
phandle = <0x2b2>;
|
};
|
|
rk806_dvs2_null {
|
pins = "gpio_pwrctrl2";
|
function = "pin_fun0";
|
phandle = <0x15e>;
|
};
|
|
rk806_dvs2_slp {
|
pins = "gpio_pwrctrl2";
|
function = "pin_fun1";
|
phandle = <0x2b3>;
|
};
|
|
rk806_dvs2_pwrdn {
|
pins = "gpio_pwrctrl2";
|
function = "pin_fun2";
|
phandle = <0x2b4>;
|
};
|
|
rk806_dvs2_rst {
|
pins = "gpio_pwrctrl2";
|
function = "pin_fun3";
|
phandle = <0x2b5>;
|
};
|
|
rk806_dvs2_dvs {
|
pins = "gpio_pwrctrl2";
|
function = "pin_fun4";
|
phandle = <0x2b6>;
|
};
|
|
rk806_dvs2_gpio {
|
pins = "gpio_pwrctrl2";
|
function = "pin_fun5";
|
phandle = <0x2b7>;
|
};
|
|
rk806_dvs3_null {
|
pins = "gpio_pwrctrl3";
|
function = "pin_fun0";
|
phandle = <0x15f>;
|
};
|
|
rk806_dvs3_slp {
|
pins = "gpio_pwrctrl3";
|
function = "pin_fun1";
|
phandle = <0x2b8>;
|
};
|
|
rk806_dvs3_pwrdn {
|
pins = "gpio_pwrctrl3";
|
function = "pin_fun2";
|
phandle = <0x2b9>;
|
};
|
|
rk806_dvs3_rst {
|
pins = "gpio_pwrctrl3";
|
function = "pin_fun3";
|
phandle = <0x2ba>;
|
};
|
|
rk806_dvs3_dvs {
|
pins = "gpio_pwrctrl3";
|
function = "pin_fun4";
|
phandle = <0x2bb>;
|
};
|
|
rk806_dvs3_gpio {
|
pins = "gpio_pwrctrl3";
|
function = "pin_fun5";
|
phandle = <0x2bc>;
|
};
|
};
|
|
regulators {
|
|
DCDC_REG1 {
|
regulator-boot-on;
|
regulator-min-microvolt = <0x86470>;
|
regulator-max-microvolt = <0xe7ef0>;
|
regulator-ramp-delay = <0x30d4>;
|
regulator-name = "vdd_gpu_s0";
|
regulator-enable-ramp-delay = <0x190>;
|
phandle = <0x59>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
|
DCDC_REG2 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x86470>;
|
regulator-max-microvolt = <0xe7ef0>;
|
regulator-ramp-delay = <0x30d4>;
|
regulator-name = "vdd_cpu_lit_s0";
|
phandle = <0x12>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
|
DCDC_REG3 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0xa4cb8>;
|
regulator-max-microvolt = <0xb71b0>;
|
regulator-ramp-delay = <0x30d4>;
|
regulator-name = "vdd_log_s0";
|
phandle = <0x3f>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
regulator-suspend-microvolt = <0xb71b0>;
|
};
|
};
|
|
DCDC_REG4 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x86470>;
|
regulator-max-microvolt = <0xe7ef0>;
|
regulator-init-microvolt = <0xb71b0>;
|
regulator-ramp-delay = <0x30d4>;
|
regulator-name = "vdd_vdenc_s0";
|
phandle = <0xb8>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
|
DCDC_REG5 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0xa4cb8>;
|
regulator-max-microvolt = <0xdbba0>;
|
regulator-ramp-delay = <0x30d4>;
|
regulator-name = "vdd_ddr_s0";
|
phandle = <0x3e>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
regulator-suspend-microvolt = <0xcf850>;
|
};
|
};
|
|
DCDC_REG6 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-name = "vdd2_ddr_s3";
|
phandle = <0x2bd>;
|
|
regulator-state-mem {
|
regulator-on-in-suspend;
|
};
|
};
|
|
DCDC_REG7 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x1e8480>;
|
regulator-max-microvolt = <0x1e8480>;
|
regulator-name = "vdd_2v0_pldo_s3";
|
phandle = <0x161>;
|
|
regulator-state-mem {
|
regulator-on-in-suspend;
|
regulator-suspend-microvolt = <0x1e8480>;
|
};
|
};
|
|
DCDC_REG8 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x325aa0>;
|
regulator-max-microvolt = <0x325aa0>;
|
regulator-name = "vcc_3v3_s3";
|
phandle = <0x2be>;
|
|
regulator-state-mem {
|
regulator-on-in-suspend;
|
regulator-suspend-microvolt = <0x325aa0>;
|
};
|
};
|
|
DCDC_REG9 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-name = "vddq_ddr_s0";
|
phandle = <0x2bf>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
|
DCDC_REG10 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x1b7740>;
|
regulator-max-microvolt = <0x1b7740>;
|
regulator-name = "vcc_1v8_s3";
|
phandle = <0x2c0>;
|
|
regulator-state-mem {
|
regulator-on-in-suspend;
|
regulator-suspend-microvolt = <0x1b7740>;
|
};
|
};
|
|
PLDO_REG1 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x1b7740>;
|
regulator-max-microvolt = <0x1b7740>;
|
regulator-name = "avcc_1v8_s0";
|
phandle = <0x1dd>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
|
PLDO_REG2 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x1b7740>;
|
regulator-max-microvolt = <0x1b7740>;
|
regulator-name = "vcc_1v8_s0";
|
phandle = <0x17e>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
regulator-suspend-microvolt = <0x1b7740>;
|
};
|
};
|
|
PLDO_REG3 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x124f80>;
|
regulator-max-microvolt = <0x124f80>;
|
regulator-name = "avdd_1v2_s0";
|
phandle = <0x2c1>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
|
PLDO_REG4 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x325aa0>;
|
regulator-max-microvolt = <0x325aa0>;
|
regulator-name = "vcc_3v3_s0";
|
phandle = <0x2c2>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
|
PLDO_REG5 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x1b7740>;
|
regulator-max-microvolt = <0x325aa0>;
|
regulator-name = "vccio_sd_s0";
|
phandle = <0x117>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
|
PLDO_REG6 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x1b7740>;
|
regulator-max-microvolt = <0x1b7740>;
|
regulator-name = "pldo6_s3";
|
phandle = <0x2c3>;
|
|
regulator-state-mem {
|
regulator-on-in-suspend;
|
regulator-suspend-microvolt = <0x1b7740>;
|
};
|
};
|
|
NLDO_REG1 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0xb71b0>;
|
regulator-max-microvolt = <0xb71b0>;
|
regulator-name = "vdd_0v75_s3";
|
phandle = <0x2c4>;
|
|
regulator-state-mem {
|
regulator-on-in-suspend;
|
regulator-suspend-microvolt = <0xb71b0>;
|
};
|
};
|
|
NLDO_REG2 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0xcf850>;
|
regulator-max-microvolt = <0xcf850>;
|
regulator-name = "vdd_ddr_pll_s0";
|
phandle = <0x2c5>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
regulator-suspend-microvolt = <0xcf850>;
|
};
|
};
|
|
NLDO_REG3 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0xcc77c>;
|
regulator-max-microvolt = <0xcc77c>;
|
regulator-name = "avdd_0v75_s0";
|
phandle = <0x1de>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
|
NLDO_REG4 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0xcf850>;
|
regulator-max-microvolt = <0xcf850>;
|
regulator-name = "vdd_0v85_s0";
|
phandle = <0x1dc>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
|
NLDO_REG5 {
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0xb71b0>;
|
regulator-max-microvolt = <0xb71b0>;
|
regulator-name = "vdd_0v75_s0";
|
phandle = <0x2c6>;
|
|
regulator-state-mem {
|
regulator-off-in-suspend;
|
};
|
};
|
};
|
};
|
};
|
|
spi@feb30000 {
|
compatible = "rockchip,rk3066-spi";
|
reg = <0x0 0xfeb30000 0x0 0x1000>;
|
interrupts = <0x0 0x149 0x4>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
clocks = <0x2 0xa6 0x2 0xa1>;
|
clock-names = "spiclk", "apb_pclk";
|
dmas = <0xe5 0x11 0xe5 0x12>;
|
dma-names = "tx", "rx";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x163 0x164 0x165>;
|
num-cs = <0x2>;
|
status = "disabled";
|
phandle = <0x2c7>;
|
};
|
|
serial@feb40000 {
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfeb40000 0x0 0x100>;
|
interrupts = <0x0 0x14c 0x4>;
|
clocks = <0x2 0xb7 0x2 0xab>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <0x2>;
|
reg-io-width = <0x4>;
|
dmas = <0x6f 0x8 0x6f 0x9>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x166>;
|
status = "okay";
|
phandle = <0x2c8>;
|
};
|
|
serial@feb50000 {
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfeb50000 0x0 0x100>;
|
interrupts = <0x0 0x14d 0x4>;
|
clocks = <0x2 0xbb 0x2 0xac>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <0x2>;
|
reg-io-width = <0x4>;
|
dmas = <0x6f 0xa 0x6f 0xb>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x167>;
|
status = "disabled";
|
phandle = <0x2c9>;
|
};
|
|
serial@feb60000 {
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfeb60000 0x0 0x100>;
|
interrupts = <0x0 0x14e 0x4>;
|
clocks = <0x2 0xbf 0x2 0xad>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <0x2>;
|
reg-io-width = <0x4>;
|
dmas = <0x6f 0xc 0x6f 0xd>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x168>;
|
status = "disabled";
|
phandle = <0x2ca>;
|
};
|
|
serial@feb70000 {
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfeb70000 0x0 0x100>;
|
interrupts = <0x0 0x14f 0x4>;
|
clocks = <0x2 0xc3 0x2 0xae>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <0x2>;
|
reg-io-width = <0x4>;
|
dmas = <0xe5 0x9 0xe5 0xa>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x169>;
|
status = "okay";
|
phandle = <0x2cb>;
|
};
|
|
serial@feb80000 {
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfeb80000 0x0 0x100>;
|
interrupts = <0x0 0x150 0x4>;
|
clocks = <0x2 0xc7 0x2 0xaf>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <0x2>;
|
reg-io-width = <0x4>;
|
dmas = <0xe5 0xb 0xe5 0xc>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x16a>;
|
status = "okay";
|
phandle = <0x2cc>;
|
};
|
|
serial@feb90000 {
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfeb90000 0x0 0x100>;
|
interrupts = <0x0 0x151 0x4>;
|
clocks = <0x2 0xcb 0x2 0xb0>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <0x2>;
|
reg-io-width = <0x4>;
|
dmas = <0xe5 0xd 0xe5 0xe>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x16b>;
|
status = "okay";
|
phandle = <0x2cd>;
|
};
|
|
serial@feba0000 {
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfeba0000 0x0 0x100>;
|
interrupts = <0x0 0x152 0x4>;
|
clocks = <0x2 0xcf 0x2 0xb1>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <0x2>;
|
reg-io-width = <0x4>;
|
dmas = <0xe6 0x7 0xe6 0x8>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x16c>;
|
status = "okay";
|
phandle = <0x2ce>;
|
};
|
|
serial@febb0000 {
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfebb0000 0x0 0x100>;
|
interrupts = <0x0 0x153 0x4>;
|
clocks = <0x2 0xd3 0x2 0xb2>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <0x2>;
|
reg-io-width = <0x4>;
|
dmas = <0xe6 0x9 0xe6 0xa>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x16d>;
|
status = "disabled";
|
phandle = <0x2cf>;
|
};
|
|
serial@febc0000 {
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
reg = <0x0 0xfebc0000 0x0 0x100>;
|
interrupts = <0x0 0x154 0x4>;
|
clocks = <0x2 0xd7 0x2 0xb3>;
|
clock-names = "baudclk", "apb_pclk";
|
reg-shift = <0x2>;
|
reg-io-width = <0x4>;
|
dmas = <0xe6 0xb 0xe6 0xc>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x16e 0x16f>;
|
status = "okay";
|
phandle = <0x2d0>;
|
};
|
|
pwm@febd0000 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfebd0000 0x0 0x10>;
|
interrupts = <0x0 0x15a 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x170>;
|
clocks = <0x2 0x54 0x2 0x53>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x2d1>;
|
};
|
|
pwm@febd0010 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfebd0010 0x0 0x10>;
|
interrupts = <0x0 0x15a 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x171>;
|
clocks = <0x2 0x54 0x2 0x53>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x2d2>;
|
};
|
|
pwm@febd0020 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfebd0020 0x0 0x10>;
|
interrupts = <0x0 0x15a 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x172>;
|
clocks = <0x2 0x54 0x2 0x53>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x2d3>;
|
};
|
|
pwm@febd0030 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfebd0030 0x0 0x10>;
|
interrupts = <0x0 0x15a 0x4 0x0 0x15b 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x173>;
|
clocks = <0x2 0x54 0x2 0x53>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x2d4>;
|
};
|
|
pwm@febe0000 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfebe0000 0x0 0x10>;
|
interrupts = <0x0 0x15c 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x174>;
|
clocks = <0x2 0x57 0x2 0x56>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x2d5>;
|
};
|
|
pwm@febe0010 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfebe0010 0x0 0x10>;
|
interrupts = <0x0 0x15c 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x175>;
|
clocks = <0x2 0x57 0x2 0x56>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x2d6>;
|
};
|
|
pwm@febe0020 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfebe0020 0x0 0x10>;
|
interrupts = <0x0 0x15c 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x176>;
|
clocks = <0x2 0x57 0x2 0x56>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x2d7>;
|
};
|
|
pwm@febe0030 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfebe0030 0x0 0x10>;
|
interrupts = <0x0 0x15c 0x4 0x0 0x15d 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x177>;
|
clocks = <0x2 0x57 0x2 0x56>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x1c6>;
|
};
|
|
pwm@febf0000 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfebf0000 0x0 0x10>;
|
interrupts = <0x0 0x15e 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x178>;
|
clocks = <0x2 0x5a 0x2 0x59>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x2d8>;
|
};
|
|
pwm@febf0010 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfebf0010 0x0 0x10>;
|
interrupts = <0x0 0x15e 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x179>;
|
clocks = <0x2 0x5a 0x2 0x59>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x2d9>;
|
};
|
|
pwm@febf0020 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfebf0020 0x0 0x10>;
|
interrupts = <0x0 0x15e 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x17a>;
|
clocks = <0x2 0x5a 0x2 0x59>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x2da>;
|
};
|
|
pwm@febf0030 {
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
reg = <0x0 0xfebf0030 0x0 0x10>;
|
interrupts = <0x0 0x15e 0x4 0x0 0x15f 0x4>;
|
#pwm-cells = <0x3>;
|
pinctrl-names = "active";
|
pinctrl-0 = <0x17b>;
|
clocks = <0x2 0x5a 0x2 0x59>;
|
clock-names = "pwm", "pclk";
|
status = "disabled";
|
phandle = <0x2db>;
|
};
|
|
tsadc@fec00000 {
|
compatible = "rockchip,rk3588-tsadc";
|
reg = <0x0 0xfec00000 0x0 0x400>;
|
interrupts = <0x0 0x18d 0x4>;
|
clocks = <0x2 0xaa 0x2 0xa9>;
|
clock-names = "tsadc", "apb_pclk";
|
assigned-clocks = <0x2 0xaa>;
|
assigned-clock-rates = <0x1e8480>;
|
resets = <0x2 0xc1 0x2 0xc0>;
|
reset-names = "tsadc", "tsadc-apb";
|
#thermal-sensor-cells = <0x1>;
|
rockchip,hw-tshut-temp = <0x1d4c0>;
|
rockchip,hw-tshut-mode = <0x0>;
|
rockchip,hw-tshut-polarity = <0x0>;
|
pinctrl-names = "gpio", "otpout";
|
pinctrl-0 = <0x17c>;
|
pinctrl-1 = <0x17d>;
|
status = "okay";
|
phandle = <0x54>;
|
};
|
|
saradc@fec10000 {
|
compatible = "rockchip,rk3588-saradc";
|
reg = <0x0 0xfec10000 0x0 0x10000>;
|
interrupts = <0x0 0x18e 0x4>;
|
#io-channel-cells = <0x1>;
|
clocks = <0x2 0x9d 0x2 0x9c>;
|
clock-names = "saradc", "apb_pclk";
|
resets = <0x2 0xbe>;
|
reset-names = "saradc-apb";
|
status = "okay";
|
vref-supply = <0x17e>;
|
phandle = <0x1c4>;
|
};
|
|
mailbox@fec60000 {
|
compatible = "rockchip,rk3588-mailbox", "rockchip,rk3368-mailbox";
|
reg = <0x0 0xfec60000 0x0 0x200>;
|
interrupts = <0x0 0x3d 0x4 0x0 0x3e 0x4 0x0 0x3f 0x4 0x0 0x40 0x4>;
|
clocks = <0x2 0x4c>;
|
clock-names = "pclk_mailbox";
|
#mbox-cells = <0x1>;
|
status = "disabled";
|
phandle = <0x2dc>;
|
};
|
|
mailbox@fec70000 {
|
compatible = "rockchip,rk3588-mailbox", "rockchip,rk3368-mailbox";
|
reg = <0x0 0xfec70000 0x0 0x200>;
|
interrupts = <0x0 0x45 0x4 0x0 0x46 0x4 0x0 0x47 0x4 0x0 0x48 0x4>;
|
clocks = <0x2 0x4d>;
|
clock-names = "pclk_mailbox";
|
#mbox-cells = <0x1>;
|
status = "disabled";
|
phandle = <0x2dd>;
|
};
|
|
i2c@fec80000 {
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
reg = <0x0 0xfec80000 0x0 0x1000>;
|
clocks = <0x2 0x92 0x2 0x8a>;
|
clock-names = "i2c", "pclk";
|
interrupts = <0x0 0x143 0x4>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x17f>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
status = "okay";
|
phandle = <0x2de>;
|
|
nkmcu@15 {
|
compatible = "nk_mcu";
|
reg = <0x15>;
|
};
|
|
hym8563@51 {
|
compatible = "haoyu,hym8563";
|
reg = <0x51>;
|
#clock-cells = <0x0>;
|
clock-frequency = <0x8000>;
|
clock-output-names = "hym8563";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x180>;
|
interrupt-parent = <0x15b>;
|
interrupts = <0x8 0x8>;
|
wakeup-source;
|
phandle = <0x1df>;
|
};
|
|
eeprom@50 {
|
compatible = "atmel,24c256";
|
reg = <0x50>;
|
};
|
|
eeprom@53 {
|
compatible = "atmel,24c256";
|
reg = <0x53>;
|
};
|
};
|
|
i2c@fec90000 {
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
reg = <0x0 0xfec90000 0x0 0x1000>;
|
clocks = <0x2 0x93 0x2 0x8b>;
|
clock-names = "i2c", "pclk";
|
interrupts = <0x0 0x144 0x4>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x181>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x2df>;
|
};
|
|
i2c@feca0000 {
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
reg = <0x0 0xfeca0000 0x0 0x1000>;
|
clocks = <0x2 0x94 0x2 0x8c>;
|
clock-names = "i2c", "pclk";
|
interrupts = <0x0 0x145 0x4>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x182>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x2e0>;
|
};
|
|
spi@fecb0000 {
|
compatible = "rockchip,rk3066-spi";
|
reg = <0x0 0xfecb0000 0x0 0x1000>;
|
interrupts = <0x0 0x14a 0x4>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
clocks = <0x2 0xa7 0x2 0xa2>;
|
clock-names = "spiclk", "apb_pclk";
|
dmas = <0xe6 0xd 0xe6 0xe>;
|
dma-names = "tx", "rx";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x183 0x184 0x185>;
|
num-cs = <0x2>;
|
status = "disabled";
|
phandle = <0x2e1>;
|
};
|
|
otp@fecc0000 {
|
compatible = "rockchip,rk3588-otp";
|
reg = <0x0 0xfecc0000 0x0 0x400>;
|
#address-cells = <0x1>;
|
#size-cells = <0x1>;
|
clocks = <0x2 0x96 0x2 0x95 0x2 0x97 0x2 0x99>;
|
clock-names = "otpc", "apb", "arb", "phy";
|
resets = <0x2 0x12a 0x2 0x129 0x2 0x12b>;
|
reset-names = "otpc", "apb", "arb";
|
phandle = <0x2e2>;
|
|
cpu-code@2 {
|
reg = <0x2 0x2>;
|
phandle = <0x2c>;
|
};
|
|
package-serial-number-high@5 {
|
reg = <0x5 0x1>;
|
bits = <0x0 0x1>;
|
phandle = <0xc9>;
|
};
|
|
package-serial-number-low@6 {
|
reg = <0x6 0x1>;
|
bits = <0x5 0x3>;
|
phandle = <0xc8>;
|
};
|
|
specification-serial-number@6 {
|
reg = <0x6 0x1>;
|
bits = <0x0 0x5>;
|
phandle = <0x21>;
|
};
|
|
id@7 {
|
reg = <0x7 0x10>;
|
phandle = <0x2a>;
|
};
|
|
cpu-version@1c {
|
reg = <0x1c 0x1>;
|
bits = <0x3 0x3>;
|
phandle = <0x2b>;
|
};
|
|
cpub0-leakage@17 {
|
reg = <0x17 0x1>;
|
phandle = <0x24>;
|
};
|
|
cpub1-leakage@18 {
|
reg = <0x18 0x1>;
|
phandle = <0x27>;
|
};
|
|
cpul-leakage@19 {
|
reg = <0x19 0x1>;
|
phandle = <0x1f>;
|
};
|
|
log-leakage@1a {
|
reg = <0x1a 0x1>;
|
phandle = <0x40>;
|
};
|
|
gpu-leakage@1b {
|
reg = <0x1b 0x1>;
|
phandle = <0x5a>;
|
};
|
|
npu-leakage@28 {
|
reg = <0x28 0x1>;
|
phandle = <0xa7>;
|
};
|
|
codec-leakage@29 {
|
reg = <0x29 0x1>;
|
phandle = <0xba>;
|
};
|
|
cpul-opp-info@3d {
|
reg = <0x3d 0x6>;
|
phandle = <0x20>;
|
};
|
|
cpub01-opp-info@43 {
|
reg = <0x43 0x6>;
|
phandle = <0x25>;
|
};
|
|
cpub23-opp-info@49 {
|
reg = <0x49 0x6>;
|
phandle = <0x28>;
|
};
|
|
gpu-opp-info@4f {
|
reg = <0x4f 0x6>;
|
phandle = <0x5b>;
|
};
|
|
npu-opp-info@55 {
|
reg = <0x55 0x6>;
|
phandle = <0xa8>;
|
};
|
|
dmc-opp-info@5b {
|
reg = <0x5b 0x6>;
|
phandle = <0x41>;
|
};
|
|
vop-opp-info@61 {
|
reg = <0x61 0x6>;
|
phandle = <0x2e3>;
|
};
|
|
venc-opp-info@67 {
|
reg = <0x67 0x6>;
|
phandle = <0xbb>;
|
};
|
};
|
|
mailbox@fece0000 {
|
compatible = "rockchip,rk3588-mailbox", "rockchip,rk3368-mailbox";
|
reg = <0x0 0xfece0000 0x0 0x200>;
|
interrupts = <0x0 0x4d 0x4 0x0 0x4e 0x4 0x0 0x4f 0x4 0x0 0x50 0x4>;
|
clocks = <0x2 0x4e>;
|
clock-names = "pclk_mailbox";
|
#mbox-cells = <0x1>;
|
status = "disabled";
|
phandle = <0x2e4>;
|
};
|
|
dma-controller@fed10000 {
|
compatible = "arm,pl330", "arm,primecell";
|
reg = <0x0 0xfed10000 0x0 0x4000>;
|
interrupts = <0x0 0x5a 0x4 0x0 0x5b 0x4>;
|
clocks = <0x2 0x7a>;
|
clock-names = "apb_pclk";
|
#dma-cells = <0x1>;
|
arm,pl330-periph-burst;
|
phandle = <0xe6>;
|
};
|
|
phy@fed60000 {
|
compatible = "rockchip,rk3588-hdptx-phy";
|
reg = <0x0 0xfed60000 0x0 0x2000>;
|
clocks = <0x2 0x2b5 0x2 0x267>;
|
clock-names = "ref", "apb";
|
resets = <0x2 0x485 0x2 0xc003b 0x2 0xc003c 0x2 0xc003d>;
|
reset-names = "apb", "init", "cmn", "lane";
|
rockchip,grf = <0x186>;
|
#phy-cells = <0x0>;
|
status = "disabled";
|
phandle = <0xff>;
|
};
|
|
hdmiphy@fed60000 {
|
compatible = "rockchip,rk3588-hdptx-phy-hdmi";
|
reg = <0x0 0xfed60000 0x0 0x2000>;
|
clocks = <0x2 0x2b5 0x2 0x267>;
|
clock-names = "ref", "apb";
|
resets = <0x2 0x48e 0x2 0x485 0x2 0xc003b 0x2 0xc003c 0x2 0xc003d 0x2 0x48c 0x2 0x48d>;
|
reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
|
rockchip,grf = <0x186>;
|
#phy-cells = <0x0>;
|
status = "okay";
|
phandle = <0xfb>;
|
|
clk-port {
|
#clock-cells = <0x0>;
|
status = "okay";
|
phandle = <0xf6>;
|
};
|
};
|
|
phy@fed80000 {
|
compatible = "rockchip,rk3588-usbdp-phy";
|
reg = <0x0 0xfed80000 0x0 0x10000>;
|
rockchip,u2phy-grf = <0x187>;
|
rockchip,usb-grf = <0x6a>;
|
rockchip,usbdpphy-grf = <0x188>;
|
rockchip,vo-grf = <0xf2>;
|
clocks = <0x2 0x2b6 0x2 0x27f 0x2 0x269 0x189>;
|
clock-names = "refclk", "immortal", "pclk", "utmi";
|
resets = <0x2 0x28 0x2 0x29 0x2 0x2a 0x2 0x2b 0x2 0x482>;
|
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
status = "okay";
|
phandle = <0x2e5>;
|
|
dp-port {
|
#phy-cells = <0x0>;
|
status = "okay";
|
phandle = <0xf3>;
|
};
|
|
u3-port {
|
#phy-cells = <0x0>;
|
status = "okay";
|
phandle = <0x5e>;
|
};
|
};
|
|
phy@feda0000 {
|
compatible = "rockchip,rk3588-mipi-dcphy";
|
reg = <0x0 0xfeda0000 0x0 0x10000>;
|
rockchip,grf = <0x18a>;
|
clocks = <0x2 0x108 0x2 0x2b6>;
|
clock-names = "pclk", "ref";
|
resets = <0x2 0xc0043 0x2 0x3e 0x2 0x3f 0x2 0xc0044>;
|
reset-names = "m_phy", "apb", "grf", "s_phy";
|
#phy-cells = <0x0>;
|
status = "okay";
|
phandle = <0x2f>;
|
};
|
|
phy@fedb0000 {
|
compatible = "rockchip,rk3588-mipi-dcphy";
|
reg = <0x0 0xfedb0000 0x0 0x10000>;
|
rockchip,grf = <0x18b>;
|
clocks = <0x2 0x109 0x2 0x2b6>;
|
clock-names = "pclk", "ref";
|
resets = <0x2 0xc0045 0x2 0x43 0x2 0x44 0x2 0xc0046>;
|
reset-names = "m_phy", "apb", "grf", "s_phy";
|
#phy-cells = <0x0>;
|
status = "okay";
|
phandle = <0x30>;
|
};
|
|
csi2-dphy0-hw@fedc0000 {
|
compatible = "rockchip,rk3588-csi2-dphy-hw";
|
reg = <0x0 0xfedc0000 0x0 0x8000>;
|
clocks = <0x2 0x10c>;
|
clock-names = "pclk";
|
resets = <0x2 0x17 0x2 0x16>;
|
reset-names = "srst_csiphy0", "srst_p_csiphy0";
|
rockchip,grf = <0x18c>;
|
rockchip,sys_grf = <0xbc>;
|
status = "okay";
|
phandle = <0x2d>;
|
};
|
|
csi2-dphy1-hw@fedc8000 {
|
compatible = "rockchip,rk3588-csi2-dphy-hw";
|
reg = <0x0 0xfedc8000 0x0 0x8000>;
|
clocks = <0x2 0x10d>;
|
clock-names = "pclk";
|
resets = <0x2 0x19 0x2 0x18>;
|
reset-names = "srst_csiphy1", "srst_p_csiphy1";
|
rockchip,grf = <0x18d>;
|
rockchip,sys_grf = <0xbc>;
|
status = "okay";
|
phandle = <0x2e>;
|
};
|
|
phy@fee00000 {
|
compatible = "rockchip,rk3588-naneng-combphy";
|
reg = <0x0 0xfee00000 0x0 0x100>;
|
#phy-cells = <0x1>;
|
clocks = <0x2 0x2bd 0x2 0x185 0x2 0x166>;
|
clock-names = "refclk", "apbclk", "phpclk";
|
assigned-clocks = <0x2 0x2bd>;
|
assigned-clock-rates = <0x5f5e100>;
|
resets = <0x2 0x20005 0x2 0x4d6>;
|
reset-names = "combphy-apb", "combphy";
|
rockchip,pipe-grf = <0x6c>;
|
rockchip,pipe-phy-grf = <0x18e>;
|
status = "okay";
|
phandle = <0x107>;
|
};
|
|
phy@fee20000 {
|
compatible = "rockchip,rk3588-naneng-combphy";
|
reg = <0x0 0xfee20000 0x0 0x100>;
|
#phy-cells = <0x1>;
|
clocks = <0x2 0x2bf 0x2 0x187 0x2 0x166>;
|
clock-names = "refclk", "apbclk", "phpclk";
|
assigned-clocks = <0x2 0x2bf>;
|
assigned-clock-rates = <0x5f5e100>;
|
resets = <0x2 0x20007 0x2 0x4d8>;
|
reset-names = "combphy-apb", "combphy";
|
rockchip,pipe-grf = <0x6c>;
|
rockchip,pipe-phy-grf = <0x18f>;
|
rockchip,pcie1ln-sel-bits = <0x100 0x1 0x1 0x0>;
|
status = "okay";
|
phandle = <0x66>;
|
};
|
|
sram@ff001000 {
|
compatible = "mmio-sram";
|
reg = <0x0 0xff001000 0x0 0xef000>;
|
#address-cells = <0x1>;
|
#size-cells = <0x1>;
|
ranges = <0x0 0x0 0xff001000 0xef000>;
|
phandle = <0x2e6>;
|
|
rkvdec-sram@0 {
|
reg = <0x0 0x78000>;
|
phandle = <0xbf>;
|
};
|
|
rkvdec-sram@78000 {
|
reg = <0x78000 0x77000>;
|
phandle = <0xc1>;
|
};
|
};
|
|
pinctrl {
|
compatible = "rockchip,rk3588-pinctrl";
|
rockchip,grf = <0x190>;
|
#address-cells = <0x2>;
|
#size-cells = <0x2>;
|
ranges;
|
phandle = <0x191>;
|
|
gpio@fd8a0000 {
|
compatible = "rockchip,gpio-bank";
|
reg = <0x0 0xfd8a0000 0x0 0x100>;
|
interrupts = <0x0 0x115 0x4>;
|
clocks = <0x2 0x284 0x2 0x285>;
|
gpio-controller;
|
#gpio-cells = <0x2>;
|
gpio-ranges = <0x191 0x0 0x0 0x20>;
|
interrupt-controller;
|
#interrupt-cells = <0x2>;
|
phandle = <0x15b>;
|
};
|
|
gpio@fec20000 {
|
compatible = "rockchip,gpio-bank";
|
reg = <0x0 0xfec20000 0x0 0x100>;
|
interrupts = <0x0 0x116 0x4>;
|
clocks = <0x2 0x7d 0x2 0x7e>;
|
gpio-controller;
|
#gpio-cells = <0x2>;
|
gpio-ranges = <0x191 0x0 0x20 0x20>;
|
interrupt-controller;
|
#interrupt-cells = <0x2>;
|
phandle = <0x1b2>;
|
};
|
|
gpio@fec30000 {
|
compatible = "rockchip,gpio-bank";
|
reg = <0x0 0xfec30000 0x0 0x100>;
|
interrupts = <0x0 0x117 0x4>;
|
clocks = <0x2 0x7f 0x2 0x80>;
|
gpio-controller;
|
#gpio-cells = <0x2>;
|
gpio-ranges = <0x191 0x0 0x40 0x20>;
|
interrupt-controller;
|
#interrupt-cells = <0x2>;
|
phandle = <0x1e8>;
|
};
|
|
gpio@fec40000 {
|
compatible = "rockchip,gpio-bank";
|
reg = <0x0 0xfec40000 0x0 0x100>;
|
interrupts = <0x0 0x118 0x4>;
|
clocks = <0x2 0x81 0x2 0x82>;
|
gpio-controller;
|
#gpio-cells = <0x2>;
|
gpio-ranges = <0x191 0x0 0x60 0x20>;
|
interrupt-controller;
|
#interrupt-cells = <0x2>;
|
phandle = <0x108>;
|
};
|
|
gpio@fec50000 {
|
compatible = "rockchip,gpio-bank";
|
reg = <0x0 0xfec50000 0x0 0x100>;
|
interrupts = <0x0 0x119 0x4>;
|
clocks = <0x2 0x83 0x2 0x84>;
|
gpio-controller;
|
#gpio-cells = <0x2>;
|
gpio-ranges = <0x191 0x0 0x80 0x20>;
|
interrupt-controller;
|
#interrupt-cells = <0x2>;
|
phandle = <0xfc>;
|
};
|
|
pcfg-pull-up {
|
bias-pull-up;
|
phandle = <0x197>;
|
};
|
|
pcfg-pull-down {
|
bias-pull-down;
|
phandle = <0x198>;
|
};
|
|
pcfg-pull-none {
|
bias-disable;
|
phandle = <0x192>;
|
};
|
|
pcfg-pull-none-drv-level-0 {
|
bias-disable;
|
drive-strength = <0x0>;
|
phandle = <0x2e7>;
|
};
|
|
pcfg-pull-none-drv-level-1 {
|
bias-disable;
|
drive-strength = <0x1>;
|
phandle = <0x2e8>;
|
};
|
|
pcfg-pull-none-drv-level-2 {
|
bias-disable;
|
drive-strength = <0x2>;
|
phandle = <0x19b>;
|
};
|
|
pcfg-pull-none-drv-level-3 {
|
bias-disable;
|
drive-strength = <0x3>;
|
phandle = <0x2e9>;
|
};
|
|
pcfg-pull-none-drv-level-4 {
|
bias-disable;
|
drive-strength = <0x4>;
|
phandle = <0x2ea>;
|
};
|
|
pcfg-pull-none-drv-level-5 {
|
bias-disable;
|
drive-strength = <0x5>;
|
phandle = <0x2eb>;
|
};
|
|
pcfg-pull-none-drv-level-6 {
|
bias-disable;
|
drive-strength = <0x6>;
|
phandle = <0x2ec>;
|
};
|
|
pcfg-pull-up-drv-level-0 {
|
bias-pull-up;
|
drive-strength = <0x0>;
|
phandle = <0x2ed>;
|
};
|
|
pcfg-pull-up-drv-level-1 {
|
bias-pull-up;
|
drive-strength = <0x1>;
|
phandle = <0x19a>;
|
};
|
|
pcfg-pull-up-drv-level-2 {
|
bias-pull-up;
|
drive-strength = <0x2>;
|
phandle = <0x193>;
|
};
|
|
pcfg-pull-up-drv-level-3 {
|
bias-pull-up;
|
drive-strength = <0x3>;
|
phandle = <0x2ee>;
|
};
|
|
pcfg-pull-up-drv-level-4 {
|
bias-pull-up;
|
drive-strength = <0x4>;
|
phandle = <0x2ef>;
|
};
|
|
pcfg-pull-up-drv-level-5 {
|
bias-pull-up;
|
drive-strength = <0x5>;
|
phandle = <0x2f0>;
|
};
|
|
pcfg-pull-up-drv-level-6 {
|
bias-pull-up;
|
drive-strength = <0x6>;
|
phandle = <0x199>;
|
};
|
|
pcfg-pull-down-drv-level-0 {
|
bias-pull-down;
|
drive-strength = <0x0>;
|
phandle = <0x2f1>;
|
};
|
|
pcfg-pull-down-drv-level-1 {
|
bias-pull-down;
|
drive-strength = <0x1>;
|
phandle = <0x2f2>;
|
};
|
|
pcfg-pull-down-drv-level-2 {
|
bias-pull-down;
|
drive-strength = <0x2>;
|
phandle = <0x2f3>;
|
};
|
|
pcfg-pull-down-drv-level-3 {
|
bias-pull-down;
|
drive-strength = <0x3>;
|
phandle = <0x2f4>;
|
};
|
|
pcfg-pull-down-drv-level-4 {
|
bias-pull-down;
|
drive-strength = <0x4>;
|
phandle = <0x2f5>;
|
};
|
|
pcfg-pull-down-drv-level-5 {
|
bias-pull-down;
|
drive-strength = <0x5>;
|
phandle = <0x2f6>;
|
};
|
|
pcfg-pull-down-drv-level-6 {
|
bias-pull-down;
|
drive-strength = <0x6>;
|
phandle = <0x2f7>;
|
};
|
|
pcfg-pull-up-smt {
|
bias-pull-up;
|
input-schmitt-enable;
|
phandle = <0x2f8>;
|
};
|
|
pcfg-pull-down-smt {
|
bias-pull-down;
|
input-schmitt-enable;
|
phandle = <0x2f9>;
|
};
|
|
pcfg-pull-none-smt {
|
bias-disable;
|
input-schmitt-enable;
|
phandle = <0x196>;
|
};
|
|
pcfg-pull-none-drv-level-0-smt {
|
bias-disable;
|
drive-strength = <0x0>;
|
input-schmitt-enable;
|
phandle = <0x2fa>;
|
};
|
|
pcfg-pull-none-drv-level-1-smt {
|
bias-disable;
|
drive-strength = <0x1>;
|
input-schmitt-enable;
|
phandle = <0x195>;
|
};
|
|
pcfg-pull-none-drv-level-2-smt {
|
bias-disable;
|
drive-strength = <0x2>;
|
input-schmitt-enable;
|
phandle = <0x2fb>;
|
};
|
|
pcfg-pull-none-drv-level-3-smt {
|
bias-disable;
|
drive-strength = <0x3>;
|
input-schmitt-enable;
|
phandle = <0x2fc>;
|
};
|
|
pcfg-pull-none-drv-level-4-smt {
|
bias-disable;
|
drive-strength = <0x4>;
|
input-schmitt-enable;
|
phandle = <0x2fd>;
|
};
|
|
pcfg-pull-none-drv-level-5-smt {
|
bias-disable;
|
drive-strength = <0x5>;
|
input-schmitt-enable;
|
phandle = <0x194>;
|
};
|
|
pcfg-pull-none-drv-level-6-smt {
|
bias-disable;
|
drive-strength = <0x6>;
|
input-schmitt-enable;
|
phandle = <0x2fe>;
|
};
|
|
pcfg-output-high {
|
output-high;
|
phandle = <0x2ff>;
|
};
|
|
pcfg-output-high-pull-up {
|
output-high;
|
bias-pull-up;
|
phandle = <0x300>;
|
};
|
|
pcfg-output-high-pull-down {
|
output-high;
|
bias-pull-down;
|
phandle = <0x301>;
|
};
|
|
pcfg-output-high-pull-none {
|
output-high;
|
bias-disable;
|
phandle = <0x302>;
|
};
|
|
pcfg-output-low {
|
output-low;
|
phandle = <0x303>;
|
};
|
|
pcfg-output-low-pull-up {
|
output-low;
|
bias-pull-up;
|
phandle = <0x304>;
|
};
|
|
pcfg-output-low-pull-down {
|
output-low;
|
bias-pull-down;
|
phandle = <0x305>;
|
};
|
|
pcfg-output-low-pull-none {
|
output-low;
|
bias-disable;
|
phandle = <0x306>;
|
};
|
|
auddsm {
|
|
auddsm-pins {
|
rockchip,pins = <0x3 0x1 0x4 0x192 0x3 0x2 0x4 0x192 0x3 0x3 0x4 0x192 0x3 0x4 0x4 0x192>;
|
phandle = <0x147>;
|
};
|
};
|
|
bt1120 {
|
|
bt1120-pins {
|
rockchip,pins = <0x4 0x8 0x2 0x192 0x4 0x0 0x2 0x192 0x4 0x1 0x2 0x192 0x4 0x2 0x2 0x192 0x4 0x3 0x2 0x192 0x4 0x4 0x2 0x192 0x4 0x5 0x2 0x192 0x4 0x6 0x2 0x192 0x4 0x7 0x2 0x192 0x4 0xa 0x2 0x192 0x4 0xb 0x2 0x192 0x4 0xc 0x2 0x192 0x4 0xd 0x2 0x192 0x4 0xe 0x2 0x192 0x4 0xf 0x2 0x192 0x4 0x10 0x2 0x192 0x4 0x11 0x2 0x192>;
|
phandle = <0x67>;
|
};
|
};
|
|
can0 {
|
|
can0m0-pins {
|
rockchip,pins = <0x0 0x10 0xb 0x192 0x0 0xf 0xb 0x192>;
|
phandle = <0x148>;
|
};
|
|
can0m1-pins {
|
rockchip,pins = <0x4 0x1d 0x9 0x192 0x4 0x1c 0x9 0x192>;
|
phandle = <0x307>;
|
};
|
};
|
|
can1 {
|
|
can1m0-pins {
|
rockchip,pins = <0x3 0xd 0x9 0x192 0x3 0xe 0x9 0x192>;
|
phandle = <0x308>;
|
};
|
|
can1m1-pins {
|
rockchip,pins = <0x4 0xa 0xc 0x192 0x4 0xb 0xc 0x192>;
|
phandle = <0x149>;
|
};
|
};
|
|
can2 {
|
|
can2m0-pins {
|
rockchip,pins = <0x3 0x14 0x9 0x192 0x3 0x15 0x9 0x192>;
|
phandle = <0x14a>;
|
};
|
|
can2m1-pins {
|
rockchip,pins = <0x0 0x1c 0xa 0x192 0x0 0x1d 0xa 0x192>;
|
phandle = <0x309>;
|
};
|
};
|
|
cif {
|
|
cif-clk {
|
rockchip,pins = <0x4 0xc 0x1 0x192>;
|
phandle = <0x30a>;
|
};
|
|
cif-dvp-clk {
|
rockchip,pins = <0x4 0x8 0x1 0x192 0x4 0xa 0x1 0x192 0x4 0xb 0x1 0x192>;
|
phandle = <0x30b>;
|
};
|
|
cif-dvp-bus16 {
|
rockchip,pins = <0x3 0x14 0x1 0x192 0x3 0x15 0x1 0x192 0x3 0x16 0x1 0x192 0x3 0x17 0x1 0x192 0x3 0x18 0x1 0x192 0x3 0x19 0x1 0x192 0x3 0x1a 0x1 0x192 0x3 0x1b 0x1 0x192>;
|
phandle = <0x30c>;
|
};
|
|
cif-dvp-bus8 {
|
rockchip,pins = <0x4 0x0 0x1 0x192 0x4 0x1 0x1 0x192 0x4 0x2 0x1 0x192 0x4 0x3 0x1 0x192 0x4 0x4 0x1 0x192 0x4 0x5 0x1 0x192 0x4 0x6 0x1 0x192 0x4 0x7 0x1 0x192>;
|
phandle = <0x30d>;
|
};
|
};
|
|
clk32k {
|
|
clk32k-in {
|
rockchip,pins = <0x0 0xa 0x1 0x192>;
|
phandle = <0x30e>;
|
};
|
|
clk32k-out0 {
|
rockchip,pins = <0x0 0xa 0x2 0x192>;
|
phandle = <0x30f>;
|
};
|
|
clk32k-out1 {
|
rockchip,pins = <0x2 0x15 0x1 0x192>;
|
phandle = <0x310>;
|
};
|
};
|
|
cpu {
|
|
cpu-pins {
|
rockchip,pins = <0x0 0x19 0x2 0x192 0x0 0x1d 0x2 0x192>;
|
phandle = <0x311>;
|
};
|
};
|
|
ddrphych0 {
|
|
ddrphych0-pins {
|
rockchip,pins = <0x4 0x0 0x7 0x192 0x4 0x1 0x7 0x192 0x4 0x2 0x7 0x192 0x4 0x3 0x7 0x192>;
|
phandle = <0x312>;
|
};
|
};
|
|
ddrphych1 {
|
|
ddrphych1-pins {
|
rockchip,pins = <0x4 0x4 0x7 0x192 0x4 0x5 0x7 0x192 0x4 0x6 0x7 0x192 0x4 0x7 0x7 0x192>;
|
phandle = <0x313>;
|
};
|
};
|
|
ddrphych2 {
|
|
ddrphych2-pins {
|
rockchip,pins = <0x4 0x8 0x7 0x192 0x4 0x9 0x7 0x192 0x4 0xa 0x7 0x192 0x4 0xb 0x7 0x192>;
|
phandle = <0x314>;
|
};
|
};
|
|
ddrphych3 {
|
|
ddrphych3-pins {
|
rockchip,pins = <0x4 0xc 0x7 0x192 0x4 0xd 0x7 0x192 0x4 0xe 0x7 0x192 0x4 0xf 0x7 0x192>;
|
phandle = <0x315>;
|
};
|
};
|
|
dp0 {
|
|
dp0m0-pins {
|
rockchip,pins = <0x4 0xc 0x5 0x192>;
|
phandle = <0x316>;
|
};
|
|
dp0m1-pins {
|
rockchip,pins = <0x0 0x14 0xa 0x192>;
|
phandle = <0x317>;
|
};
|
|
dp0m2-pins {
|
rockchip,pins = <0x1 0x0 0x5 0x192>;
|
phandle = <0x318>;
|
};
|
};
|
|
dp1 {
|
|
dp1m0-pins {
|
rockchip,pins = <0x3 0x1d 0x5 0x192>;
|
phandle = <0x1a1>;
|
};
|
|
dp1m1-pins {
|
rockchip,pins = <0x0 0x15 0xa 0x192>;
|
phandle = <0x319>;
|
};
|
|
dp1m2-pins {
|
rockchip,pins = <0x1 0x1 0x5 0x192>;
|
phandle = <0x31a>;
|
};
|
};
|
|
emmc {
|
|
emmc-rstnout {
|
rockchip,pins = <0x2 0x3 0x1 0x192>;
|
phandle = <0x31b>;
|
};
|
|
emmc-bus8 {
|
rockchip,pins = <0x2 0x18 0x1 0x193 0x2 0x19 0x1 0x193 0x2 0x1a 0x1 0x193 0x2 0x1b 0x1 0x193 0x2 0x1c 0x1 0x193 0x2 0x1d 0x1 0x193 0x2 0x1e 0x1 0x193 0x2 0x1f 0x1 0x193>;
|
phandle = <0x31c>;
|
};
|
|
emmc-clk {
|
rockchip,pins = <0x2 0x1 0x1 0x193>;
|
phandle = <0x31d>;
|
};
|
|
emmc-cmd {
|
rockchip,pins = <0x2 0x0 0x1 0x193>;
|
phandle = <0x31e>;
|
};
|
|
emmc-data-strobe {
|
rockchip,pins = <0x2 0x2 0x1 0x192>;
|
phandle = <0x31f>;
|
};
|
};
|
|
eth1 {
|
|
eth1-pins {
|
rockchip,pins = <0x3 0x6 0x1 0x192>;
|
phandle = <0x320>;
|
};
|
};
|
|
fspi {
|
|
fspim0-pins {
|
rockchip,pins = <0x2 0x0 0x2 0x193 0x2 0x1e 0x2 0x193 0x2 0x18 0x2 0x193 0x2 0x19 0x2 0x193 0x2 0x1a 0x2 0x193 0x2 0x1b 0x2 0x193>;
|
phandle = <0x321>;
|
};
|
|
fspim0-cs1 {
|
rockchip,pins = <0x2 0x1f 0x2 0x193>;
|
phandle = <0x322>;
|
};
|
|
fspim2-pins {
|
rockchip,pins = <0x3 0x5 0x5 0x193 0x3 0x14 0x2 0x193 0x3 0x0 0x5 0x193 0x3 0x1 0x5 0x193 0x3 0x2 0x5 0x193 0x3 0x3 0x5 0x193>;
|
phandle = <0x323>;
|
};
|
|
fspim2-cs1 {
|
rockchip,pins = <0x3 0x15 0x2 0x193>;
|
phandle = <0x324>;
|
};
|
|
fspim1-pins {
|
rockchip,pins = <0x2 0xb 0x3 0x193 0x2 0xc 0x3 0x193 0x2 0x6 0x3 0x193 0x2 0x7 0x3 0x193 0x2 0x8 0x3 0x193 0x2 0x9 0x3 0x193>;
|
phandle = <0x325>;
|
};
|
|
fspim1-cs1 {
|
rockchip,pins = <0x2 0xd 0x3 0x193>;
|
phandle = <0x326>;
|
};
|
};
|
|
gmac1 {
|
|
gmac1-miim {
|
rockchip,pins = <0x3 0x12 0x1 0x192 0x3 0x13 0x1 0x192>;
|
phandle = <0x10d>;
|
};
|
|
gmac1-clkinout {
|
rockchip,pins = <0x3 0xe 0x1 0x192>;
|
phandle = <0x327>;
|
};
|
|
gmac1-rx-bus2 {
|
rockchip,pins = <0x3 0x7 0x1 0x192 0x3 0x8 0x1 0x192 0x3 0x9 0x1 0x192>;
|
phandle = <0x10f>;
|
};
|
|
gmac1-tx-bus2 {
|
rockchip,pins = <0x3 0xb 0x1 0x192 0x3 0xc 0x1 0x192 0x3 0xd 0x1 0x192>;
|
phandle = <0x10e>;
|
};
|
|
gmac1-rgmii-clk {
|
rockchip,pins = <0x3 0x5 0x1 0x192 0x3 0x4 0x1 0x192>;
|
phandle = <0x110>;
|
};
|
|
gmac1-rgmii-bus {
|
rockchip,pins = <0x3 0x2 0x1 0x192 0x3 0x3 0x1 0x192 0x3 0x0 0x1 0x192 0x3 0x1 0x1 0x192>;
|
phandle = <0x111>;
|
};
|
|
gmac1-ppsclk {
|
rockchip,pins = <0x3 0x11 0x1 0x192>;
|
phandle = <0x328>;
|
};
|
|
gmac1-ppstrig {
|
rockchip,pins = <0x3 0x10 0x1 0x192>;
|
phandle = <0x329>;
|
};
|
|
gmac1-ptp-ref-clk {
|
rockchip,pins = <0x3 0xf 0x1 0x192>;
|
phandle = <0x32a>;
|
};
|
|
gmac1-txer {
|
rockchip,pins = <0x3 0xa 0x1 0x192>;
|
phandle = <0x32b>;
|
};
|
};
|
|
gpu {
|
|
gpu-pins {
|
rockchip,pins = <0x0 0x15 0x2 0x192>;
|
phandle = <0x32c>;
|
};
|
};
|
|
hdmi {
|
|
hdmim0-rx-cec {
|
rockchip,pins = <0x4 0xd 0x5 0x192>;
|
phandle = <0x32d>;
|
};
|
|
hdmim0-rx-hpdin {
|
rockchip,pins = <0x4 0xe 0x5 0x192>;
|
phandle = <0x32e>;
|
};
|
|
hdmim0-rx-scl {
|
rockchip,pins = <0x0 0x1a 0xb 0x192>;
|
phandle = <0x32f>;
|
};
|
|
hdmim0-rx-sda {
|
rockchip,pins = <0x0 0x19 0xb 0x192>;
|
phandle = <0x330>;
|
};
|
|
hdmim0-tx0-cec {
|
rockchip,pins = <0x4 0x11 0x5 0x192>;
|
phandle = <0xf7>;
|
};
|
|
hdmim0-tx0-hpd {
|
rockchip,pins = <0x1 0x5 0x5 0x192>;
|
phandle = <0xf8>;
|
};
|
|
hdmim0-tx0-scl {
|
rockchip,pins = <0x4 0xf 0x5 0x194>;
|
phandle = <0xf9>;
|
};
|
|
hdmim0-tx0-sda {
|
rockchip,pins = <0x4 0x10 0x5 0x195>;
|
phandle = <0xfa>;
|
};
|
|
hdmim0-tx1-hpd {
|
rockchip,pins = <0x1 0x6 0x5 0x192>;
|
phandle = <0x1a6>;
|
};
|
|
hdmim1-rx {
|
rockchip,pins = <0x3 0x19 0x5 0x192 0x3 0x1a 0x5 0x196 0x3 0x1b 0x5 0x196 0x3 0x1c 0x5 0x192>;
|
phandle = <0x1b0>;
|
};
|
|
hdmim1-rx-cec {
|
rockchip,pins = <0x3 0x19 0x5 0x192>;
|
phandle = <0x331>;
|
};
|
|
hdmim1-rx-hpdin {
|
rockchip,pins = <0x3 0x1c 0x5 0x192>;
|
phandle = <0x332>;
|
};
|
|
hdmim1-rx-scl {
|
rockchip,pins = <0x3 0x1a 0x5 0x196>;
|
phandle = <0x333>;
|
};
|
|
hdmim1-rx-sda {
|
rockchip,pins = <0x3 0x1b 0x5 0x196>;
|
phandle = <0x334>;
|
};
|
|
hdmim1-tx0-cec {
|
rockchip,pins = <0x0 0x19 0xd 0x192>;
|
phandle = <0x335>;
|
};
|
|
hdmim1-tx0-hpd {
|
rockchip,pins = <0x3 0x1c 0x3 0x192>;
|
phandle = <0x336>;
|
};
|
|
hdmim1-tx0-scl {
|
rockchip,pins = <0x0 0x1d 0xb 0x194>;
|
phandle = <0x337>;
|
};
|
|
hdmim1-tx0-sda {
|
rockchip,pins = <0x0 0x1c 0xb 0x195>;
|
phandle = <0x338>;
|
};
|
|
hdmim1-tx1-cec {
|
rockchip,pins = <0x0 0x1a 0xd 0x192>;
|
phandle = <0x339>;
|
};
|
|
hdmim1-tx1-hpd {
|
rockchip,pins = <0x3 0xf 0x5 0x192>;
|
phandle = <0x33a>;
|
};
|
|
hdmim1-tx1-scl {
|
rockchip,pins = <0x3 0x16 0x5 0x194>;
|
phandle = <0x1a7>;
|
};
|
|
hdmim1-tx1-sda {
|
rockchip,pins = <0x3 0x15 0x5 0x195>;
|
phandle = <0x1a8>;
|
};
|
|
hdmim2-rx-cec {
|
rockchip,pins = <0x1 0xf 0x5 0x192>;
|
phandle = <0x33b>;
|
};
|
|
hdmim2-rx-hpdin {
|
rockchip,pins = <0x1 0xe 0x5 0x192>;
|
phandle = <0x33c>;
|
};
|
|
hdmim2-rx-scl {
|
rockchip,pins = <0x1 0x1e 0x5 0x192>;
|
phandle = <0x33d>;
|
};
|
|
hdmim2-rx-sda {
|
rockchip,pins = <0x1 0x1f 0x5 0x192>;
|
phandle = <0x33e>;
|
};
|
|
hdmim2-tx0-scl {
|
rockchip,pins = <0x3 0x17 0x5 0x194>;
|
phandle = <0x33f>;
|
};
|
|
hdmim2-tx0-sda {
|
rockchip,pins = <0x3 0x18 0x5 0x195>;
|
phandle = <0x340>;
|
};
|
|
hdmim2-tx1-cec {
|
rockchip,pins = <0x3 0x14 0x5 0x192>;
|
phandle = <0x1a5>;
|
};
|
|
hdmim2-tx1-scl {
|
rockchip,pins = <0x1 0x4 0x5 0x194>;
|
phandle = <0x341>;
|
};
|
|
hdmim2-tx1-sda {
|
rockchip,pins = <0x1 0x3 0x5 0x195>;
|
phandle = <0x342>;
|
};
|
|
hdmi-debug0 {
|
rockchip,pins = <0x1 0x7 0x7 0x192>;
|
phandle = <0x343>;
|
};
|
|
hdmi-debug1 {
|
rockchip,pins = <0x1 0x8 0x7 0x192>;
|
phandle = <0x344>;
|
};
|
|
hdmi-debug2 {
|
rockchip,pins = <0x1 0x9 0x7 0x192>;
|
phandle = <0x345>;
|
};
|
|
hdmi-debug3 {
|
rockchip,pins = <0x1 0xa 0x7 0x192>;
|
phandle = <0x346>;
|
};
|
|
hdmi-debug4 {
|
rockchip,pins = <0x1 0xb 0x7 0x192>;
|
phandle = <0x347>;
|
};
|
|
hdmi-debug5 {
|
rockchip,pins = <0x1 0xc 0x7 0x192>;
|
phandle = <0x348>;
|
};
|
|
hdmi-debug6 {
|
rockchip,pins = <0x1 0x0 0x7 0x192>;
|
phandle = <0x349>;
|
};
|
|
hdmim0-tx1-cec {
|
rockchip,pins = <0x2 0x14 0x4 0x192>;
|
phandle = <0x34a>;
|
};
|
|
hdmim0-tx1-scl {
|
rockchip,pins = <0x2 0xd 0x4 0x192>;
|
phandle = <0x34b>;
|
};
|
|
hdmim0-tx1-sda {
|
rockchip,pins = <0x2 0xc 0x4 0x192>;
|
phandle = <0x34c>;
|
};
|
|
hdmirx-det {
|
rockchip,pins = <0x1 0xe 0x0 0x197>;
|
phandle = <0x1b1>;
|
};
|
};
|
|
i2c0 {
|
|
i2c0m0-xfer {
|
rockchip,pins = <0x0 0xb 0x2 0x196 0x0 0x6 0x2 0x196>;
|
phandle = <0x34d>;
|
};
|
|
i2c0m2-xfer {
|
rockchip,pins = <0x0 0x19 0x3 0x196 0x0 0x1a 0x3 0x196>;
|
phandle = <0x6d>;
|
};
|
|
i2c0m1-xfer {
|
rockchip,pins = <0x4 0x15 0x9 0x196 0x4 0x16 0x9 0x196>;
|
phandle = <0x34e>;
|
};
|
};
|
|
i2c1 {
|
|
i2c1m0-xfer {
|
rockchip,pins = <0x0 0xd 0x9 0x196 0x0 0xe 0x9 0x196>;
|
phandle = <0x34f>;
|
};
|
|
i2c1m1-xfer {
|
rockchip,pins = <0x0 0x8 0x2 0x196 0x0 0x9 0x2 0x196>;
|
phandle = <0x350>;
|
};
|
|
i2c1m2-xfer {
|
rockchip,pins = <0x0 0x1c 0x9 0x196 0x0 0x1d 0x9 0x196>;
|
phandle = <0x14b>;
|
};
|
|
i2c1m3-xfer {
|
rockchip,pins = <0x2 0x1c 0x9 0x196 0x2 0x1d 0x9 0x196>;
|
phandle = <0x351>;
|
};
|
|
i2c1m4-xfer {
|
rockchip,pins = <0x1 0x1a 0x9 0x196 0x1 0x1b 0x9 0x196>;
|
phandle = <0x352>;
|
};
|
};
|
|
i2c2 {
|
|
i2c2m0-xfer {
|
rockchip,pins = <0x0 0xf 0x9 0x196 0x0 0x10 0x9 0x196>;
|
phandle = <0x14c>;
|
};
|
|
i2c2m2-xfer {
|
rockchip,pins = <0x2 0x3 0x9 0x196 0x2 0x2 0x9 0x196>;
|
phandle = <0x353>;
|
};
|
|
i2c2m3-xfer {
|
rockchip,pins = <0x1 0x15 0x9 0x196 0x1 0x14 0x9 0x196>;
|
phandle = <0x354>;
|
};
|
|
i2c2m4-xfer {
|
rockchip,pins = <0x1 0x1 0x9 0x196 0x1 0x0 0x9 0x196>;
|
phandle = <0x355>;
|
};
|
|
i2c2m1-xfer {
|
rockchip,pins = <0x2 0x11 0x9 0x196 0x2 0x10 0x9 0x196>;
|
phandle = <0x356>;
|
};
|
};
|
|
i2c3 {
|
|
i2c3m0-xfer {
|
rockchip,pins = <0x1 0x11 0x9 0x196 0x1 0x10 0x9 0x196>;
|
phandle = <0x14d>;
|
};
|
|
i2c3m1-xfer {
|
rockchip,pins = <0x3 0xf 0x9 0x196 0x3 0x10 0x9 0x196>;
|
phandle = <0x357>;
|
};
|
|
i2c3m2-xfer {
|
rockchip,pins = <0x4 0x4 0x9 0x196 0x4 0x5 0x9 0x196>;
|
phandle = <0x358>;
|
};
|
|
i2c3m4-xfer {
|
rockchip,pins = <0x4 0x18 0x9 0x196 0x4 0x19 0x9 0x196>;
|
phandle = <0x359>;
|
};
|
|
i2c3m3-xfer {
|
rockchip,pins = <0x2 0xa 0x9 0x196 0x2 0xb 0x9 0x196>;
|
phandle = <0x35a>;
|
};
|
};
|
|
i2c4 {
|
|
i2c4m0-xfer {
|
rockchip,pins = <0x3 0x6 0x9 0x196 0x3 0x5 0x9 0x196>;
|
phandle = <0x35b>;
|
};
|
|
i2c4m2-xfer {
|
rockchip,pins = <0x0 0x15 0x9 0x196 0x0 0x14 0x9 0x196>;
|
phandle = <0x35c>;
|
};
|
|
i2c4m3-xfer {
|
rockchip,pins = <0x1 0x3 0x9 0x196 0x1 0x2 0x9 0x196>;
|
phandle = <0x35d>;
|
};
|
|
i2c4m4-xfer {
|
rockchip,pins = <0x1 0x17 0x9 0x196 0x1 0x16 0x9 0x196>;
|
phandle = <0x35e>;
|
};
|
|
i2c4m1-xfer {
|
rockchip,pins = <0x2 0xd 0x9 0x196 0x2 0xc 0x9 0x196>;
|
phandle = <0x150>;
|
};
|
};
|
|
i2c5 {
|
|
i2c5m0-xfer {
|
rockchip,pins = <0x3 0x17 0x9 0x196 0x3 0x18 0x9 0x196>;
|
phandle = <0x151>;
|
};
|
|
i2c5m1-xfer {
|
rockchip,pins = <0x4 0xe 0x9 0x196 0x4 0xf 0x9 0x196>;
|
phandle = <0x35f>;
|
};
|
|
i2c5m2-xfer {
|
rockchip,pins = <0x4 0x6 0x9 0x196 0x4 0x7 0x9 0x196>;
|
phandle = <0x360>;
|
};
|
|
i2c5m3-xfer {
|
rockchip,pins = <0x1 0xe 0x9 0x196 0x1 0xf 0x9 0x196>;
|
phandle = <0x361>;
|
};
|
|
i2c5m4-xfer {
|
rockchip,pins = <0x2 0xe 0x9 0x196 0x2 0xf 0x9 0x196>;
|
phandle = <0x362>;
|
};
|
};
|
|
i2c6 {
|
|
i2c6m0-xfer {
|
rockchip,pins = <0x0 0x18 0x9 0x196 0x0 0x17 0x9 0x196>;
|
phandle = <0x17f>;
|
};
|
|
i2c6m1-xfer {
|
rockchip,pins = <0x1 0x13 0x9 0x196 0x1 0x12 0x9 0x196>;
|
phandle = <0x363>;
|
};
|
|
i2c6m3-xfer {
|
rockchip,pins = <0x4 0x9 0x9 0x196 0x4 0x8 0x9 0x196>;
|
phandle = <0x364>;
|
};
|
|
i2c6m4-xfer {
|
rockchip,pins = <0x3 0x1 0x9 0x196 0x3 0x0 0x9 0x196>;
|
phandle = <0x365>;
|
};
|
|
i2c6m2-xfer {
|
rockchip,pins = <0x2 0x13 0x9 0x196 0x2 0x12 0x9 0x196>;
|
phandle = <0x366>;
|
};
|
};
|
|
i2c7 {
|
|
i2c7m0-xfer {
|
rockchip,pins = <0x1 0x18 0x9 0x196 0x1 0x19 0x9 0x196>;
|
phandle = <0x181>;
|
};
|
|
i2c7m2-xfer {
|
rockchip,pins = <0x3 0x1a 0x9 0x196 0x3 0x1b 0x9 0x196>;
|
phandle = <0x367>;
|
};
|
|
i2c7m3-xfer {
|
rockchip,pins = <0x4 0xa 0x9 0x196 0x4 0xb 0x9 0x196>;
|
phandle = <0x368>;
|
};
|
|
i2c7m1-xfer {
|
rockchip,pins = <0x4 0x13 0x9 0x196 0x4 0x14 0x9 0x196>;
|
phandle = <0x369>;
|
};
|
};
|
|
i2c8 {
|
|
i2c8m0-xfer {
|
rockchip,pins = <0x4 0x1a 0x9 0x196 0x4 0x1b 0x9 0x196>;
|
phandle = <0x182>;
|
};
|
|
i2c8m2-xfer {
|
rockchip,pins = <0x1 0x1e 0x9 0x196 0x1 0x1f 0x9 0x196>;
|
phandle = <0x36a>;
|
};
|
|
i2c8m3-xfer {
|
rockchip,pins = <0x4 0x10 0x9 0x196 0x4 0x11 0x9 0x196>;
|
phandle = <0x36b>;
|
};
|
|
i2c8m4-xfer {
|
rockchip,pins = <0x3 0x12 0x9 0x196 0x3 0x13 0x9 0x196>;
|
phandle = <0x36c>;
|
};
|
|
i2c8m1-xfer {
|
rockchip,pins = <0x2 0x8 0x9 0x196 0x2 0x9 0x9 0x196>;
|
phandle = <0x36d>;
|
};
|
};
|
|
i2s0 {
|
|
i2s0-idle {
|
rockchip,pins = <0x1 0x15 0x0 0x192 0x1 0x13 0x0 0x192>;
|
phandle = <0x120>;
|
};
|
|
i2s0-lrck {
|
rockchip,pins = <0x1 0x15 0x1 0x196>;
|
phandle = <0x11c>;
|
};
|
|
i2s0-mclk {
|
rockchip,pins = <0x1 0x12 0x1 0x196>;
|
phandle = <0x14f>;
|
};
|
|
i2s0-sclk {
|
rockchip,pins = <0x1 0x13 0x1 0x196>;
|
phandle = <0x11d>;
|
};
|
|
i2s0-sdi0 {
|
rockchip,pins = <0x1 0x1c 0x2 0x192>;
|
phandle = <0x11e>;
|
};
|
|
i2s0-sdi1 {
|
rockchip,pins = <0x1 0x1b 0x2 0x192>;
|
phandle = <0x36e>;
|
};
|
|
i2s0-sdi2 {
|
rockchip,pins = <0x1 0x1a 0x2 0x192>;
|
phandle = <0x36f>;
|
};
|
|
i2s0-sdi3 {
|
rockchip,pins = <0x1 0x19 0x2 0x192>;
|
phandle = <0x370>;
|
};
|
|
i2s0-sdo0 {
|
rockchip,pins = <0x1 0x17 0x1 0x192>;
|
phandle = <0x11f>;
|
};
|
|
i2s0-sdo1 {
|
rockchip,pins = <0x1 0x18 0x1 0x192>;
|
phandle = <0x371>;
|
};
|
|
i2s0-sdo2 {
|
rockchip,pins = <0x1 0x19 0x1 0x192>;
|
phandle = <0x372>;
|
};
|
|
i2s0-sdo3 {
|
rockchip,pins = <0x1 0x1a 0x1 0x192>;
|
phandle = <0x373>;
|
};
|
};
|
|
i2s1 {
|
|
i2s1m0-lrck {
|
rockchip,pins = <0x4 0x2 0x3 0x196>;
|
phandle = <0x121>;
|
};
|
|
i2s1m0-mclk {
|
rockchip,pins = <0x4 0x0 0x3 0x196>;
|
phandle = <0x374>;
|
};
|
|
i2s1m0-sclk {
|
rockchip,pins = <0x4 0x1 0x3 0x196>;
|
phandle = <0x122>;
|
};
|
|
i2s1m0-sdi0 {
|
rockchip,pins = <0x4 0x5 0x3 0x192>;
|
phandle = <0x123>;
|
};
|
|
i2s1m0-sdi1 {
|
rockchip,pins = <0x4 0x6 0x3 0x192>;
|
phandle = <0x124>;
|
};
|
|
i2s1m0-sdi2 {
|
rockchip,pins = <0x4 0x7 0x3 0x192>;
|
phandle = <0x125>;
|
};
|
|
i2s1m0-sdi3 {
|
rockchip,pins = <0x4 0x8 0x3 0x192>;
|
phandle = <0x126>;
|
};
|
|
i2s1m0-sdo0 {
|
rockchip,pins = <0x4 0x9 0x3 0x192>;
|
phandle = <0x127>;
|
};
|
|
i2s1m0-sdo1 {
|
rockchip,pins = <0x4 0xa 0x3 0x192>;
|
phandle = <0x128>;
|
};
|
|
i2s1m0-sdo2 {
|
rockchip,pins = <0x4 0xb 0x3 0x192>;
|
phandle = <0x129>;
|
};
|
|
i2s1m0-sdo3 {
|
rockchip,pins = <0x4 0xc 0x3 0x192>;
|
phandle = <0x12a>;
|
};
|
|
i2s1m1-lrck {
|
rockchip,pins = <0x0 0xf 0x1 0x196>;
|
phandle = <0x375>;
|
};
|
|
i2s1m1-mclk {
|
rockchip,pins = <0x0 0xd 0x1 0x196>;
|
phandle = <0x376>;
|
};
|
|
i2s1m1-sclk {
|
rockchip,pins = <0x0 0xe 0x1 0x196>;
|
phandle = <0x377>;
|
};
|
|
i2s1m1-sdi0 {
|
rockchip,pins = <0x0 0x15 0x1 0x192>;
|
phandle = <0x378>;
|
};
|
|
i2s1m1-sdi1 {
|
rockchip,pins = <0x0 0x16 0x1 0x192>;
|
phandle = <0x379>;
|
};
|
|
i2s1m1-sdi2 {
|
rockchip,pins = <0x0 0x17 0x1 0x192>;
|
phandle = <0x37a>;
|
};
|
|
i2s1m1-sdi3 {
|
rockchip,pins = <0x0 0x18 0x1 0x192>;
|
phandle = <0x37b>;
|
};
|
|
i2s1m1-sdo0 {
|
rockchip,pins = <0x0 0x19 0x1 0x192>;
|
phandle = <0x37c>;
|
};
|
|
i2s1m1-sdo1 {
|
rockchip,pins = <0x0 0x1a 0x1 0x192>;
|
phandle = <0x37d>;
|
};
|
|
i2s1m1-sdo2 {
|
rockchip,pins = <0x0 0x1c 0x1 0x192>;
|
phandle = <0x37e>;
|
};
|
|
i2s1m1-sdo3 {
|
rockchip,pins = <0x0 0x1d 0x1 0x192>;
|
phandle = <0x37f>;
|
};
|
};
|
|
i2s2 {
|
|
i2s2m1-idle {
|
rockchip,pins = <0x3 0xe 0x0 0x192 0x3 0xd 0x0 0x192>;
|
phandle = <0x12f>;
|
};
|
|
i2s2m1-lrck {
|
rockchip,pins = <0x3 0xe 0x3 0x196>;
|
phandle = <0x130>;
|
};
|
|
i2s2m1-mclk {
|
rockchip,pins = <0x3 0xc 0x3 0x196>;
|
phandle = <0x380>;
|
};
|
|
i2s2m1-sclk {
|
rockchip,pins = <0x3 0xd 0x3 0x196>;
|
phandle = <0x131>;
|
};
|
|
i2s2m1-sdi {
|
rockchip,pins = <0x3 0xa 0x3 0x192>;
|
phandle = <0x381>;
|
};
|
|
i2s2m1-sdo {
|
rockchip,pins = <0x3 0xb 0x3 0x192>;
|
phandle = <0x382>;
|
};
|
|
i2s2m0-idle {
|
rockchip,pins = <0x2 0x10 0x0 0x192 0x2 0xf 0x0 0x192>;
|
phandle = <0x383>;
|
};
|
|
i2s2m0-lrck {
|
rockchip,pins = <0x2 0x10 0x2 0x196>;
|
phandle = <0x12c>;
|
};
|
|
i2s2m0-mclk {
|
rockchip,pins = <0x2 0xe 0x2 0x196>;
|
phandle = <0x384>;
|
};
|
|
i2s2m0-sclk {
|
rockchip,pins = <0x2 0xf 0x2 0x196>;
|
phandle = <0x12b>;
|
};
|
|
i2s2m0-sdi {
|
rockchip,pins = <0x2 0x13 0x2 0x192>;
|
phandle = <0x12d>;
|
};
|
|
i2s2m0-sdo {
|
rockchip,pins = <0x4 0x13 0x2 0x192>;
|
phandle = <0x12e>;
|
};
|
};
|
|
i2s3 {
|
|
i2s3-idle {
|
rockchip,pins = <0x3 0x2 0x0 0x192 0x3 0x1 0x0 0x192>;
|
phandle = <0x134>;
|
};
|
|
i2s3-lrck {
|
rockchip,pins = <0x3 0x2 0x3 0x196>;
|
phandle = <0x135>;
|
};
|
|
i2s3-mclk {
|
rockchip,pins = <0x3 0x0 0x3 0x196>;
|
phandle = <0x385>;
|
};
|
|
i2s3-sclk {
|
rockchip,pins = <0x3 0x1 0x3 0x196>;
|
phandle = <0x136>;
|
};
|
|
i2s3-sdi {
|
rockchip,pins = <0x3 0x4 0x3 0x192>;
|
phandle = <0x132>;
|
};
|
|
i2s3-sdo {
|
rockchip,pins = <0x3 0x3 0x3 0x192>;
|
phandle = <0x133>;
|
};
|
};
|
|
jtag {
|
|
jtagm0-pins {
|
rockchip,pins = <0x4 0x1a 0x5 0x192 0x4 0x1b 0x5 0x192>;
|
phandle = <0x386>;
|
};
|
|
jtagm1-pins {
|
rockchip,pins = <0x4 0x18 0x5 0x192 0x4 0x19 0x5 0x192>;
|
phandle = <0x387>;
|
};
|
|
jtagm2-pins {
|
rockchip,pins = <0x0 0xd 0x2 0x192 0x0 0xe 0x2 0x192>;
|
phandle = <0x388>;
|
};
|
};
|
|
litcpu {
|
|
litcpu-pins {
|
rockchip,pins = <0x0 0x1b 0x1 0x192>;
|
phandle = <0x389>;
|
};
|
};
|
|
mcu {
|
|
mcum0-pins {
|
rockchip,pins = <0x4 0x1c 0x5 0x192 0x4 0x1d 0x5 0x192>;
|
phandle = <0x38a>;
|
};
|
|
mcum1-pins {
|
rockchip,pins = <0x3 0x1c 0x6 0x192 0x3 0x1d 0x6 0x192>;
|
phandle = <0x38b>;
|
};
|
};
|
|
mipi {
|
|
mipim0-camera0-clk {
|
rockchip,pins = <0x4 0x9 0x1 0x192>;
|
phandle = <0x38c>;
|
};
|
|
mipim0-camera1-clk {
|
rockchip,pins = <0x1 0xe 0x2 0x192>;
|
phandle = <0x38d>;
|
};
|
|
mipim0-camera2-clk {
|
rockchip,pins = <0x1 0xf 0x2 0x192>;
|
phandle = <0x38e>;
|
};
|
|
mipim0-camera3-clk {
|
rockchip,pins = <0x1 0x1e 0x2 0x192>;
|
phandle = <0x38f>;
|
};
|
|
mipim0-camera4-clk {
|
rockchip,pins = <0x1 0x1f 0x2 0x192>;
|
phandle = <0x390>;
|
};
|
|
mipim1-camera0-clk {
|
rockchip,pins = <0x3 0x5 0x4 0x192>;
|
phandle = <0x391>;
|
};
|
|
mipim1-camera1-clk {
|
rockchip,pins = <0x3 0x6 0x4 0x192>;
|
phandle = <0x392>;
|
};
|
|
mipim1-camera2-clk {
|
rockchip,pins = <0x3 0x7 0x4 0x192>;
|
phandle = <0x393>;
|
};
|
|
mipim1-camera3-clk {
|
rockchip,pins = <0x3 0x8 0x4 0x192>;
|
phandle = <0x394>;
|
};
|
|
mipim1-camera4-clk {
|
rockchip,pins = <0x3 0x9 0x4 0x192>;
|
phandle = <0x395>;
|
};
|
|
mipi-te0 {
|
rockchip,pins = <0x3 0x12 0x2 0x192>;
|
phandle = <0x396>;
|
};
|
|
mipi-te1 {
|
rockchip,pins = <0x3 0x13 0x2 0x192>;
|
phandle = <0x397>;
|
};
|
};
|
|
npu {
|
|
npu-pins {
|
rockchip,pins = <0x0 0x16 0x2 0x192>;
|
phandle = <0x398>;
|
};
|
};
|
|
pcie20x1 {
|
|
pcie20x1m0-pins {
|
rockchip,pins = <0x3 0x17 0x4 0x192 0x3 0x19 0x4 0x192 0x3 0x18 0x4 0x192>;
|
phandle = <0x399>;
|
};
|
|
pcie20x1m1-pins {
|
rockchip,pins = <0x4 0xf 0x4 0x192 0x4 0x11 0x4 0x192 0x4 0x10 0x4 0x192>;
|
phandle = <0x39a>;
|
};
|
|
pcie20x1-2-button-rstn {
|
rockchip,pins = <0x4 0xb 0x4 0x192>;
|
phandle = <0x39b>;
|
};
|
};
|
|
pcie30phy {
|
|
pcie30phy-pins {
|
rockchip,pins = <0x1 0x14 0x4 0x192 0x1 0x19 0x4 0x192>;
|
phandle = <0x39c>;
|
};
|
};
|
|
pcie30x1 {
|
|
pcie30x1m0-pins {
|
rockchip,pins = <0x0 0x10 0xc 0x192 0x0 0x15 0xc 0x192 0x0 0x14 0xc 0x192 0x0 0xd 0xc 0x192 0x0 0xf 0xc 0x192 0x0 0xe 0xc 0x192>;
|
phandle = <0x39d>;
|
};
|
|
pcie30x1m1-pins {
|
rockchip,pins = <0x4 0x3 0x4 0x192 0x4 0x5 0x4 0x192 0x4 0x4 0x4 0x192 0x4 0x0 0x4 0x192 0x4 0x2 0x4 0x192 0x4 0x1 0x4 0x192>;
|
phandle = <0x39e>;
|
};
|
|
pcie30x1m2-pins {
|
rockchip,pins = <0x1 0xd 0x4 0x192 0x1 0xc 0x4 0x192 0x1 0xb 0x4 0x192 0x1 0x0 0x4 0x192 0x1 0x7 0x4 0x192 0x1 0x1 0x4 0x192>;
|
phandle = <0x39f>;
|
};
|
|
pcie30x1-0-button-rstn {
|
rockchip,pins = <0x4 0x9 0x4 0x192>;
|
phandle = <0x3a0>;
|
};
|
|
pcie30x1-1-button-rstn {
|
rockchip,pins = <0x4 0xa 0x4 0x192>;
|
phandle = <0x3a1>;
|
};
|
};
|
|
pcie30x2 {
|
|
pcie30x2m0-pins {
|
rockchip,pins = <0x0 0x19 0xc 0x192 0x0 0x1c 0xc 0x192 0x0 0x1a 0xc 0x192>;
|
phandle = <0x3a2>;
|
};
|
|
pcie30x2m1-pins {
|
rockchip,pins = <0x4 0x6 0x4 0x192 0x4 0x8 0x4 0x192 0x4 0x7 0x4 0x192>;
|
phandle = <0x3a3>;
|
};
|
|
pcie30x2m2-pins {
|
rockchip,pins = <0x3 0x1a 0x4 0x192 0x3 0x1c 0x4 0x192 0x3 0x1b 0x4 0x192>;
|
phandle = <0x3a4>;
|
};
|
|
pcie30x2m3-pins {
|
rockchip,pins = <0x1 0x1f 0x4 0x192 0x1 0xf 0x4 0x192 0x1 0xe 0x4 0x192>;
|
phandle = <0x3a5>;
|
};
|
|
pcie30x2-button-rstn {
|
rockchip,pins = <0x3 0x11 0x4 0x192>;
|
phandle = <0x3a6>;
|
};
|
};
|
|
pcie30x4 {
|
|
pcie30x4m0-pins {
|
rockchip,pins = <0x0 0x16 0xc 0x192 0x0 0x18 0xc 0x192 0x0 0x17 0xc 0x192>;
|
phandle = <0x3a7>;
|
};
|
|
pcie30x4m1-pins {
|
rockchip,pins = <0x4 0xc 0x4 0x192 0x4 0xe 0x4 0x192 0x4 0xd 0x4 0x192>;
|
phandle = <0x3a8>;
|
};
|
|
pcie30x4m2-pins {
|
rockchip,pins = <0x3 0x14 0x4 0x192 0x3 0x16 0x4 0x192 0x3 0x15 0x4 0x192>;
|
phandle = <0x3a9>;
|
};
|
|
pcie30x4m3-pins {
|
rockchip,pins = <0x1 0x8 0x4 0x192 0x1 0xa 0x4 0x192 0x1 0x9 0x4 0x192>;
|
phandle = <0x3aa>;
|
};
|
|
pcie30x4-button-rstn {
|
rockchip,pins = <0x3 0x1d 0x4 0x192>;
|
phandle = <0x3ab>;
|
};
|
|
pcie30x4-clkreqn-m1 {
|
rockchip,pins = <0x4 0xc 0x0 0x198>;
|
phandle = <0x1b6>;
|
};
|
};
|
|
pdm0 {
|
|
pdm0m0-clk {
|
rockchip,pins = <0x1 0x16 0x3 0x192>;
|
phandle = <0x13c>;
|
};
|
|
pdm0m0-clk1 {
|
rockchip,pins = <0x1 0x14 0x3 0x192>;
|
phandle = <0x13d>;
|
};
|
|
pdm0m0-idle {
|
rockchip,pins = <0x1 0x16 0x0 0x192 0x1 0x14 0x0 0x192>;
|
phandle = <0x13b>;
|
};
|
|
pdm0m0-sdi0 {
|
rockchip,pins = <0x1 0x1d 0x3 0x192>;
|
phandle = <0x137>;
|
};
|
|
pdm0m0-sdi1 {
|
rockchip,pins = <0x1 0x19 0x3 0x192>;
|
phandle = <0x138>;
|
};
|
|
pdm0m0-sdi2 {
|
rockchip,pins = <0x1 0x1a 0x3 0x192>;
|
phandle = <0x139>;
|
};
|
|
pdm0m0-sdi3 {
|
rockchip,pins = <0x1 0x1b 0x3 0x192>;
|
phandle = <0x13a>;
|
};
|
|
pdm0m1-clk {
|
rockchip,pins = <0x0 0x10 0x2 0x192>;
|
phandle = <0x3ac>;
|
};
|
|
pdm0m1-clk1 {
|
rockchip,pins = <0x0 0x14 0x2 0x192>;
|
phandle = <0x3ad>;
|
};
|
|
pdm0m1-idle {
|
rockchip,pins = <0x0 0x10 0x0 0x192 0x0 0x14 0x0 0x192>;
|
phandle = <0x3ae>;
|
};
|
|
pdm0m1-sdi0 {
|
rockchip,pins = <0x0 0x17 0x2 0x192>;
|
phandle = <0x3af>;
|
};
|
|
pdm0m1-sdi1 {
|
rockchip,pins = <0x0 0x18 0x2 0x192>;
|
phandle = <0x3b0>;
|
};
|
|
pdm0m1-sdi2 {
|
rockchip,pins = <0x0 0x1c 0x2 0x192>;
|
phandle = <0x3b1>;
|
};
|
|
pdm0m1-sdi3 {
|
rockchip,pins = <0x0 0x1e 0x2 0x192>;
|
phandle = <0x3b2>;
|
};
|
};
|
|
pdm1 {
|
|
pdm1m0-clk {
|
rockchip,pins = <0x4 0x1d 0x2 0x192>;
|
phandle = <0x143>;
|
};
|
|
pdm1m0-clk1 {
|
rockchip,pins = <0x4 0x1c 0x2 0x192>;
|
phandle = <0x144>;
|
};
|
|
pdm1m0-idle {
|
rockchip,pins = <0x4 0x1d 0x0 0x192 0x4 0x1c 0x0 0x192>;
|
phandle = <0x142>;
|
};
|
|
pdm1m0-sdi0 {
|
rockchip,pins = <0x4 0x1b 0x2 0x192>;
|
phandle = <0x13e>;
|
};
|
|
pdm1m0-sdi1 {
|
rockchip,pins = <0x4 0x1a 0x2 0x192>;
|
phandle = <0x13f>;
|
};
|
|
pdm1m0-sdi2 {
|
rockchip,pins = <0x4 0x19 0x2 0x192>;
|
phandle = <0x140>;
|
};
|
|
pdm1m0-sdi3 {
|
rockchip,pins = <0x4 0x18 0x2 0x192>;
|
phandle = <0x141>;
|
};
|
|
pdm1m1-clk {
|
rockchip,pins = <0x1 0xc 0x2 0x192>;
|
phandle = <0x3b3>;
|
};
|
|
pdm1m1-clk1 {
|
rockchip,pins = <0x1 0xb 0x2 0x192>;
|
phandle = <0x3b4>;
|
};
|
|
pdm1m1-idle {
|
rockchip,pins = <0x1 0xc 0x0 0x192 0x1 0xb 0x0 0x192>;
|
phandle = <0x3b5>;
|
};
|
|
pdm1m1-sdi0 {
|
rockchip,pins = <0x1 0x7 0x2 0x192>;
|
phandle = <0x3b6>;
|
};
|
|
pdm1m1-sdi1 {
|
rockchip,pins = <0x1 0x8 0x2 0x192>;
|
phandle = <0x3b7>;
|
};
|
|
pdm1m1-sdi2 {
|
rockchip,pins = <0x1 0x9 0x2 0x192>;
|
phandle = <0x3b8>;
|
};
|
|
pdm1m1-sdi3 {
|
rockchip,pins = <0x1 0xa 0x2 0x192>;
|
phandle = <0x3b9>;
|
};
|
};
|
|
pmic {
|
|
pmic-pins {
|
rockchip,pins = <0x0 0x7 0x0 0x197 0x0 0x2 0x1 0x192 0x0 0x3 0x1 0x192 0x0 0x11 0x1 0x192 0x0 0x12 0x1 0x192 0x0 0x13 0x1 0x192 0x0 0x1e 0x1 0x192>;
|
phandle = <0x15c>;
|
};
|
};
|
|
pmu {
|
|
pmu-pins {
|
rockchip,pins = <0x0 0x5 0x3 0x192>;
|
phandle = <0x3ba>;
|
};
|
};
|
|
pwm0 {
|
|
pwm0m0-pins {
|
rockchip,pins = <0x0 0xf 0x3 0x192>;
|
phandle = <0x71>;
|
};
|
|
pwm0m1-pins {
|
rockchip,pins = <0x1 0x1a 0xb 0x192>;
|
phandle = <0x3bb>;
|
};
|
|
pwm0m2-pins {
|
rockchip,pins = <0x1 0x2 0xb 0x192>;
|
phandle = <0x3bc>;
|
};
|
};
|
|
pwm1 {
|
|
pwm1m0-pins {
|
rockchip,pins = <0x0 0x10 0x3 0x192>;
|
phandle = <0x72>;
|
};
|
|
pwm1m1-pins {
|
rockchip,pins = <0x1 0x1b 0xb 0x192>;
|
phandle = <0x3bd>;
|
};
|
|
pwm1m2-pins {
|
rockchip,pins = <0x1 0x3 0xb 0x192>;
|
phandle = <0x3be>;
|
};
|
};
|
|
pwm2 {
|
|
pwm2m0-pins {
|
rockchip,pins = <0x0 0x14 0x3 0x192>;
|
phandle = <0x73>;
|
};
|
|
pwm2m1-pins {
|
rockchip,pins = <0x3 0x9 0xb 0x192>;
|
phandle = <0x3bf>;
|
};
|
|
pwm2m2-pins {
|
rockchip,pins = <0x4 0x12 0xb 0x192>;
|
phandle = <0x3c0>;
|
};
|
};
|
|
pwm3 {
|
|
pwm3m0-pins {
|
rockchip,pins = <0x0 0x1c 0x3 0x192>;
|
phandle = <0x3c1>;
|
};
|
|
pwm3m1-pins {
|
rockchip,pins = <0x3 0xa 0xb 0x192>;
|
phandle = <0x74>;
|
};
|
|
pwm3m2-pins {
|
rockchip,pins = <0x1 0x12 0xb 0x192>;
|
phandle = <0x3c2>;
|
};
|
|
pwm3m3-pins {
|
rockchip,pins = <0x1 0x7 0xb 0x192>;
|
phandle = <0x3c3>;
|
};
|
};
|
|
pwm4 {
|
|
pwm4m0-pins {
|
rockchip,pins = <0x0 0x15 0xb 0x192>;
|
phandle = <0x170>;
|
};
|
|
pwm4m1-pins {
|
rockchip,pins = <0x4 0x13 0xb 0x192>;
|
phandle = <0x3c4>;
|
};
|
};
|
|
pwm5 {
|
|
pwm5m0-pins {
|
rockchip,pins = <0x0 0x9 0x3 0x192>;
|
phandle = <0x171>;
|
};
|
|
pwm5m1-pins {
|
rockchip,pins = <0x0 0x16 0xb 0x192>;
|
phandle = <0x3c5>;
|
};
|
|
pwm5m2-pins {
|
rockchip,pins = <0x4 0x14 0xb 0x192>;
|
phandle = <0x3c6>;
|
};
|
};
|
|
pwm6 {
|
|
pwm6m0-pins {
|
rockchip,pins = <0x0 0x17 0xb 0x192>;
|
phandle = <0x172>;
|
};
|
|
pwm6m1-pins {
|
rockchip,pins = <0x4 0x11 0xb 0x192>;
|
phandle = <0x3c7>;
|
};
|
|
pwm6m2-pins {
|
rockchip,pins = <0x4 0x15 0xb 0x192>;
|
phandle = <0x3c8>;
|
};
|
};
|
|
pwm7 {
|
|
pwm7m0-pins {
|
rockchip,pins = <0x0 0x18 0xb 0x192>;
|
phandle = <0x173>;
|
};
|
|
pwm7m1-pins {
|
rockchip,pins = <0x4 0x1c 0xb 0x192>;
|
phandle = <0x3c9>;
|
};
|
|
pwm7m2-pins {
|
rockchip,pins = <0x1 0x13 0xb 0x192>;
|
phandle = <0x3ca>;
|
};
|
|
pwm7m3-pins {
|
rockchip,pins = <0x4 0x16 0xb 0x192>;
|
phandle = <0x3cb>;
|
};
|
};
|
|
pwm8 {
|
|
pwm8m0-pins {
|
rockchip,pins = <0x3 0x7 0xb 0x192>;
|
phandle = <0x174>;
|
};
|
|
pwm8m1-pins {
|
rockchip,pins = <0x4 0x18 0xb 0x192>;
|
phandle = <0x3cc>;
|
};
|
|
pwm8m2-pins {
|
rockchip,pins = <0x3 0x18 0xb 0x192>;
|
phandle = <0x3cd>;
|
};
|
};
|
|
pwm9 {
|
|
pwm9m0-pins {
|
rockchip,pins = <0x3 0x8 0xb 0x192>;
|
phandle = <0x175>;
|
};
|
|
pwm9m1-pins {
|
rockchip,pins = <0x4 0x19 0xb 0x192>;
|
phandle = <0x3ce>;
|
};
|
|
pwm9m2-pins {
|
rockchip,pins = <0x3 0x19 0xb 0x192>;
|
phandle = <0x3cf>;
|
};
|
};
|
|
pwm10 {
|
|
pwm10m0-pins {
|
rockchip,pins = <0x3 0x0 0xb 0x192>;
|
phandle = <0x3d0>;
|
};
|
|
pwm10m1-pins {
|
rockchip,pins = <0x4 0x1b 0xb 0x192>;
|
phandle = <0x3d1>;
|
};
|
|
pwm10m2-pins {
|
rockchip,pins = <0x3 0x1b 0xb 0x192>;
|
phandle = <0x176>;
|
};
|
};
|
|
pwm11 {
|
|
pwm11m0-pins {
|
rockchip,pins = <0x3 0x1 0xb 0x192>;
|
phandle = <0x3d2>;
|
};
|
|
pwm11m1-pins {
|
rockchip,pins = <0x4 0xc 0xb 0x192>;
|
phandle = <0x3d3>;
|
};
|
|
pwm11m2-pins {
|
rockchip,pins = <0x1 0x14 0xb 0x192>;
|
phandle = <0x3d4>;
|
};
|
|
pwm11m3-pins {
|
rockchip,pins = <0x3 0x1d 0xb 0x192>;
|
phandle = <0x177>;
|
};
|
};
|
|
pwm12 {
|
|
pwm12m0-pins {
|
rockchip,pins = <0x3 0xd 0xb 0x192>;
|
phandle = <0x178>;
|
};
|
|
pwm12m1-pins {
|
rockchip,pins = <0x4 0xd 0xb 0x192>;
|
phandle = <0x3d5>;
|
};
|
};
|
|
pwm13 {
|
|
pwm13m0-pins {
|
rockchip,pins = <0x3 0xe 0xb 0x192>;
|
phandle = <0x179>;
|
};
|
|
pwm13m1-pins {
|
rockchip,pins = <0x4 0xe 0xb 0x192>;
|
phandle = <0x3d6>;
|
};
|
|
pwm13m2-pins {
|
rockchip,pins = <0x1 0xf 0xb 0x192>;
|
phandle = <0x3d7>;
|
};
|
};
|
|
pwm14 {
|
|
pwm14m0-pins {
|
rockchip,pins = <0x3 0x12 0xb 0x192>;
|
phandle = <0x17a>;
|
};
|
|
pwm14m1-pins {
|
rockchip,pins = <0x4 0xa 0xb 0x192>;
|
phandle = <0x3d8>;
|
};
|
|
pwm14m2-pins {
|
rockchip,pins = <0x1 0x1e 0xb 0x192>;
|
phandle = <0x3d9>;
|
};
|
};
|
|
pwm15 {
|
|
pwm15m0-pins {
|
rockchip,pins = <0x3 0x13 0xb 0x192>;
|
phandle = <0x17b>;
|
};
|
|
pwm15m1-pins {
|
rockchip,pins = <0x4 0xb 0xb 0x192>;
|
phandle = <0x3da>;
|
};
|
|
pwm15m2-pins {
|
rockchip,pins = <0x1 0x16 0xb 0x192>;
|
phandle = <0x3db>;
|
};
|
|
pwm15m3-pins {
|
rockchip,pins = <0x1 0x1f 0xb 0x192>;
|
phandle = <0x3dc>;
|
};
|
};
|
|
refclk {
|
|
refclk-pins {
|
rockchip,pins = <0x0 0x0 0x1 0x192>;
|
phandle = <0x3dd>;
|
};
|
};
|
|
sata {
|
|
sata-pins {
|
rockchip,pins = <0x0 0x16 0xd 0x192 0x0 0x1c 0xd 0x192 0x0 0x1d 0xd 0x192>;
|
phandle = <0x3de>;
|
};
|
};
|
|
sata0 {
|
|
sata0m0-pins {
|
rockchip,pins = <0x4 0xe 0x6 0x192>;
|
phandle = <0x3df>;
|
};
|
|
sata0m1-pins {
|
rockchip,pins = <0x1 0xb 0x6 0x192>;
|
phandle = <0x3e0>;
|
};
|
};
|
|
sata1 {
|
|
sata1m0-pins {
|
rockchip,pins = <0x4 0xd 0x6 0x192>;
|
phandle = <0x3e1>;
|
};
|
|
sata1m1-pins {
|
rockchip,pins = <0x1 0x1 0x6 0x192>;
|
phandle = <0x3e2>;
|
};
|
};
|
|
sata2 {
|
|
sata2m0-pins {
|
rockchip,pins = <0x4 0x9 0x6 0x192>;
|
phandle = <0x3e3>;
|
};
|
|
sata2m1-pins {
|
rockchip,pins = <0x1 0xf 0x6 0x192>;
|
phandle = <0x3e4>;
|
};
|
};
|
|
sdio {
|
|
sdiom1-pins {
|
rockchip,pins = <0x3 0x5 0x2 0x192 0x3 0x4 0x2 0x197 0x3 0x0 0x2 0x197 0x3 0x1 0x2 0x197 0x3 0x2 0x2 0x197 0x3 0x3 0x2 0x197>;
|
phandle = <0x3e5>;
|
};
|
|
sdiom0-pins {
|
rockchip,pins = <0x2 0xb 0x2 0x192 0x2 0xa 0x2 0x197 0x2 0x6 0x2 0x197 0x2 0x7 0x2 0x197 0x2 0x8 0x2 0x197 0x2 0x9 0x2 0x197>;
|
phandle = <0x119>;
|
};
|
};
|
|
sdmmc {
|
|
sdmmc-bus4 {
|
rockchip,pins = <0x4 0x18 0x1 0x193 0x4 0x19 0x1 0x193 0x4 0x1a 0x1 0x193 0x4 0x1b 0x1 0x193>;
|
phandle = <0x116>;
|
};
|
|
sdmmc-clk {
|
rockchip,pins = <0x4 0x1d 0x1 0x193>;
|
phandle = <0x113>;
|
};
|
|
sdmmc-cmd {
|
rockchip,pins = <0x4 0x1c 0x1 0x193>;
|
phandle = <0x114>;
|
};
|
|
sdmmc-det {
|
rockchip,pins = <0x0 0x4 0x1 0x197>;
|
phandle = <0x115>;
|
};
|
|
sdmmc-pwren {
|
rockchip,pins = <0x0 0x5 0x2 0x192>;
|
phandle = <0x3e6>;
|
};
|
};
|
|
spdif0 {
|
|
spdif0m0-tx {
|
rockchip,pins = <0x1 0xe 0x3 0x192>;
|
phandle = <0x145>;
|
};
|
|
spdif0m1-tx {
|
rockchip,pins = <0x4 0xc 0x6 0x192>;
|
phandle = <0x3e7>;
|
};
|
};
|
|
spdif1 {
|
|
spdif1m0-tx {
|
rockchip,pins = <0x1 0xf 0x3 0x192>;
|
phandle = <0x146>;
|
};
|
|
spdif1m1-tx {
|
rockchip,pins = <0x4 0x9 0x2 0x192>;
|
phandle = <0x3e8>;
|
};
|
|
spdif1m2-tx {
|
rockchip,pins = <0x4 0x11 0x3 0x192>;
|
phandle = <0x3e9>;
|
};
|
};
|
|
spi0 {
|
|
spi0m0-pins {
|
rockchip,pins = <0x0 0x16 0x8 0x199 0x0 0x17 0x8 0x199 0x0 0x10 0x8 0x199>;
|
phandle = <0x155>;
|
};
|
|
spi0m0-cs0 {
|
rockchip,pins = <0x0 0x19 0x8 0x199>;
|
phandle = <0x153>;
|
};
|
|
spi0m0-cs1 {
|
rockchip,pins = <0x0 0xf 0x8 0x199>;
|
phandle = <0x154>;
|
};
|
|
spi0m1-pins {
|
rockchip,pins = <0x4 0x2 0x8 0x199 0x4 0x0 0x8 0x199 0x4 0x1 0x8 0x199>;
|
phandle = <0x3ea>;
|
};
|
|
spi0m1-cs0 {
|
rockchip,pins = <0x4 0xa 0x8 0x199>;
|
phandle = <0x3eb>;
|
};
|
|
spi0m1-cs1 {
|
rockchip,pins = <0x4 0x9 0x8 0x199>;
|
phandle = <0x3ec>;
|
};
|
|
spi0m2-pins {
|
rockchip,pins = <0x1 0xb 0x8 0x199 0x1 0x9 0x8 0x199 0x1 0xa 0x8 0x199>;
|
phandle = <0x3ed>;
|
};
|
|
spi0m2-cs0 {
|
rockchip,pins = <0x1 0xc 0x8 0x199>;
|
phandle = <0x3ee>;
|
};
|
|
spi0m2-cs1 {
|
rockchip,pins = <0x1 0xd 0x8 0x199>;
|
phandle = <0x3ef>;
|
};
|
|
spi0m3-pins {
|
rockchip,pins = <0x3 0x1b 0x8 0x199 0x3 0x19 0x8 0x199 0x3 0x1a 0x8 0x199>;
|
phandle = <0x3f0>;
|
};
|
|
spi0m3-cs0 {
|
rockchip,pins = <0x3 0x1c 0x8 0x199>;
|
phandle = <0x3f1>;
|
};
|
|
spi0m3-cs1 {
|
rockchip,pins = <0x3 0x1d 0x8 0x199>;
|
phandle = <0x3f2>;
|
};
|
};
|
|
spi1 {
|
|
spi1m1-pins {
|
rockchip,pins = <0x3 0x11 0x8 0x199 0x3 0x10 0x8 0x199 0x3 0xf 0x8 0x199>;
|
phandle = <0x158>;
|
};
|
|
spi1m1-cs0 {
|
rockchip,pins = <0x3 0x12 0x8 0x199>;
|
phandle = <0x156>;
|
};
|
|
spi1m1-cs1 {
|
rockchip,pins = <0x3 0x13 0x8 0x199>;
|
phandle = <0x157>;
|
};
|
|
spi1m2-pins {
|
rockchip,pins = <0x1 0x1a 0x8 0x199 0x1 0x18 0x8 0x199 0x1 0x19 0x8 0x199>;
|
phandle = <0x3f3>;
|
};
|
|
spi1m2-cs0 {
|
rockchip,pins = <0x1 0x1b 0x8 0x199>;
|
phandle = <0x3f4>;
|
};
|
|
spi1m2-cs1 {
|
rockchip,pins = <0x1 0x1d 0x8 0x199>;
|
phandle = <0x3f5>;
|
};
|
|
spi1m0-pins {
|
rockchip,pins = <0x2 0x10 0x8 0x19a 0x2 0x11 0x8 0x19a 0x2 0x12 0x8 0x19a>;
|
phandle = <0x3f6>;
|
};
|
|
spi1m0-cs0 {
|
rockchip,pins = <0x2 0x13 0x8 0x19a>;
|
phandle = <0x3f7>;
|
};
|
|
spi1m0-cs1 {
|
rockchip,pins = <0x2 0x14 0x8 0x19a>;
|
phandle = <0x3f8>;
|
};
|
};
|
|
spi2 {
|
|
spi2m0-pins {
|
rockchip,pins = <0x1 0x6 0x8 0x199 0x1 0x4 0x8 0x199 0x1 0x5 0x8 0x199>;
|
phandle = <0x3f9>;
|
};
|
|
spi2m0-cs0 {
|
rockchip,pins = <0x1 0x7 0x8 0x199>;
|
phandle = <0x3fa>;
|
};
|
|
spi2m0-cs1 {
|
rockchip,pins = <0x1 0x8 0x8 0x199>;
|
phandle = <0x3fb>;
|
};
|
|
spi2m1-pins {
|
rockchip,pins = <0x4 0x6 0x8 0x199 0x4 0x4 0x8 0x199 0x4 0x5 0x8 0x199>;
|
phandle = <0x3fc>;
|
};
|
|
spi2m1-cs0 {
|
rockchip,pins = <0x4 0x7 0x8 0x199>;
|
phandle = <0x3fd>;
|
};
|
|
spi2m1-cs1 {
|
rockchip,pins = <0x4 0x8 0x8 0x199>;
|
phandle = <0x3fe>;
|
};
|
|
spi2m2-pins {
|
rockchip,pins = <0x0 0x5 0x1 0x19a 0x0 0xb 0x1 0x19a 0x0 0x6 0x1 0x19a>;
|
phandle = <0x15a>;
|
};
|
|
spi2m2-cs0 {
|
rockchip,pins = <0x0 0x9 0x1 0x19a>;
|
phandle = <0x159>;
|
};
|
|
spi2m2-cs1 {
|
rockchip,pins = <0x0 0x8 0x1 0x19a>;
|
phandle = <0x3ff>;
|
};
|
};
|
|
spi3 {
|
|
spi3m1-pins {
|
rockchip,pins = <0x4 0xf 0x8 0x199 0x4 0xd 0x8 0x199 0x4 0xe 0x8 0x199>;
|
phandle = <0x165>;
|
};
|
|
spi3m1-cs0 {
|
rockchip,pins = <0x4 0x10 0x8 0x199>;
|
phandle = <0x163>;
|
};
|
|
spi3m1-cs1 {
|
rockchip,pins = <0x4 0x11 0x8 0x199>;
|
phandle = <0x164>;
|
};
|
|
spi3m2-pins {
|
rockchip,pins = <0x0 0x1b 0x8 0x199 0x0 0x18 0x8 0x199 0x0 0x1a 0x8 0x199>;
|
phandle = <0x400>;
|
};
|
|
spi3m2-cs0 {
|
rockchip,pins = <0x0 0x1c 0x8 0x199>;
|
phandle = <0x401>;
|
};
|
|
spi3m2-cs1 {
|
rockchip,pins = <0x0 0x1d 0x8 0x199>;
|
phandle = <0x402>;
|
};
|
|
spi3m3-pins {
|
rockchip,pins = <0x3 0x18 0x8 0x199 0x3 0x16 0x8 0x199 0x3 0x17 0x8 0x199>;
|
phandle = <0x403>;
|
};
|
|
spi3m3-cs0 {
|
rockchip,pins = <0x3 0x14 0x8 0x199>;
|
phandle = <0x404>;
|
};
|
|
spi3m3-cs1 {
|
rockchip,pins = <0x3 0x15 0x8 0x199>;
|
phandle = <0x405>;
|
};
|
|
spi3m0-pins {
|
rockchip,pins = <0x4 0x16 0x8 0x19a 0x4 0x14 0x8 0x19a 0x4 0x15 0x8 0x19a>;
|
phandle = <0x406>;
|
};
|
|
spi3m0-cs0 {
|
rockchip,pins = <0x4 0x12 0x8 0x19a>;
|
phandle = <0x407>;
|
};
|
|
spi3m0-cs1 {
|
rockchip,pins = <0x4 0x13 0x8 0x19a>;
|
phandle = <0x408>;
|
};
|
};
|
|
spi4 {
|
|
spi4m0-pins {
|
rockchip,pins = <0x1 0x12 0x8 0x199 0x1 0x10 0x8 0x199 0x1 0x11 0x8 0x199>;
|
phandle = <0x185>;
|
};
|
|
spi4m0-cs0 {
|
rockchip,pins = <0x1 0x13 0x8 0x199>;
|
phandle = <0x183>;
|
};
|
|
spi4m0-cs1 {
|
rockchip,pins = <0x1 0x14 0x8 0x199>;
|
phandle = <0x184>;
|
};
|
|
spi4m1-pins {
|
rockchip,pins = <0x3 0x2 0x8 0x199 0x3 0x0 0x8 0x199 0x3 0x1 0x8 0x199>;
|
phandle = <0x409>;
|
};
|
|
spi4m1-cs0 {
|
rockchip,pins = <0x3 0x3 0x8 0x199>;
|
phandle = <0x40a>;
|
};
|
|
spi4m1-cs1 {
|
rockchip,pins = <0x3 0x4 0x8 0x199>;
|
phandle = <0x40b>;
|
};
|
|
spi4m2-pins {
|
rockchip,pins = <0x1 0x2 0x8 0x199 0x1 0x0 0x8 0x199 0x1 0x1 0x8 0x199>;
|
phandle = <0x40c>;
|
};
|
|
spi4m2-cs0 {
|
rockchip,pins = <0x1 0x3 0x8 0x199>;
|
phandle = <0x40d>;
|
};
|
};
|
|
tsadc {
|
|
tsadcm1-shut {
|
rockchip,pins = <0x0 0x2 0x2 0x192>;
|
phandle = <0x40e>;
|
};
|
|
tsadc-shut {
|
rockchip,pins = <0x0 0x1 0x2 0x192>;
|
phandle = <0x17d>;
|
};
|
|
tsadc-shut-org {
|
rockchip,pins = <0x0 0x1 0x1 0x192>;
|
phandle = <0x40f>;
|
};
|
};
|
|
uart0 {
|
|
uart0m0-xfer {
|
rockchip,pins = <0x0 0x14 0x4 0x197 0x0 0x15 0x4 0x197>;
|
phandle = <0x410>;
|
};
|
|
uart0m1-xfer {
|
rockchip,pins = <0x0 0x8 0x4 0x197 0x0 0x9 0x4 0x197>;
|
phandle = <0x70>;
|
};
|
|
uart0m2-xfer {
|
rockchip,pins = <0x4 0x4 0xa 0x197 0x4 0x3 0xa 0x197>;
|
phandle = <0x411>;
|
};
|
|
uart0-ctsn {
|
rockchip,pins = <0x0 0x19 0x4 0x192>;
|
phandle = <0x412>;
|
};
|
|
uart0-rtsn {
|
rockchip,pins = <0x0 0x16 0x4 0x192>;
|
phandle = <0x413>;
|
};
|
};
|
|
uart1 {
|
|
uart1m1-xfer {
|
rockchip,pins = <0x1 0xf 0xa 0x197 0x1 0xe 0xa 0x197>;
|
phandle = <0x414>;
|
};
|
|
uart1m1-ctsn {
|
rockchip,pins = <0x1 0x1f 0xa 0x192>;
|
phandle = <0x415>;
|
};
|
|
uart1m1-rtsn {
|
rockchip,pins = <0x1 0x1e 0xa 0x192>;
|
phandle = <0x416>;
|
};
|
|
uart1m2-xfer {
|
rockchip,pins = <0x0 0x1a 0xa 0x197 0x0 0x19 0xa 0x197>;
|
phandle = <0x417>;
|
};
|
|
uart1m2-ctsn {
|
rockchip,pins = <0x0 0x18 0xa 0x192>;
|
phandle = <0x418>;
|
};
|
|
uart1m2-rtsn {
|
rockchip,pins = <0x0 0x17 0xa 0x192>;
|
phandle = <0x419>;
|
};
|
|
uart1m0-xfer {
|
rockchip,pins = <0x2 0xe 0xa 0x197 0x2 0xf 0xa 0x197>;
|
phandle = <0x166>;
|
};
|
|
uart1m0-ctsn {
|
rockchip,pins = <0x2 0x11 0xa 0x192>;
|
phandle = <0x41a>;
|
};
|
|
uart1m0-rtsn {
|
rockchip,pins = <0x2 0x10 0xa 0x192>;
|
phandle = <0x41b>;
|
};
|
};
|
|
uart2 {
|
|
uart2m0-xfer {
|
rockchip,pins = <0x0 0xe 0xa 0x197 0x0 0xd 0xa 0x197>;
|
phandle = <0x1eb>;
|
};
|
|
uart2m1-xfer {
|
rockchip,pins = <0x4 0x19 0xa 0x197 0x4 0x18 0xa 0x197>;
|
phandle = <0x167>;
|
};
|
|
uart2m2-xfer {
|
rockchip,pins = <0x3 0xa 0xa 0x197 0x3 0x9 0xa 0x197>;
|
phandle = <0x41c>;
|
};
|
|
uart2-ctsn {
|
rockchip,pins = <0x3 0xc 0xa 0x192>;
|
phandle = <0x41d>;
|
};
|
|
uart2-rtsn {
|
rockchip,pins = <0x3 0xb 0xa 0x192>;
|
phandle = <0x41e>;
|
};
|
};
|
|
uart3 {
|
|
uart3m0-xfer {
|
rockchip,pins = <0x1 0x10 0xa 0x197 0x1 0x11 0xa 0x197>;
|
phandle = <0x41f>;
|
};
|
|
uart3m1-xfer {
|
rockchip,pins = <0x3 0xe 0xa 0x197 0x3 0xd 0xa 0x197>;
|
phandle = <0x168>;
|
};
|
|
uart3m2-xfer {
|
rockchip,pins = <0x4 0x6 0xa 0x197 0x4 0x5 0xa 0x197>;
|
phandle = <0x420>;
|
};
|
|
uart3-ctsn {
|
rockchip,pins = <0x1 0x13 0xa 0x192>;
|
phandle = <0x421>;
|
};
|
|
uart3-rtsn {
|
rockchip,pins = <0x1 0x12 0xa 0x192>;
|
phandle = <0x422>;
|
};
|
};
|
|
uart4 {
|
|
uart4m0-xfer {
|
rockchip,pins = <0x1 0x1b 0xa 0x197 0x1 0x1a 0xa 0x197>;
|
phandle = <0x169>;
|
};
|
|
uart4m1-xfer {
|
rockchip,pins = <0x3 0x18 0xa 0x197 0x3 0x19 0xa 0x197>;
|
phandle = <0x423>;
|
};
|
|
uart4m2-xfer {
|
rockchip,pins = <0x1 0xa 0xa 0x197 0x1 0xb 0xa 0x197>;
|
phandle = <0x424>;
|
};
|
|
uart4-ctsn {
|
rockchip,pins = <0x1 0x17 0xa 0x192>;
|
phandle = <0x425>;
|
};
|
|
uart4-rtsn {
|
rockchip,pins = <0x1 0x15 0xa 0x192>;
|
phandle = <0x426>;
|
};
|
};
|
|
uart5 {
|
|
uart5m0-xfer {
|
rockchip,pins = <0x4 0x1c 0xa 0x197 0x4 0x1d 0xa 0x197>;
|
phandle = <0x427>;
|
};
|
|
uart5m0-ctsn {
|
rockchip,pins = <0x4 0x1a 0xa 0x192>;
|
phandle = <0x428>;
|
};
|
|
uart5m0-rtsn {
|
rockchip,pins = <0x4 0x1b 0xa 0x192>;
|
phandle = <0x429>;
|
};
|
|
uart5m1-xfer {
|
rockchip,pins = <0x3 0x15 0xa 0x197 0x3 0x14 0xa 0x197>;
|
phandle = <0x16a>;
|
};
|
|
uart5m1-ctsn {
|
rockchip,pins = <0x2 0x2 0xa 0x192>;
|
phandle = <0x42a>;
|
};
|
|
uart5m1-rtsn {
|
rockchip,pins = <0x2 0x3 0xa 0x192>;
|
phandle = <0x42b>;
|
};
|
|
uart5m2-xfer {
|
rockchip,pins = <0x2 0x1c 0xa 0x197 0x2 0x1d 0xa 0x197>;
|
phandle = <0x42c>;
|
};
|
};
|
|
uart6 {
|
|
uart6m1-xfer {
|
rockchip,pins = <0x1 0x0 0xa 0x197 0x1 0x1 0xa 0x197>;
|
phandle = <0x42d>;
|
};
|
|
uart6m1-ctsn {
|
rockchip,pins = <0x1 0x3 0xa 0x192>;
|
phandle = <0x42e>;
|
};
|
|
uart6m1-rtsn {
|
rockchip,pins = <0x1 0x2 0xa 0x192>;
|
phandle = <0x42f>;
|
};
|
|
uart6m2-xfer {
|
rockchip,pins = <0x1 0x19 0xa 0x197 0x1 0x18 0xa 0x197>;
|
phandle = <0x16b>;
|
};
|
|
uart6m0-xfer {
|
rockchip,pins = <0x2 0x6 0xa 0x197 0x2 0x7 0xa 0x197>;
|
phandle = <0x430>;
|
};
|
|
uart6m0-ctsn {
|
rockchip,pins = <0x2 0x9 0xa 0x192>;
|
phandle = <0x431>;
|
};
|
|
uart6m0-rtsn {
|
rockchip,pins = <0x2 0x8 0xa 0x192>;
|
phandle = <0x432>;
|
};
|
};
|
|
uart7 {
|
|
uart7m1-xfer {
|
rockchip,pins = <0x3 0x11 0xa 0x197 0x3 0x10 0xa 0x197>;
|
phandle = <0x16c>;
|
};
|
|
uart7m1-ctsn {
|
rockchip,pins = <0x3 0x13 0xa 0x192>;
|
phandle = <0x433>;
|
};
|
|
uart7m1-rtsn {
|
rockchip,pins = <0x3 0x12 0xa 0x192>;
|
phandle = <0x434>;
|
};
|
|
uart7m2-xfer {
|
rockchip,pins = <0x1 0xc 0xa 0x197 0x1 0xd 0xa 0x197>;
|
phandle = <0x435>;
|
};
|
|
uart7m0-xfer {
|
rockchip,pins = <0x2 0xc 0xa 0x197 0x2 0xd 0xa 0x197>;
|
phandle = <0x436>;
|
};
|
|
uart7m0-ctsn {
|
rockchip,pins = <0x4 0x16 0xa 0x192>;
|
phandle = <0x437>;
|
};
|
|
uart7m0-rtsn {
|
rockchip,pins = <0x4 0x12 0xa 0x192>;
|
phandle = <0x438>;
|
};
|
};
|
|
uart8 {
|
|
uart8m0-xfer {
|
rockchip,pins = <0x4 0x9 0xa 0x197 0x4 0x8 0xa 0x197>;
|
phandle = <0x439>;
|
};
|
|
uart8m0-ctsn {
|
rockchip,pins = <0x4 0xb 0xa 0x192>;
|
phandle = <0x43a>;
|
};
|
|
uart8m0-rtsn {
|
rockchip,pins = <0x4 0xa 0xa 0x192>;
|
phandle = <0x43b>;
|
};
|
|
uart8m1-xfer {
|
rockchip,pins = <0x3 0x3 0xa 0x197 0x3 0x2 0xa 0x197>;
|
phandle = <0x16d>;
|
};
|
|
uart8m1-ctsn {
|
rockchip,pins = <0x3 0x5 0xa 0x192>;
|
phandle = <0x43c>;
|
};
|
|
uart8m1-rtsn {
|
rockchip,pins = <0x3 0x4 0xa 0x192>;
|
phandle = <0x43d>;
|
};
|
|
uart8-xfer {
|
rockchip,pins = <0x4 0x9 0xa 0x197>;
|
phandle = <0x43e>;
|
};
|
};
|
|
uart9 {
|
|
uart9m1-xfer {
|
rockchip,pins = <0x4 0xd 0xa 0x197 0x4 0xc 0xa 0x197>;
|
phandle = <0x43f>;
|
};
|
|
uart9m1-ctsn {
|
rockchip,pins = <0x4 0x1 0xa 0x192>;
|
phandle = <0x440>;
|
};
|
|
uart9m1-rtsn {
|
rockchip,pins = <0x4 0x0 0xa 0x192>;
|
phandle = <0x441>;
|
};
|
|
uart9m2-xfer {
|
rockchip,pins = <0x3 0x1c 0xa 0x197 0x3 0x1d 0xa 0x197>;
|
phandle = <0x442>;
|
};
|
|
uart9m2-ctsn {
|
rockchip,pins = <0x3 0x1b 0xa 0x192>;
|
phandle = <0x443>;
|
};
|
|
uart9m2-rtsn {
|
rockchip,pins = <0x3 0x1a 0xa 0x192>;
|
phandle = <0x444>;
|
};
|
|
uart9m0-xfer {
|
rockchip,pins = <0x2 0x14 0xa 0x197 0x2 0x12 0xa 0x197>;
|
phandle = <0x16e>;
|
};
|
|
uart9m0-ctsn {
|
rockchip,pins = <0x4 0x15 0xa 0x192>;
|
phandle = <0x16f>;
|
};
|
|
uart9m0-rtsn {
|
rockchip,pins = <0x4 0x14 0xa 0x192>;
|
phandle = <0x1e4>;
|
};
|
};
|
|
vop {
|
|
vop-pins {
|
rockchip,pins = <0x1 0x2 0x1 0x192>;
|
phandle = <0x445>;
|
};
|
};
|
|
bt656 {
|
|
bt656-pins {
|
rockchip,pins = <0x4 0x8 0x2 0x19b 0x4 0x0 0x2 0x19b 0x4 0x1 0x2 0x19b 0x4 0x2 0x2 0x19b 0x4 0x3 0x2 0x19b 0x4 0x4 0x2 0x19b 0x4 0x5 0x2 0x19b 0x4 0x6 0x2 0x19b 0x4 0x7 0x2 0x19b>;
|
phandle = <0x446>;
|
};
|
};
|
|
gpio-func {
|
|
tsadc-gpio-func {
|
rockchip,pins = <0x0 0x1 0x0 0x192>;
|
phandle = <0x17c>;
|
};
|
};
|
|
pcfg-pull-none-drv-level-7 {
|
bias-disable;
|
drive-strength = <0x7>;
|
phandle = <0x447>;
|
};
|
|
pcfg-pull-none-drv-level-8 {
|
bias-disable;
|
drive-strength = <0x8>;
|
phandle = <0x448>;
|
};
|
|
pcfg-pull-none-drv-level-9 {
|
bias-disable;
|
drive-strength = <0x9>;
|
phandle = <0x449>;
|
};
|
|
pcfg-pull-none-drv-level-10 {
|
bias-disable;
|
drive-strength = <0xa>;
|
phandle = <0x44a>;
|
};
|
|
pcfg-pull-none-drv-level-11 {
|
bias-disable;
|
drive-strength = <0xb>;
|
phandle = <0x44b>;
|
};
|
|
pcfg-pull-none-drv-level-12 {
|
bias-disable;
|
drive-strength = <0xc>;
|
phandle = <0x44c>;
|
};
|
|
pcfg-pull-none-drv-level-13 {
|
bias-disable;
|
drive-strength = <0xd>;
|
phandle = <0x44d>;
|
};
|
|
pcfg-pull-none-drv-level-14 {
|
bias-disable;
|
drive-strength = <0xe>;
|
phandle = <0x44e>;
|
};
|
|
pcfg-pull-none-drv-level-15 {
|
bias-disable;
|
drive-strength = <0xf>;
|
phandle = <0x44f>;
|
};
|
|
pcfg-pull-up-drv-level-7 {
|
bias-pull-up;
|
drive-strength = <0x7>;
|
phandle = <0x450>;
|
};
|
|
pcfg-pull-up-drv-level-8 {
|
bias-pull-up;
|
drive-strength = <0x8>;
|
phandle = <0x451>;
|
};
|
|
pcfg-pull-up-drv-level-9 {
|
bias-pull-up;
|
drive-strength = <0x9>;
|
phandle = <0x452>;
|
};
|
|
pcfg-pull-up-drv-level-10 {
|
bias-pull-up;
|
drive-strength = <0xa>;
|
phandle = <0x453>;
|
};
|
|
pcfg-pull-up-drv-level-11 {
|
bias-pull-up;
|
drive-strength = <0xb>;
|
phandle = <0x454>;
|
};
|
|
pcfg-pull-up-drv-level-12 {
|
bias-pull-up;
|
drive-strength = <0xc>;
|
phandle = <0x455>;
|
};
|
|
pcfg-pull-up-drv-level-13 {
|
bias-pull-up;
|
drive-strength = <0xd>;
|
phandle = <0x456>;
|
};
|
|
pcfg-pull-up-drv-level-14 {
|
bias-pull-up;
|
drive-strength = <0xe>;
|
phandle = <0x457>;
|
};
|
|
pcfg-pull-up-drv-level-15 {
|
bias-pull-up;
|
drive-strength = <0xf>;
|
phandle = <0x458>;
|
};
|
|
pcfg-pull-down-drv-level-7 {
|
bias-pull-down;
|
drive-strength = <0x7>;
|
phandle = <0x459>;
|
};
|
|
pcfg-pull-down-drv-level-8 {
|
bias-pull-down;
|
drive-strength = <0x8>;
|
phandle = <0x45a>;
|
};
|
|
pcfg-pull-down-drv-level-9 {
|
bias-pull-down;
|
drive-strength = <0x9>;
|
phandle = <0x45b>;
|
};
|
|
pcfg-pull-down-drv-level-10 {
|
bias-pull-down;
|
drive-strength = <0xa>;
|
phandle = <0x45c>;
|
};
|
|
pcfg-pull-down-drv-level-11 {
|
bias-pull-down;
|
drive-strength = <0xb>;
|
phandle = <0x45d>;
|
};
|
|
pcfg-pull-down-drv-level-12 {
|
bias-pull-down;
|
drive-strength = <0xc>;
|
phandle = <0x45e>;
|
};
|
|
pcfg-pull-down-drv-level-13 {
|
bias-pull-down;
|
drive-strength = <0xd>;
|
phandle = <0x45f>;
|
};
|
|
pcfg-pull-down-drv-level-14 {
|
bias-pull-down;
|
drive-strength = <0xe>;
|
phandle = <0x460>;
|
};
|
|
pcfg-pull-down-drv-level-15 {
|
bias-pull-down;
|
drive-strength = <0xf>;
|
phandle = <0x461>;
|
};
|
|
eth0 {
|
|
eth0-pins {
|
rockchip,pins = <0x2 0x13 0x1 0x192>;
|
phandle = <0x462>;
|
};
|
};
|
|
gmac0 {
|
|
gmac0-miim {
|
rockchip,pins = <0x4 0x14 0x1 0x192 0x4 0x15 0x1 0x192>;
|
phandle = <0x463>;
|
};
|
|
gmac0-clkinout {
|
rockchip,pins = <0x4 0x13 0x1 0x192>;
|
phandle = <0x464>;
|
};
|
|
gmac0-rx-bus2 {
|
rockchip,pins = <0x2 0x11 0x1 0x192 0x2 0x12 0x1 0x192 0x4 0x12 0x1 0x192>;
|
phandle = <0x465>;
|
};
|
|
gmac0-tx-bus2 {
|
rockchip,pins = <0x2 0xe 0x1 0x192 0x2 0xf 0x1 0x192 0x2 0x10 0x1 0x192>;
|
phandle = <0x466>;
|
};
|
|
gmac0-rgmii-clk {
|
rockchip,pins = <0x2 0x8 0x1 0x192 0x2 0xb 0x1 0x192>;
|
phandle = <0x467>;
|
};
|
|
gmac0-rgmii-bus {
|
rockchip,pins = <0x2 0x6 0x1 0x192 0x2 0x7 0x1 0x192 0x2 0x9 0x1 0x192 0x2 0xa 0x1 0x192>;
|
phandle = <0x468>;
|
};
|
|
gmac0-ppsclk {
|
rockchip,pins = <0x2 0x14 0x1 0x192>;
|
phandle = <0x469>;
|
};
|
|
gmac0-ppstring {
|
rockchip,pins = <0x2 0xd 0x1 0x192>;
|
phandle = <0x46a>;
|
};
|
|
gmac0-ptp-refclk {
|
rockchip,pins = <0x2 0xc 0x1 0x192>;
|
phandle = <0x46b>;
|
};
|
|
gmac0-txer {
|
rockchip,pins = <0x4 0x16 0x1 0x192>;
|
phandle = <0x46c>;
|
};
|
};
|
|
cam {
|
|
mipicsi0-pwr {
|
rockchip,pins = <0x1 0x1a 0x0 0x192>;
|
phandle = <0x46d>;
|
};
|
|
mipicsi1-pwr {
|
rockchip,pins = <0x1 0x1b 0x0 0x192>;
|
phandle = <0x46e>;
|
};
|
|
mipidcphy0-pwr {
|
rockchip,pins = <0x2 0x14 0x0 0x192>;
|
phandle = <0x46f>;
|
};
|
};
|
|
vga {
|
|
vga-hpdin-l {
|
rockchip,pins = <0x3 0x6 0x0 0x192>;
|
phandle = <0x470>;
|
};
|
};
|
|
headphone {
|
|
hp-det {
|
rockchip,pins = <0x3 0x1d 0x0 0x192>;
|
phandle = <0x1e1>;
|
};
|
|
spk-con {
|
rockchip,pins = <0x4 0xc 0x0 0x192>;
|
phandle = <0x1d9>;
|
};
|
};
|
|
hym8563 {
|
|
hym8563-int {
|
rockchip,pins = <0x0 0x8 0x0 0x197>;
|
phandle = <0x180>;
|
};
|
};
|
|
lcd {
|
|
lcd-rst-gpio {
|
rockchip,pins = <0x1 0x0 0x0 0x192>;
|
phandle = <0x471>;
|
};
|
};
|
|
sdio-pwrseq {
|
|
wifi-enable-h {
|
rockchip,pins = <0x1 0x16 0x0 0x197>;
|
phandle = <0x1e0>;
|
};
|
};
|
|
touch {
|
|
touch-gpio {
|
rockchip,pins = <0x3 0x11 0x0 0x198 0x3 0x10 0x0 0x197>;
|
phandle = <0x152>;
|
};
|
};
|
|
usb {
|
|
vcc5v0-host-en {
|
rockchip,pins = <0x4 0x8 0x0 0x192>;
|
phandle = <0x1e3>;
|
};
|
};
|
|
wireless-bluetooth {
|
|
uart9-gpios {
|
rockchip,pins = <0x4 0x14 0x0 0x192>;
|
phandle = <0x1e6>;
|
};
|
|
bt-reset-gpio {
|
rockchip,pins = <0x0 0xa 0x0 0x192>;
|
phandle = <0x1e5>;
|
};
|
};
|
|
ndj_io_init {
|
|
ndj_io_gpio_col {
|
rockchip,pins = <0x0 0x1b 0x0 0x192 0x4 0x1 0x0 0x192 0x4 0xe 0x0 0x192 0x0 0x16 0x0 0x192 0x2 0xc 0x0 0x192 0x2 0x13 0x0 0x192 0x4 0xd 0x0 0x192 0x1 0x9 0x0 0x192 0x1 0x0 0x0 0x192 0x1 0xa 0x0 0x192 0x1 0x1 0x0 0x192 0x1 0xb 0x0 0x192 0x1 0x2 0x0 0x192 0x1 0xc 0x0 0x192 0x1 0x3 0x0 0x192>;
|
phandle = <0x1e7>;
|
};
|
};
|
};
|
|
rkcif-mipi-lvds4 {
|
compatible = "rockchip,rkcif-mipi-lvds";
|
rockchip,hw = <0x49>;
|
iommus = <0x4a>;
|
status = "disabled";
|
phandle = <0x19c>;
|
};
|
|
rkcif-mipi-lvds4-sditf {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x19c>;
|
status = "disabled";
|
phandle = <0x472>;
|
};
|
|
rkcif-mipi-lvds4-sditf-vir1 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x19c>;
|
status = "disabled";
|
phandle = <0x473>;
|
};
|
|
rkcif-mipi-lvds4-sditf-vir2 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x19c>;
|
status = "disabled";
|
phandle = <0x474>;
|
};
|
|
rkcif-mipi-lvds4-sditf-vir3 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x19c>;
|
status = "disabled";
|
phandle = <0x475>;
|
};
|
|
rkcif-mipi-lvds5 {
|
compatible = "rockchip,rkcif-mipi-lvds";
|
rockchip,hw = <0x49>;
|
iommus = <0x4a>;
|
status = "disabled";
|
phandle = <0x19d>;
|
};
|
|
rkcif-mipi-lvds5-sditf {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x19d>;
|
status = "disabled";
|
phandle = <0x476>;
|
};
|
|
rkcif-mipi-lvds5-sditf-vir1 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x19d>;
|
status = "disabled";
|
phandle = <0x477>;
|
};
|
|
rkcif-mipi-lvds5-sditf-vir2 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x19d>;
|
status = "disabled";
|
phandle = <0x478>;
|
};
|
|
rkcif-mipi-lvds5-sditf-vir3 {
|
compatible = "rockchip,rkcif-sditf";
|
rockchip,cif = <0x19d>;
|
status = "disabled";
|
phandle = <0x479>;
|
};
|
|
usbdrd3_1 {
|
compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
|
clocks = <0x2 0x1a6 0x2 0x1a5 0x2 0x1a4>;
|
clock-names = "ref", "suspend", "bus";
|
#address-cells = <0x2>;
|
#size-cells = <0x2>;
|
ranges;
|
status = "okay";
|
phandle = <0x47a>;
|
|
usb@fc400000 {
|
compatible = "snps,dwc3";
|
reg = <0x0 0xfc400000 0x0 0x400000>;
|
interrupts = <0x0 0xdd 0x4>;
|
power-domains = <0x57 0x1f>;
|
resets = <0x2 0x2a7>;
|
reset-names = "usb3-otg";
|
dr_mode = "host";
|
phys = <0x19e 0x19f>;
|
phy-names = "usb2-phy", "usb3-phy";
|
phy_type = "utmi_wide";
|
snps,dis_enblslpm_quirk;
|
snps,dis-u2-freeclk-exists-quirk;
|
snps,dis-del-phy-power-chg-quirk;
|
snps,dis-tx-ipgap-linecheck-quirk;
|
status = "okay";
|
phandle = <0x47b>;
|
};
|
};
|
|
syscon@fd5b8000 {
|
compatible = "rockchip,pcie30-phy-grf", "syscon";
|
reg = <0x0 0xfd5b8000 0x0 0x10000>;
|
phandle = <0x1c3>;
|
};
|
|
syscon@fd5c0000 {
|
compatible = "rockchip,pipe-phy-grf", "syscon";
|
reg = <0x0 0xfd5c0000 0x0 0x100>;
|
phandle = <0x1c2>;
|
};
|
|
syscon@fd5cc000 {
|
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
reg = <0x0 0xfd5cc000 0x0 0x4000>;
|
phandle = <0x1c0>;
|
};
|
|
syscon@fd5d4000 {
|
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
reg = <0x0 0xfd5d4000 0x0 0x4000>;
|
#address-cells = <0x1>;
|
#size-cells = <0x1>;
|
phandle = <0x1bf>;
|
|
usb2-phy@4000 {
|
compatible = "rockchip,rk3588-usb2phy";
|
reg = <0x4000 0x10>;
|
interrupts = <0x0 0x18a 0x4>;
|
resets = <0x2 0xc0048 0x2 0x489>;
|
reset-names = "phy", "apb";
|
clocks = <0x2 0x2b5>;
|
clock-names = "phyclk";
|
clock-output-names = "usb480m_phy1";
|
#clock-cells = <0x0>;
|
rockchip,usbctrl-grf = <0x6a>;
|
status = "okay";
|
phandle = <0x1c1>;
|
|
otg-port {
|
#phy-cells = <0x0>;
|
status = "okay";
|
phy-supply = <0x6b>;
|
phandle = <0x19e>;
|
};
|
};
|
};
|
|
syscon@fd5e4000 {
|
compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
|
reg = <0x0 0xfd5e4000 0x0 0x100>;
|
phandle = <0x1be>;
|
};
|
|
spdif-tx@fddb8000 {
|
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
|
reg = <0x0 0xfddb8000 0x0 0x1000>;
|
interrupts = <0x0 0xc6 0x4>;
|
dmas = <0xe5 0x16>;
|
dma-names = "tx";
|
clock-names = "mclk", "hclk";
|
clocks = <0x2 0x20f 0x2 0x20a>;
|
assigned-clocks = <0x2 0x20b>;
|
assigned-clock-parents = <0x2 0x5>;
|
power-domains = <0x57 0x19>;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x1cf>;
|
};
|
|
i2s@fddc8000 {
|
compatible = "rockchip,rk3588-i2s-tdm";
|
reg = <0x0 0xfddc8000 0x0 0x1000>;
|
interrupts = <0x0 0xbc 0x4>;
|
clocks = <0x2 0x201 0x2 0x1fe>;
|
clock-names = "mclk_tx", "hclk";
|
assigned-clocks = <0x2 0x1ff>;
|
assigned-clock-parents = <0x2 0x5>;
|
dmas = <0xe6 0x16>;
|
dma-names = "tx";
|
power-domains = <0x57 0x19>;
|
resets = <0x2 0x391>;
|
reset-names = "tx-m";
|
rockchip,playback-only;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x47c>;
|
};
|
|
spdif-tx@fdde8000 {
|
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
|
reg = <0x0 0xfdde8000 0x0 0x1000>;
|
interrupts = <0x0 0xc5 0x4>;
|
dmas = <0xe5 0x8>;
|
dma-names = "tx";
|
clock-names = "mclk", "hclk";
|
clocks = <0x2 0x25c 0x2 0x258>;
|
assigned-clocks = <0x2 0x259>;
|
assigned-clock-parents = <0x2 0x5>;
|
power-domains = <0x57 0x1a>;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x47d>;
|
};
|
|
i2s@fddf4000 {
|
compatible = "rockchip,rk3588-i2s-tdm";
|
reg = <0x0 0xfddf4000 0x0 0x1000>;
|
interrupts = <0x0 0xba 0x4>;
|
clocks = <0x2 0x24c 0x2 0x24c 0x2 0x252>;
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
assigned-clocks = <0x2 0x249>;
|
assigned-clock-parents = <0x2 0x7>;
|
dmas = <0xe6 0x4>;
|
dma-names = "tx";
|
power-domains = <0x57 0x1a>;
|
resets = <0x2 0x3ef>;
|
reset-names = "tx-m";
|
rockchip,always-on;
|
rockchip,hdmi-path;
|
rockchip,playback-only;
|
#sound-dai-cells = <0x0>;
|
status = "okay";
|
phandle = <0x1cb>;
|
};
|
|
i2s@fddf8000 {
|
compatible = "rockchip,rk3588-i2s-tdm";
|
reg = <0x0 0xfddf8000 0x0 0x1000>;
|
interrupts = <0x0 0xbb 0x4>;
|
clocks = <0x2 0x23c 0x2 0x23c 0x2 0x238>;
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
assigned-clocks = <0x2 0x239>;
|
assigned-clock-parents = <0x2 0x5>;
|
dmas = <0xe6 0x15>;
|
dma-names = "rx";
|
power-domains = <0x57 0x1a>;
|
resets = <0x2 0x3c3>;
|
reset-names = "rx-m";
|
rockchip,capture-only;
|
#sound-dai-cells = <0x0>;
|
status = "okay";
|
phandle = <0x1db>;
|
};
|
|
i2s@fde00000 {
|
compatible = "rockchip,rk3588-i2s-tdm";
|
reg = <0x0 0xfde00000 0x0 0x1000>;
|
interrupts = <0x0 0xbe 0x4>;
|
clocks = <0x2 0x237 0x2 0x237 0x2 0x233>;
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
assigned-clocks = <0x2 0x234>;
|
assigned-clock-parents = <0x2 0x5>;
|
dmas = <0xe6 0x18>;
|
dma-names = "rx";
|
power-domains = <0x57 0x1a>;
|
resets = <0x2 0x417>;
|
reset-names = "rx-m";
|
rockchip,capture-only;
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x47e>;
|
};
|
|
spdif-rx@fde10000 {
|
compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
|
reg = <0x0 0xfde10000 0x0 0x1000>;
|
interrupts = <0x0 0xc8 0x4>;
|
clocks = <0x2 0x260 0x2 0x25f>;
|
clock-names = "mclk", "hclk";
|
assigned-clocks = <0x2 0x260>;
|
assigned-clock-parents = <0x2 0x5>;
|
dmas = <0x6f 0x16>;
|
dma-names = "rx";
|
power-domains = <0x57 0x1a>;
|
resets = <0x2 0x3ff>;
|
reset-names = "spdifrx-m";
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x47f>;
|
};
|
|
spdif-rx@fde18000 {
|
compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
|
reg = <0x0 0xfde18000 0x0 0x1000>;
|
interrupts = <0x0 0xc9 0x4>;
|
clocks = <0x2 0x262 0x2 0x261>;
|
clock-names = "mclk", "hclk";
|
assigned-clocks = <0x2 0x262>;
|
assigned-clock-parents = <0x2 0x5>;
|
dmas = <0x6f 0x17>;
|
dma-names = "rx";
|
power-domains = <0x57 0x1a>;
|
resets = <0x2 0x401>;
|
reset-names = "spdifrx-m";
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x480>;
|
};
|
|
dp@fde60000 {
|
compatible = "rockchip,rk3588-dp";
|
reg = <0x0 0xfde60000 0x0 0x4000>;
|
interrupts = <0x0 0xa2 0x4>;
|
clocks = <0x2 0x1e7 0x2 0x2cd 0x2 0x201 0x2 0x20d 0x4 0x2 0x1eb>;
|
clock-names = "apb", "aux", "i2s", "spdif", "hclk", "hdcp";
|
assigned-clocks = <0x2 0x2cd>;
|
assigned-clock-rates = <0xf42400>;
|
resets = <0x2 0x389>;
|
phys = <0x1a0>;
|
power-domains = <0x57 0x19>;
|
#sound-dai-cells = <0x1>;
|
status = "disabled";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x1a1>;
|
phandle = <0x1d0>;
|
|
ports {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
port@0 {
|
reg = <0x0>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
endpoint@0 {
|
reg = <0x0>;
|
remote-endpoint = <0x1a2>;
|
status = "disabled";
|
phandle = <0xd1>;
|
};
|
|
endpoint@1 {
|
reg = <0x1>;
|
remote-endpoint = <0x3a>;
|
status = "disabled";
|
phandle = <0xd7>;
|
};
|
|
endpoint@2 {
|
reg = <0x2>;
|
remote-endpoint = <0x1a3>;
|
status = "disabled";
|
phandle = <0xdf>;
|
};
|
};
|
|
port@1 {
|
reg = <0x1>;
|
|
endpoint {
|
phandle = <0x481>;
|
};
|
};
|
};
|
};
|
|
hdmi@fdea0000 {
|
compatible = "rockchip,rk3588-dw-hdmi";
|
reg = <0x0 0xfdea0000 0x0 0x10000 0x0 0xfdeb0000 0x0 0x10000>;
|
interrupts = <0x0 0xad 0x4 0x0 0xae 0x4 0x0 0xaf 0x4 0x0 0xb0 0x4 0x0 0x169 0x4>;
|
clocks = <0x2 0x224 0x2 0x266 0x2 0x225 0x2 0x226 0x2 0x24c 0x2 0x274 0x2 0x275 0x2 0x276 0x2 0x277 0x5 0x1a4>;
|
clock-names = "pclk", "hpd", "earc", "hdmitx_ref", "aud", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", "hclk_vo1", "link_clk";
|
resets = <0x2 0x3d7 0x2 0x49d>;
|
reset-names = "ref", "hdp";
|
power-domains = <0x57 0x1a>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x1a5 0x1a6 0x1a7 0x1a8>;
|
reg-io-width = <0x4>;
|
rockchip,grf = <0xbc>;
|
rockchip,vo1_grf = <0xcc>;
|
phys = <0x1a9>;
|
phy-names = "hdmi";
|
#sound-dai-cells = <0x0>;
|
status = "disabled";
|
enable-gpios = <0xfc 0xa 0x0>;
|
phandle = <0x1cc>;
|
|
ports {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
port@0 {
|
reg = <0x0>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
phandle = <0x482>;
|
|
endpoint@0 {
|
reg = <0x0>;
|
remote-endpoint = <0x1aa>;
|
status = "disabled";
|
phandle = <0xd3>;
|
};
|
|
endpoint@1 {
|
reg = <0x1>;
|
remote-endpoint = <0x3b>;
|
status = "disabled";
|
phandle = <0xd9>;
|
};
|
|
endpoint@2 {
|
reg = <0x2>;
|
remote-endpoint = <0x1ab>;
|
status = "disabled";
|
phandle = <0xe1>;
|
};
|
};
|
};
|
};
|
|
edp@fded0000 {
|
compatible = "rockchip,rk3588-edp";
|
reg = <0x0 0xfded0000 0x0 0x1000>;
|
interrupts = <0x0 0xa4 0x4>;
|
clocks = <0x2 0x214 0x2 0x213 0x2 0x215 0x5>;
|
clock-names = "dp", "pclk", "spdif", "hclk";
|
resets = <0x2 0x3e4 0x2 0x3e3>;
|
reset-names = "dp", "apb";
|
phys = <0x1ac>;
|
phy-names = "dp";
|
power-domains = <0x57 0x1a>;
|
rockchip,grf = <0xcc>;
|
status = "okay";
|
force-hpd;
|
phandle = <0x483>;
|
|
ports {
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
port@0 {
|
reg = <0x0>;
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
|
endpoint@0 {
|
reg = <0x0>;
|
remote-endpoint = <0x1ad>;
|
status = "disabled";
|
phandle = <0xd2>;
|
};
|
|
endpoint@1 {
|
reg = <0x1>;
|
remote-endpoint = <0x1ae>;
|
status = "disabled";
|
phandle = <0xd8>;
|
};
|
|
endpoint@2 {
|
reg = <0x2>;
|
remote-endpoint = <0x37>;
|
status = "okay";
|
phandle = <0xe0>;
|
};
|
};
|
|
port@1 {
|
reg = <0x1>;
|
|
endpoint {
|
remote-endpoint = <0x1af>;
|
phandle = <0x1ea>;
|
};
|
};
|
};
|
};
|
|
hdmirx-controller@fdee0000 {
|
compatible = "rockchip,rk3588-hdmirx-ctrler", "rockchip,hdmirx-ctrler";
|
reg = <0x0 0xfdee0000 0x0 0x6000>;
|
reg-names = "hdmirx_regs";
|
power-domains = <0x57 0x1a>;
|
rockchip,grf = <0xbc>;
|
rockchip,vo1_grf = <0xcc>;
|
interrupts = <0x0 0xb1 0x4 0x0 0x1b4 0x4 0x0 0xb3 0x4>;
|
interrupt-names = "cec", "hdmi", "dma";
|
clocks = <0x2 0x21a 0x2 0x21f 0x2 0x2b2 0x2 0x21b 0x2 0x21c 0x2 0x232 0x5>;
|
clock-names = "aclk", "audio", "cr_para", "pclk", "ref", "hclk_s_hdmirx", "hclk_vo1";
|
resets = <0x2 0x3d9 0x2 0x3da 0x2 0x3db 0x2 0x3b7>;
|
reset-names = "rst_a", "rst_p", "rst_ref", "rst_biu";
|
pinctrl-0 = <0x1b0 0x1b1>;
|
pinctrl-names = "default";
|
status = "okay";
|
#sound-dai-cells = <0x1>;
|
hpd-trigger-level = <0x1>;
|
hdmirx-det-gpios = <0x1b2 0xe 0x1>;
|
phandle = <0x1da>;
|
};
|
|
pcie@fe150000 {
|
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
|
#address-cells = <0x3>;
|
#size-cells = <0x2>;
|
bus-range = <0x0 0xf>;
|
clocks = <0x2 0x14e 0x2 0x153 0x2 0x149 0x2 0x158 0x2 0x15e 0x2 0x183>;
|
clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux", "pipe";
|
device_type = "pci";
|
interrupts = <0x0 0x107 0x4 0x0 0x106 0x4 0x0 0x105 0x4 0x0 0x104 0x4 0x0 0x103 0x4>;
|
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
#interrupt-cells = <0x1>;
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
interrupt-map = <0x0 0x0 0x0 0x1 0x1b3 0x0 0x0 0x0 0x0 0x2 0x1b3 0x1 0x0 0x0 0x0 0x3 0x1b3 0x2 0x0 0x0 0x0 0x4 0x1b3 0x3>;
|
linux,pci-domain = <0x0>;
|
num-ib-windows = <0x10>;
|
num-ob-windows = <0x10>;
|
num-viewport = <0x8>;
|
max-link-speed = <0x3>;
|
msi-map = <0x0 0x1b4 0x0 0x1000>;
|
num-lanes = <0x4>;
|
phys = <0x1b5>;
|
phy-names = "pcie-phy";
|
power-domains = <0x57 0x22>;
|
ranges = <0x800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0xe00000 0xc3000000 0x9 0x0 0x9 0x0 0x0 0x40000000>;
|
reg = <0x0 0xfe150000 0x0 0x10000 0xa 0x40000000 0x0 0x400000>;
|
reg-names = "pcie-apb", "pcie-dbi";
|
resets = <0x2 0x20d 0x2 0x21c>;
|
reset-names = "pcie", "periph";
|
rockchip,pipe-grf = <0x6c>;
|
status = "disabled";
|
reset-gpios = <0xfc 0xb 0x0>;
|
vpcie3v3-supply = <0x105>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x1b6>;
|
phandle = <0x484>;
|
|
legacy-interrupt-controller {
|
interrupt-controller;
|
#address-cells = <0x0>;
|
#interrupt-cells = <0x1>;
|
interrupt-parent = <0x1>;
|
interrupts = <0x0 0x104 0x1>;
|
phandle = <0x1b3>;
|
};
|
};
|
|
pcie@fe160000 {
|
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
|
#address-cells = <0x3>;
|
#size-cells = <0x2>;
|
bus-range = <0x10 0x1f>;
|
clocks = <0x2 0x14f 0x2 0x154 0x2 0x14a 0x2 0x159 0x2 0x15f 0x2 0x184>;
|
clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux", "pipe";
|
device_type = "pci";
|
interrupts = <0x0 0x102 0x4 0x0 0x101 0x4 0x0 0x100 0x4 0x0 0xff 0x4 0x0 0xfe 0x4>;
|
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
#interrupt-cells = <0x1>;
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
interrupt-map = <0x0 0x0 0x0 0x1 0x1b7 0x0 0x0 0x0 0x0 0x2 0x1b7 0x1 0x0 0x0 0x0 0x3 0x1b7 0x2 0x0 0x0 0x0 0x4 0x1b7 0x3>;
|
linux,pci-domain = <0x1>;
|
num-ib-windows = <0x10>;
|
num-ob-windows = <0x10>;
|
num-viewport = <0x8>;
|
max-link-speed = <0x3>;
|
msi-map = <0x1000 0x1b4 0x1000 0x1000>;
|
num-lanes = <0x2>;
|
phys = <0x1b5>;
|
phy-names = "pcie-phy";
|
power-domains = <0x57 0x22>;
|
ranges = <0x800 0x0 0xf1000000 0x0 0xf1000000 0x0 0x100000 0x81000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x100000 0x82000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0xe00000 0xc3000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>;
|
reg = <0x0 0xfe160000 0x0 0x10000 0xa 0x40400000 0x0 0x400000>;
|
reg-names = "pcie-apb", "pcie-dbi";
|
resets = <0x2 0x20e 0x2 0x21d>;
|
reset-names = "pcie", "periph";
|
rockchip,pipe-grf = <0x6c>;
|
status = "disabled";
|
phandle = <0x485>;
|
|
legacy-interrupt-controller {
|
interrupt-controller;
|
#address-cells = <0x0>;
|
#interrupt-cells = <0x1>;
|
interrupt-parent = <0x1>;
|
interrupts = <0x0 0xff 0x1>;
|
phandle = <0x1b7>;
|
};
|
};
|
|
pcie@fe170000 {
|
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
|
#address-cells = <0x3>;
|
#size-cells = <0x2>;
|
bus-range = <0x20 0x2f>;
|
clocks = <0x2 0x150 0x2 0x155 0x2 0x14b 0x2 0x15b 0x2 0x160 0x2 0x2c4>;
|
clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux", "pipe";
|
device_type = "pci";
|
interrupts = <0x0 0xf3 0x4 0x0 0xf2 0x4 0x0 0xf1 0x4 0x0 0xf0 0x4 0x0 0xef 0x4>;
|
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
#interrupt-cells = <0x1>;
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
interrupt-map = <0x0 0x0 0x0 0x1 0x1b8 0x0 0x0 0x0 0x0 0x2 0x1b8 0x1 0x0 0x0 0x0 0x3 0x1b8 0x2 0x0 0x0 0x0 0x4 0x1b8 0x3>;
|
linux,pci-domain = <0x2>;
|
num-ib-windows = <0x8>;
|
num-ob-windows = <0x8>;
|
num-viewport = <0x4>;
|
max-link-speed = <0x2>;
|
msi-map = <0x2000 0x104 0x2000 0x1000>;
|
num-lanes = <0x1>;
|
phys = <0x1b9 0x2>;
|
phy-names = "pcie-phy";
|
ranges = <0x800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0xe00000 0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
|
reg = <0x0 0xfe170000 0x0 0x10000 0xa 0x40800000 0x0 0x400000>;
|
reg-names = "pcie-apb", "pcie-dbi";
|
resets = <0x2 0x20f 0x2 0x21e>;
|
reset-names = "pcie", "periph";
|
rockchip,pipe-grf = <0x6c>;
|
status = "okay";
|
reset-gpios = <0xfc 0x5 0x0>;
|
vpcie3v3-supply = <0x105>;
|
phandle = <0x486>;
|
|
legacy-interrupt-controller {
|
interrupt-controller;
|
#address-cells = <0x0>;
|
#interrupt-cells = <0x1>;
|
interrupt-parent = <0x1>;
|
interrupts = <0x0 0xf0 0x1>;
|
phandle = <0x1b8>;
|
};
|
};
|
|
uio@fe1b0000 {
|
compatible = "rockchip,uio-gmac";
|
reg = <0x0 0xfe1b0000 0x0 0x10000>;
|
rockchip,ethernet = <0x1ba>;
|
status = "disabled";
|
phandle = <0x487>;
|
};
|
|
ethernet@fe1b0000 {
|
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
reg = <0x0 0xfe1b0000 0x0 0x10000>;
|
interrupts = <0x0 0xe3 0x4 0x0 0xe2 0x4>;
|
interrupt-names = "macirq", "eth_wake_irq";
|
rockchip,grf = <0xbc>;
|
rockchip,php_grf = <0x6c>;
|
clocks = <0x2 0x144 0x2 0x145 0x2 0x167 0x2 0x16c 0x2 0x142>;
|
clock-names = "stmmaceth", "clk_mac_ref", "pclk_mac", "aclk_mac", "ptp_ref";
|
resets = <0x2 0x20a>;
|
reset-names = "stmmaceth";
|
power-domains = <0x57 0x21>;
|
snps,mixed-burst;
|
snps,tso;
|
snps,axi-config = <0x1bb>;
|
snps,mtl-rx-config = <0x1bc>;
|
snps,mtl-tx-config = <0x1bd>;
|
status = "disabled";
|
phandle = <0x1ba>;
|
|
mdio {
|
compatible = "snps,dwmac-mdio";
|
#address-cells = <0x1>;
|
#size-cells = <0x0>;
|
phandle = <0x488>;
|
};
|
|
stmmac-axi-config {
|
snps,wr_osr_lmt = <0x4>;
|
snps,rd_osr_lmt = <0x8>;
|
snps,blen = <0x0 0x0 0x0 0x0 0x10 0x8 0x4>;
|
phandle = <0x1bb>;
|
};
|
|
rx-queues-config {
|
snps,rx-queues-to-use = <0x1>;
|
phandle = <0x1bc>;
|
|
queue0 {
|
};
|
};
|
|
tx-queues-config {
|
snps,tx-queues-to-use = <0x1>;
|
phandle = <0x1bd>;
|
|
queue0 {
|
};
|
};
|
};
|
|
sata@fe220000 {
|
compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
|
reg = <0x0 0xfe220000 0x0 0x1000>;
|
clocks = <0x2 0x172 0x2 0x16f 0x2 0x175 0x2 0x164 0x2 0x17f>;
|
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
interrupts = <0x0 0x112 0x4>;
|
interrupt-names = "hostc";
|
phys = <0x1b9 0x1>;
|
phy-names = "sata-phy";
|
ports-implemented = <0x1>;
|
status = "disabled";
|
phandle = <0x489>;
|
};
|
|
phy@fed70000 {
|
compatible = "rockchip,rk3588-hdptx-phy";
|
reg = <0x0 0xfed70000 0x0 0x2000>;
|
clocks = <0x2 0x2b5 0x2 0x268>;
|
clock-names = "ref", "apb";
|
resets = <0x2 0x486 0x2 0xc003f 0x2 0xc0040 0x2 0xc0041>;
|
reset-names = "apb", "init", "cmn", "lane";
|
rockchip,grf = <0x1be>;
|
#phy-cells = <0x0>;
|
status = "okay";
|
phandle = <0x1ac>;
|
};
|
|
hdmiphy@fed70000 {
|
compatible = "rockchip,rk3588-hdptx-phy-hdmi";
|
reg = <0x0 0xfed70000 0x0 0x2000>;
|
clocks = <0x2 0x2b5 0x2 0x268>;
|
clock-names = "ref", "apb";
|
resets = <0x2 0x491 0x2 0x486 0x2 0xc003f 0x2 0xc0040 0x2 0xc0041 0x2 0x48f 0x2 0x490>;
|
reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
|
rockchip,grf = <0x1be>;
|
#phy-cells = <0x0>;
|
status = "disabled";
|
phandle = <0x1a9>;
|
|
clk-port {
|
#clock-cells = <0x0>;
|
status = "okay";
|
phandle = <0x1a4>;
|
};
|
};
|
|
phy@fed90000 {
|
compatible = "rockchip,rk3588-usbdp-phy";
|
reg = <0x0 0xfed90000 0x0 0x10000>;
|
rockchip,u2phy-grf = <0x1bf>;
|
rockchip,usb-grf = <0x6a>;
|
rockchip,usbdpphy-grf = <0x1c0>;
|
rockchip,vo-grf = <0xf2>;
|
clocks = <0x2 0x2b6 0x2 0x280 0x2 0x26a 0x1c1>;
|
clock-names = "refclk", "immortal", "pclk", "utmi";
|
resets = <0x2 0x2f 0x2 0x30 0x2 0x31 0x2 0x32 0x2 0x484>;
|
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
status = "okay";
|
phandle = <0x48a>;
|
|
dp-port {
|
#phy-cells = <0x0>;
|
status = "okay";
|
phandle = <0x1a0>;
|
};
|
|
u3-port {
|
#phy-cells = <0x0>;
|
status = "okay";
|
phandle = <0x19f>;
|
};
|
};
|
|
phy@fee10000 {
|
compatible = "rockchip,rk3588-naneng-combphy";
|
reg = <0x0 0xfee10000 0x0 0x100>;
|
#phy-cells = <0x1>;
|
clocks = <0x2 0x2be 0x2 0x186 0x2 0x166>;
|
clock-names = "refclk", "apbclk", "phpclk";
|
assigned-clocks = <0x2 0x2be>;
|
assigned-clock-rates = <0x5f5e100>;
|
resets = <0x2 0x20006 0x2 0x4d7>;
|
reset-names = "combphy-apb", "combphy";
|
rockchip,pipe-grf = <0x6c>;
|
rockchip,pipe-phy-grf = <0x1c2>;
|
rockchip,pcie1ln-sel-bits = <0x100 0x0 0x0 0x0>;
|
status = "okay";
|
phandle = <0x1b9>;
|
};
|
|
phy@fee80000 {
|
compatible = "rockchip,rk3588-pcie3-phy";
|
reg = <0x0 0xfee80000 0x0 0x20000>;
|
#phy-cells = <0x0>;
|
clocks = <0x2 0x188>;
|
clock-names = "pclk";
|
resets = <0x2 0x2000a>;
|
reset-names = "phy";
|
rockchip,pipe-grf = <0x6c>;
|
rockchip,phy-grf = <0x1c3>;
|
status = "disabled";
|
rockchip,pcie30-phymode = <0x4>;
|
phandle = <0x1b5>;
|
};
|
|
adc-keys {
|
compatible = "adc-keys";
|
io-channels = <0x1c4 0x1>;
|
io-channel-names = "buttons";
|
keyup-threshold-microvolt = <0x1b7740>;
|
poll-interval = <0x64>;
|
phandle = <0x48b>;
|
|
vol-up-key {
|
label = "volume up";
|
linux,code = <0x73>;
|
press-threshold-microvolt = <0x4268>;
|
};
|
|
vol-down-key {
|
label = "volume down";
|
linux,code = <0x72>;
|
press-threshold-microvolt = <0x65ce8>;
|
};
|
|
menu-key {
|
label = "menu";
|
linux,code = <0x8b>;
|
press-threshold-microvolt = <0xd9490>;
|
};
|
|
back-key {
|
label = "back";
|
linux,code = <0x9e>;
|
press-threshold-microvolt = <0x12d838>;
|
};
|
};
|
|
backlight {
|
compatible = "pwm-backlight";
|
brightness-levels = <0x0 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>;
|
default-brightness-level = <0xc8>;
|
pwms = <0x1c5 0x0 0x61a8 0x0>;
|
status = "okay";
|
phandle = <0xee>;
|
};
|
|
backlight1 {
|
compatible = "pwm-backlight";
|
brightness-levels = <0x0 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>;
|
default-brightness-level = <0xc8>;
|
pwms = <0x1c6 0x0 0x61a8 0x0>;
|
status = "disabled";
|
phandle = <0xe9>;
|
};
|
|
bt-sco {
|
status = "disabled";
|
compatible = "delta,dfbmcs320";
|
#sound-dai-cells = <0x1>;
|
phandle = <0x1c8>;
|
};
|
|
bt-sound {
|
status = "disabled";
|
compatible = "simple-audio-card";
|
simple-audio-card,format = "dsp_a";
|
simple-audio-card,bitclock-inversion = <0x0>;
|
simple-audio-card,mclk-fs = <0x100>;
|
simple-audio-card,name = "rockchip,bt";
|
phandle = <0x48c>;
|
|
simple-audio-card,cpu {
|
sound-dai = <0x1c7>;
|
};
|
|
simple-audio-card,codec {
|
sound-dai = <0x1c8 0x1>;
|
};
|
};
|
|
hdmi0-sound {
|
status = "okay";
|
compatible = "rockchip,hdmi";
|
rockchip,mclk-fs = <0x80>;
|
rockchip,card-name = "rockchip-hdmi0";
|
rockchip,cpu = <0x1c9>;
|
rockchip,codec = <0x1ca>;
|
rockchip,jack-det;
|
phandle = <0x48d>;
|
};
|
|
hdmi1-sound {
|
status = "disabled";
|
compatible = "rockchip,hdmi";
|
rockchip,mclk-fs = <0x80>;
|
rockchip,card-name = "rockchip-hdmi1";
|
rockchip,cpu = <0x1cb>;
|
rockchip,codec = <0x1cc>;
|
rockchip,jack-det;
|
phandle = <0x48e>;
|
};
|
|
dp0-sound {
|
status = "disabled";
|
compatible = "rockchip,hdmi";
|
rockchip,card-name = "rockchip-dp0";
|
rockchip,mclk-fs = <0x200>;
|
rockchip,cpu = <0x1cd>;
|
rockchip,codec = <0x1ce 0x1>;
|
rockchip,jack-det;
|
phandle = <0x48f>;
|
};
|
|
dp1-sound {
|
status = "disabled";
|
compatible = "rockchip,hdmi";
|
rockchip,card-name = "rockchip-dp1";
|
rockchip,mclk-fs = <0x200>;
|
rockchip,cpu = <0x1cf>;
|
rockchip,codec = <0x1d0 0x1>;
|
rockchip,jack-det;
|
phandle = <0x490>;
|
};
|
|
leds {
|
compatible = "gpio-leds";
|
phandle = <0x491>;
|
|
sys_led {
|
gpios = <0x1b2 0x1e 0x0>;
|
linux,default-trigger = "heartbeat";
|
phandle = <0x492>;
|
};
|
};
|
|
spdif-tx0-dc {
|
status = "disabled";
|
compatible = "linux,spdif-dit";
|
#sound-dai-cells = <0x0>;
|
phandle = <0x1d2>;
|
};
|
|
spdif-tx0-sound {
|
status = "disabled";
|
compatible = "simple-audio-card";
|
simple-audio-card,mclk-fs = <0x80>;
|
simple-audio-card,name = "rockchip,spdif-tx0";
|
phandle = <0x493>;
|
|
simple-audio-card,cpu {
|
sound-dai = <0x1d1>;
|
};
|
|
simple-audio-card,codec {
|
sound-dai = <0x1d2>;
|
};
|
};
|
|
spdif-tx1-dc {
|
status = "disabled";
|
compatible = "linux,spdif-dit";
|
#sound-dai-cells = <0x0>;
|
phandle = <0x1d4>;
|
};
|
|
spdif-tx1-sound {
|
status = "disabled";
|
compatible = "simple-audio-card";
|
simple-audio-card,mclk-fs = <0x80>;
|
simple-audio-card,name = "rockchip,spdif-tx1";
|
phandle = <0x494>;
|
|
simple-audio-card,cpu {
|
sound-dai = <0x1d3>;
|
};
|
|
simple-audio-card,codec {
|
sound-dai = <0x1d4>;
|
};
|
};
|
|
test-power {
|
status = "okay";
|
};
|
|
vcc12v-dcin {
|
compatible = "regulator-fixed";
|
regulator-name = "vcc12v_dcin";
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0xb71b00>;
|
regulator-max-microvolt = <0xb71b00>;
|
phandle = <0x1d5>;
|
};
|
|
vcc5v0-sys {
|
compatible = "regulator-fixed";
|
regulator-name = "vcc5v0_sys";
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x4c4b40>;
|
regulator-max-microvolt = <0x4c4b40>;
|
vin-supply = <0x1d5>;
|
phandle = <0x6e>;
|
};
|
|
vcc5v0-usbdcin {
|
compatible = "regulator-fixed";
|
regulator-name = "vcc5v0_usbdcin";
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x4c4b40>;
|
regulator-max-microvolt = <0x4c4b40>;
|
vin-supply = <0x1d5>;
|
phandle = <0x1d6>;
|
};
|
|
vcc5v0-usb {
|
compatible = "regulator-fixed";
|
regulator-name = "vcc5v0_usb";
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x4c4b40>;
|
regulator-max-microvolt = <0x4c4b40>;
|
vin-supply = <0x1d6>;
|
phandle = <0x1e2>;
|
};
|
|
reserved-memory {
|
#address-cells = <0x2>;
|
#size-cells = <0x2>;
|
ranges;
|
|
cma {
|
compatible = "shared-dma-pool";
|
reusable;
|
reg = <0x0 0x10000000 0x0 0x8000000>;
|
linux,cma-default;
|
size = <0x0 0x800000>;
|
};
|
|
drm-logo@00000000 {
|
compatible = "rockchip,drm-logo";
|
reg = <0x0 0x0 0x0 0x0>;
|
phandle = <0x32>;
|
};
|
|
drm-cubic-lut@00000000 {
|
compatible = "rockchip,drm-cubic-lut";
|
reg = <0x0 0x0 0x0 0x0>;
|
phandle = <0x495>;
|
};
|
|
ramoops@110000 {
|
compatible = "ramoops";
|
reg = <0x0 0x110000 0x0 0xf0000>;
|
record-size = <0x20000>;
|
console-size = <0x80000>;
|
ftrace-size = <0x0>;
|
pmsg-size = <0x50000>;
|
phandle = <0x496>;
|
};
|
};
|
|
es8316-sound {
|
status = "okay";
|
compatible = "rockchip,multicodecs-card";
|
rockchip,card-name = "rockchip-es8316";
|
rockchip,format = "i2s";
|
rockchip,mclk-fs = <0x100>;
|
rockchip,cpu = <0x1d7>;
|
rockchip,codec = <0x1d8>;
|
poll-interval = <0x64>;
|
io-channels = <0x1c4 0x3>;
|
io-channel-names = "adc-detect";
|
keyup-threshold-microvolt = <0x1b7740>;
|
pinctrl-0 = <0x1d9>;
|
pinctrl-names = "default";
|
phandle = <0x497>;
|
|
play-pause-key {
|
label = "playpause";
|
linux,code = <0xa4>;
|
press-threshold-microvolt = <0x7d0>;
|
};
|
};
|
|
pwm-fan {
|
compatible = "pwm-fan";
|
#cooling-cells = <0x2>;
|
pwms = <0x1c5 0x0 0xc350 0x0>;
|
cooling-levels = <0x0 0x32 0x64 0x96 0xc8 0xff>;
|
rockchip,temp-trips = <0xc350 0x1 0xd6d8 0x2 0xea60 0x3 0xfde8 0x4 0x11170 0x5>;
|
phandle = <0x498>;
|
};
|
|
hdmiin-sound {
|
compatible = "rockchip,hdmi";
|
rockchip,mclk-fs = <0x80>;
|
rockchip,format = "i2s";
|
rockchip,bitclock-master = <0x1da>;
|
rockchip,frame-master = <0x1da>;
|
rockchip,card-name = "rockchip,hdmiin";
|
rockchip,cpu = <0x1db>;
|
rockchip,codec = <0x1da 0x0>;
|
rockchip,jack-det;
|
};
|
|
pcie20-avdd0v85 {
|
compatible = "regulator-fixed";
|
regulator-name = "pcie20_avdd0v85";
|
regulator-boot-on;
|
regulator-always-on;
|
regulator-min-microvolt = <0xcf850>;
|
regulator-max-microvolt = <0xcf850>;
|
vin-supply = <0x1dc>;
|
phandle = <0x499>;
|
};
|
|
pcie20-avdd1v8 {
|
compatible = "regulator-fixed";
|
regulator-name = "pcie20_avdd1v8";
|
regulator-boot-on;
|
regulator-always-on;
|
regulator-min-microvolt = <0x1b7740>;
|
regulator-max-microvolt = <0x1b7740>;
|
vin-supply = <0x1dd>;
|
phandle = <0x49a>;
|
};
|
|
pcie30-avdd0v75 {
|
compatible = "regulator-fixed";
|
regulator-name = "pcie30_avdd0v75";
|
regulator-boot-on;
|
regulator-always-on;
|
regulator-min-microvolt = <0xb71b0>;
|
regulator-max-microvolt = <0xb71b0>;
|
vin-supply = <0x1de>;
|
phandle = <0x49b>;
|
};
|
|
pcie30-avdd1v8 {
|
compatible = "regulator-fixed";
|
regulator-name = "pcie30_avdd1v8";
|
regulator-boot-on;
|
regulator-always-on;
|
regulator-min-microvolt = <0x1b7740>;
|
regulator-max-microvolt = <0x1b7740>;
|
vin-supply = <0x1dd>;
|
phandle = <0x49c>;
|
};
|
|
sdio-pwrseq {
|
compatible = "mmc-pwrseq-simple";
|
clocks = <0x1df>;
|
clock-names = "ext_clock";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x1e0>;
|
post-power-on-delay-ms = <0xc8>;
|
reset-gpios = <0x1b2 0x16 0x1>;
|
phandle = <0x11a>;
|
};
|
|
rk-headset {
|
status = "okay";
|
compatible = "rockchip_headset";
|
headset_gpio = <0x108 0x1d 0x0>;
|
spk_ctl_gpio = <0xfc 0xc 0x1>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x1e1>;
|
io-channels = <0x1c4 0x3>;
|
phandle = <0x49d>;
|
};
|
|
vcc-1v1-nldo-s3 {
|
compatible = "regulator-fixed";
|
regulator-name = "vcc_1v1_nldo_s3";
|
regulator-always-on;
|
regulator-boot-on;
|
regulator-min-microvolt = <0x10c8e0>;
|
regulator-max-microvolt = <0x10c8e0>;
|
vin-supply = <0x6e>;
|
phandle = <0x162>;
|
};
|
|
vcc3v3-lcd0-n {
|
compatible = "regulator-fixed";
|
regulator-name = "vcc3v3_lcd0_n";
|
regulator-always-on;
|
regulator-boot-on;
|
enable-active-high;
|
gpio = <0x1b2 0x14 0x0>;
|
vin-supply = <0x17e>;
|
phandle = <0xef>;
|
};
|
|
vcc3v3-pcie30 {
|
compatible = "regulator-fixed";
|
regulator-name = "vcc3v3_pcie30";
|
regulator-min-microvolt = <0x325aa0>;
|
regulator-max-microvolt = <0x325aa0>;
|
enable-active-high;
|
startup-delay-us = <0x1388>;
|
vin-supply = <0x1d5>;
|
phandle = <0x105>;
|
};
|
|
vcc5v0-host {
|
compatible = "regulator-fixed";
|
regulator-name = "vcc5v0_host";
|
regulator-boot-on;
|
regulator-always-on;
|
regulator-min-microvolt = <0x4c4b40>;
|
regulator-max-microvolt = <0x4c4b40>;
|
enable-active-high;
|
gpio = <0xfc 0x8 0x0>;
|
vin-supply = <0x1e2>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x1e3>;
|
phandle = <0x6b>;
|
};
|
|
vcc-3v3-sd-s0-regulator {
|
compatible = "regulator-fixed";
|
regulator-name = "vcc_3v3_sd_s0";
|
enable-active-high;
|
phandle = <0x118>;
|
};
|
|
wireless-bluetooth {
|
compatible = "bluetooth-platdata";
|
clocks = <0x1df>;
|
clock-names = "ext_clock";
|
uart_rts_gpios = <0xfc 0x14 0x1>;
|
pinctrl-names = "default", "rts_gpio";
|
pinctrl-0 = <0x1e4 0x1e5>;
|
pinctrl-1 = <0x1e6>;
|
BT,reset_gpio = <0x15b 0xa 0x0>;
|
status = "okay";
|
phandle = <0x49e>;
|
};
|
|
wireless-wlan {
|
compatible = "wlan-platdata";
|
wifi_chip_type = "ap6398s";
|
status = "okay";
|
phandle = <0x49f>;
|
};
|
|
ndj_io_init {
|
compatible = "nk_io_control";
|
pinctrl-names = "default";
|
pinctrl-0 = <0x1e7>;
|
|
vcc_12v {
|
gpio_num = <0x15b 0x1b 0x0>;
|
gpio_function = <0x0>;
|
};
|
|
vcc_3v {
|
gpio_num = <0xfc 0x1 0x0>;
|
gpio_function = <0x0>;
|
};
|
|
hub_5V_reset {
|
gpio_num = <0xfc 0xe 0x0>;
|
gpio_function = <0x3>;
|
};
|
|
4g_power {
|
gpio_num = <0x15b 0x16 0x0>;
|
gpio_function = <0x0>;
|
};
|
|
wake_wifi_bt {
|
gpio_num = <0x1e8 0xd 0x1>;
|
gpio_function = <0x0>;
|
};
|
|
air_mode_4g {
|
gpio_num = <0x1e8 0xc 0x1>;
|
gpio_function = <0x0>;
|
};
|
|
reset_4g {
|
gpio_num = <0x1e8 0x13 0x1>;
|
gpio_function = <0x3>;
|
};
|
};
|
|
panel {
|
compatible = "simple-panel";
|
backlight = <0xee>;
|
power-supply = <0xef>;
|
vcc-5v-gpio = <0xfc 0xd 0x0>;
|
enable-gpios = <0x108 0x16 0x0>;
|
reset-gpios = <0x1b2 0xd 0x1>;
|
edp-bl-gpios = <0x108 0xa 0x0>;
|
edp-bl-en = <0x108 0x6 0x0>;
|
bus-format = <0x100a>;
|
bpc = <0x8>;
|
prepare-delay-ms = <0xc8>;
|
enable-delay-ms = <0x14>;
|
lvds-gpio0 = <0x1e8 0x15 0x0>;
|
lvds-gpio1 = <0xfc 0x12 0x0>;
|
lvds-gpio2 = <0xfc 0x13 0x0>;
|
lvds-gpio3 = <0xfc 0x16 0x0>;
|
nodka-lvds = <0xf>;
|
phandle = <0x4a0>;
|
|
display-timings {
|
native-mode = <0x1e9>;
|
|
timing0 {
|
clock-frequency = <0x459e440>;
|
hactive = <0x500>;
|
vactive = <0x320>;
|
hfront-porch = <0x46>;
|
hsync-len = <0x2>;
|
hback-porch = <0x58>;
|
vfront-porch = <0x3>;
|
vsync-len = <0xe>;
|
vback-porch = <0x17>;
|
hsync-active = <0x0>;
|
vsync-active = <0x0>;
|
de-active = <0x0>;
|
pixelclk-active = <0x0>;
|
phandle = <0x1e9>;
|
};
|
};
|
|
port {
|
|
endpoint {
|
remote-endpoint = <0x1ea>;
|
phandle = <0x1af>;
|
};
|
};
|
};
|
|
chosen {
|
bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTUUID=614e0000-0000 rw rootwait net.ifnames=0";
|
phandle = <0x4a1>;
|
};
|
|
cspmu@fd10c000 {
|
compatible = "rockchip,cspmu";
|
reg = <0x0 0xfd10c000 0x0 0x1000 0x0 0xfd10d000 0x0 0x1000 0x0 0xfd10e000 0x0 0x1000 0x0 0xfd10f000 0x0 0x1000 0x0 0xfd12c000 0x0 0x1000 0x0 0xfd12d000 0x0 0x1000 0x0 0xfd12e000 0x0 0x1000 0x0 0xfd12f000 0x0 0x1000>;
|
phandle = <0x4a2>;
|
};
|
|
debug@fd104000 {
|
compatible = "rockchip,debug";
|
reg = <0x0 0xfd104000 0x0 0x1000 0x0 0xfd105000 0x0 0x1000 0x0 0xfd106000 0x0 0x1000 0x0 0xfd107000 0x0 0x1000 0x0 0xfd124000 0x0 0x1000 0x0 0xfd125000 0x0 0x1000 0x0 0xfd126000 0x0 0x1000 0x0 0xfd127000 0x0 0x1000>;
|
phandle = <0x4a3>;
|
};
|
|
fiq-debugger {
|
compatible = "rockchip,fiq-debugger";
|
rockchip,serial-id = <0x2>;
|
rockchip,wake-irq = <0x0>;
|
rockchip,irq-mode-enable = <0x1>;
|
rockchip,baudrate = <0x16e360>;
|
interrupts = <0x0 0x1a7 0x8>;
|
pinctrl-names = "default";
|
pinctrl-0 = <0x1eb>;
|
status = "okay";
|
phandle = <0x4a4>;
|
};
|
|
__symbols__ {
|
spll = "/clocks/spll";
|
xin32k = "/clocks/xin32k";
|
xin24m = "/clocks/xin24m";
|
hclk_vo1 = "/clocks/hclk_vo1@fd7c08ec";
|
aclk_vdpu_low_pre = "/clocks/aclk_vdpu_low_pre@fd7c08b0";
|
hclk_vo0 = "/clocks/hclk_vo0@fd7c08dc";
|
hclk_usb = "/clocks/hclk_usb@fd7c08a8";
|
hclk_nvm = "/clocks/hclk_nvm@fd7c087c";
|
aclk_usb = "/clocks/aclk_usb@fd7c08a8";
|
hclk_isp1_pre = "/clocks/hclk_isp1_pre@fd7c0868";
|
aclk_isp1_pre = "/clocks/aclk_isp1_pre@fd7c0868";
|
aclk_rkvdec0_pre = "/clocks/aclk_rkvdec0_pre@fd7c08a0";
|
hclk_rkvdec0_pre = "/clocks/hclk_rkvdec0_pre@fd7c08a0";
|
aclk_rkvdec1_pre = "/clocks/aclk_rkvdec1_pre@fd7c08a4";
|
hclk_rkvdec1_pre = "/clocks/hclk_rkvdec1_pre@fd7c08a4";
|
aclk_jpeg_decoder_pre = "/clocks/aclk_jpeg_decoder_pre@fd7c08b0";
|
aclk_rkvenc1_pre = "/clocks/aclk_rkvenc1_pre@fd7c08c0";
|
hclk_rkvenc1_pre = "/clocks/hclk_rkvenc1_pre@fd7c08c0";
|
aclk_hdcp0_pre = "/clocks/aclk_hdcp0_pre@fd7c08dc";
|
aclk_hdcp1_pre = "/clocks/aclk_hdcp1_pre@fd7c08ec";
|
pclk_av1_pre = "/clocks/pclk_av1_pre@fd7c0910";
|
aclk_av1_pre = "/clocks/aclk_av1_pre@fd7c0910";
|
hclk_sdio_pre = "/clocks/hclk_sdio_pre@fd7c092c";
|
pclk_vo0_grf = "/clocks/pclk_vo0_grf@fd7c08dc";
|
pclk_vo1_grf = "/clocks/pclk_vo1_grf@fd7c08ec";
|
mclkin_i2s0 = "/clocks/mclkin-i2s0";
|
mclkin_i2s1 = "/clocks/mclkin-i2s1";
|
mclkin_i2s2 = "/clocks/mclkin-i2s2";
|
mclkin_i2s3 = "/clocks/mclkin-i2s3";
|
mclkout_i2s0 = "/clocks/mclkout-i2s0@fd58c318";
|
mclkout_i2s1 = "/clocks/mclkout-i2s1@fd58c318";
|
mclkout_i2s1m1 = "/clocks/mclkout-i2s1@fd58a000";
|
mclkout_i2s2 = "/clocks/mclkout-i2s2@fd58c318";
|
mclkout_i2s3 = "/clocks/mclkout-i2s3@fd58c318";
|
cpu_l0 = "/cpus/cpu@0";
|
cpu_l1 = "/cpus/cpu@100";
|
cpu_l2 = "/cpus/cpu@200";
|
cpu_l3 = "/cpus/cpu@300";
|
cpu_b0 = "/cpus/cpu@400";
|
cpu_b1 = "/cpus/cpu@500";
|
cpu_b2 = "/cpus/cpu@600";
|
cpu_b3 = "/cpus/cpu@700";
|
CPU_SLEEP = "/cpus/idle-states/cpu-sleep";
|
l2_cache_l0 = "/cpus/l2-cache-l0";
|
l2_cache_l1 = "/cpus/l2-cache-l1";
|
l2_cache_l2 = "/cpus/l2-cache-l2";
|
l2_cache_l3 = "/cpus/l2-cache-l3";
|
l2_cache_b0 = "/cpus/l2-cache-b0";
|
l2_cache_b1 = "/cpus/l2-cache-b1";
|
l2_cache_b2 = "/cpus/l2-cache-b2";
|
l2_cache_b3 = "/cpus/l2-cache-b3";
|
l3_cache = "/cpus/l3-cache";
|
cluster0_opp_table = "/cluster0-opp-table";
|
cluster1_opp_table = "/cluster1-opp-table";
|
cluster2_opp_table = "/cluster2-opp-table";
|
arm_pmu = "/arm-pmu";
|
csi2_dcphy0 = "/csi2-dcphy0";
|
csi2_dcphy1 = "/csi2-dcphy1";
|
csi2_dphy0 = "/csi2-dphy0";
|
csi2_dphy1 = "/csi2-dphy1";
|
csi2_dphy2 = "/csi2-dphy2";
|
csi2_dphy3 = "/csi2-dphy3";
|
csi2_dphy4 = "/csi2-dphy4";
|
csi2_dphy5 = "/csi2-dphy5";
|
display_subsystem = "/display-subsystem";
|
route_dp0 = "/display-subsystem/route/route-dp0";
|
route_dsi0 = "/display-subsystem/route/route-dsi0";
|
route_dsi1 = "/display-subsystem/route/route-dsi1";
|
route_edp0 = "/display-subsystem/route/route-edp0";
|
route_edp1 = "/display-subsystem/route/route-edp1";
|
route_hdmi0 = "/display-subsystem/route/route-hdmi0";
|
route_rgb = "/display-subsystem/route/route-rgb";
|
route_dp1 = "/display-subsystem/route/route-dp1";
|
route_hdmi1 = "/display-subsystem/route/route-hdmi1";
|
dmc = "/dmc";
|
dmc_opp_table = "/dmc-opp-table";
|
scmi = "/firmware/scmi";
|
scmi_clk = "/firmware/scmi/protocol@14";
|
scmi_reset = "/firmware/scmi/protocol@16";
|
sdei = "/firmware/sdei";
|
optee = "/firmware/optee";
|
jpege_ccu = "/jpege-ccu";
|
mipi_dcphy1 = "/mipi-dcphy-dummy";
|
mipi_dcphy0 = "/mipi-dcphy-dummy";
|
mipi0_csi2 = "/mipi0-csi2";
|
mipi1_csi2 = "/mipi1-csi2";
|
mipi2_csi2 = "/mipi2-csi2";
|
mipi3_csi2 = "/mipi3-csi2";
|
mipi4_csi2 = "/mipi4-csi2";
|
mipi5_csi2 = "/mipi5-csi2";
|
mpp_srv = "/mpp-srv";
|
rkcif_dvp = "/rkcif-dvp";
|
rkcif_dvp_sditf = "/rkcif-dvp-sditf";
|
rkcif_mipi_lvds = "/rkcif-mipi-lvds";
|
rkcif_mipi_lvds_sditf = "/rkcif-mipi-lvds-sditf";
|
rkcif_mipi_lvds_sditf_vir1 = "/rkcif-mipi-lvds-sditf-vir1";
|
rkcif_mipi_lvds_sditf_vir2 = "/rkcif-mipi-lvds-sditf-vir2";
|
rkcif_mipi_lvds_sditf_vir3 = "/rkcif-mipi-lvds-sditf-vir3";
|
rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1";
|
rkcif_mipi_lvds1_sditf = "/rkcif-mipi-lvds1-sditf";
|
rkcif_mipi_lvds1_sditf_vir1 = "/rkcif-mipi-lvds1-sditf-vir1";
|
rkcif_mipi_lvds1_sditf_vir2 = "/rkcif-mipi-lvds1-sditf-vir2";
|
rkcif_mipi_lvds1_sditf_vir3 = "/rkcif-mipi-lvds1-sditf-vir3";
|
rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2";
|
rkcif_mipi_lvds2_sditf = "/rkcif-mipi-lvds2-sditf";
|
rkcif_mipi_lvds2_sditf_vir1 = "/rkcif-mipi-lvds2-sditf-vir1";
|
rkcif_mipi_lvds2_sditf_vir2 = "/rkcif-mipi-lvds2-sditf-vir2";
|
rkcif_mipi_lvds2_sditf_vir3 = "/rkcif-mipi-lvds2-sditf-vir3";
|
rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3";
|
rkcif_mipi_lvds3_sditf = "/rkcif-mipi-lvds3-sditf";
|
rkcif_mipi_lvds3_sditf_vir1 = "/rkcif-mipi-lvds3-sditf-vir1";
|
rkcif_mipi_lvds3_sditf_vir2 = "/rkcif-mipi-lvds3-sditf-vir2";
|
rkcif_mipi_lvds3_sditf_vir3 = "/rkcif-mipi-lvds3-sditf-vir3";
|
rkisp0_vir0 = "/rkisp0-vir0";
|
rkisp0_vir1 = "/rkisp0-vir1";
|
rkisp0_vir2 = "/rkisp0-vir2";
|
rkisp0_vir3 = "/rkisp0-vir3";
|
rkisp1_vir0 = "/rkisp1-vir0";
|
rkisp1_vir1 = "/rkisp1-vir1";
|
rkisp1_vir2 = "/rkisp1-vir2";
|
rkisp1_vir3 = "/rkisp1-vir3";
|
rkispp0_vir0 = "/rkispp0-vir0";
|
rkispp1_vir0 = "/rkispp1-vir0";
|
rkvenc_ccu = "/rkvenc-ccu";
|
rockchip_suspend = "/rockchip-suspend";
|
rockchip_system_monitor = "/rockchip-system-monitor";
|
thermal_zones = "/thermal-zones";
|
soc_thermal = "/thermal-zones/soc-thermal";
|
threshold = "/thermal-zones/soc-thermal/trips/trip-point-0";
|
target = "/thermal-zones/soc-thermal/trips/trip-point-1";
|
soc_crit = "/thermal-zones/soc-thermal/trips/soc-crit";
|
bigcore0_thermal = "/thermal-zones/bigcore0-thermal";
|
bigcore1_thermal = "/thermal-zones/bigcore1-thermal";
|
little_core_thermal = "/thermal-zones/littlecore-thermal";
|
center_thermal = "/thermal-zones/center-thermal";
|
gpu_thermal = "/thermal-zones/gpu-thermal";
|
npu_thermal = "/thermal-zones/npu-thermal";
|
scmi_shmem = "/sram@10f000/sram@0";
|
gpu = "/gpu@fb000000";
|
gpu_opp_table = "/gpu-opp-table";
|
usbdrd3_0 = "/usbdrd3_0";
|
usbdrd_dwc3_0 = "/usbdrd3_0/usb@fc000000";
|
usb_host0_ehci = "/usb@fc800000";
|
usb_host0_ohci = "/usb@fc840000";
|
usb_host1_ehci = "/usb@fc880000";
|
usb_host1_ohci = "/usb@fc8c0000";
|
mmu600_pcie = "/iommu@fc900000";
|
mmu600_php = "/iommu@fcb00000";
|
usbhost3_0 = "/usbhost3_0";
|
usbhost_dwc3_0 = "/usbhost3_0/usb@fcd00000";
|
pmu0_grf = "/syscon@fd588000";
|
reboot_mode = "/syscon@fd588000/reboot-mode";
|
pmu1_grf = "/syscon@fd58a000";
|
sys_grf = "/syscon@fd58c000";
|
rgb = "/syscon@fd58c000/rgb";
|
rgb_in_vp3 = "/syscon@fd58c000/rgb/ports/port@0/endpoint@2";
|
bigcore0_grf = "/syscon@fd590000";
|
bigcore1_grf = "/syscon@fd592000";
|
litcore_grf = "/syscon@fd594000";
|
dsu_grf = "/syscon@fd598000";
|
gpu_grf = "/syscon@fd5a0000";
|
npu_grf = "/syscon@fd5a2000";
|
vop_grf = "/syscon@fd5a4000";
|
vo0_grf = "/syscon@fd5a6000";
|
vo1_grf = "/syscon@fd5a8000";
|
usb_grf = "/syscon@fd5ac000";
|
php_grf = "/syscon@fd5b0000";
|
mipidphy0_grf = "/syscon@fd5b4000";
|
mipidphy1_grf = "/syscon@fd5b5000";
|
pipe_phy0_grf = "/syscon@fd5bc000";
|
pipe_phy2_grf = "/syscon@fd5c4000";
|
usbdpphy0_grf = "/syscon@fd5c8000";
|
usb2phy0_grf = "/syscon@fd5d0000";
|
u2phy0 = "/syscon@fd5d0000/usb2-phy@0";
|
u2phy0_otg = "/syscon@fd5d0000/usb2-phy@0/otg-port";
|
usb2phy2_grf = "/syscon@fd5d8000";
|
u2phy2 = "/syscon@fd5d8000/usb2-phy@8000";
|
u2phy2_host = "/syscon@fd5d8000/usb2-phy@8000/host-port";
|
usb2phy3_grf = "/syscon@fd5dc000";
|
u2phy3 = "/syscon@fd5dc000/usb2-phy@c000";
|
u2phy3_host = "/syscon@fd5dc000/usb2-phy@c000/host-port";
|
hdptxphy0_grf = "/syscon@fd5e0000";
|
mipidcphy0_grf = "/syscon@fd5e8000";
|
mipidcphy1_grf = "/syscon@fd5ec000";
|
ioc = "/syscon@fd5f0000";
|
cru = "/clock-controller@fd7c0000";
|
i2c0 = "/i2c@fd880000";
|
vdd_cpu_big0_s0 = "/i2c@fd880000/rk8602@42";
|
vdd_cpu_big0_mem_s0 = "/i2c@fd880000/rk8602@42";
|
vdd_cpu_big1_s0 = "/i2c@fd880000/rk8603@43";
|
vdd_cpu_big1_mem_s0 = "/i2c@fd880000/rk8603@43";
|
uart0 = "/serial@fd890000";
|
pwm0 = "/pwm@fd8b0000";
|
pwm1 = "/pwm@fd8b0010";
|
pwm2 = "/pwm@fd8b0020";
|
pwm3 = "/pwm@fd8b0030";
|
pmu = "/power-management@fd8d8000";
|
power = "/power-management@fd8d8000/power-controller";
|
rknpu = "/npu@fdab0000";
|
npu_opp_table = "/npu-opp-table";
|
rknpu_mmu = "/iommu@fdab9000";
|
vepu = "/vepu@fdb50000";
|
vdpu = "/vdpu@fdb50400";
|
vdpu_mmu = "/iommu@fdb50800";
|
avsd = "/avsd-plus@fdb51000";
|
rga3_core0 = "/rga@fdb60000";
|
rga3_0_mmu = "/iommu@fdb60f00";
|
rga3_core1 = "/rga@fdb70000";
|
rga3_1_mmu = "/iommu@fdb70f00";
|
rga2 = "/rga@fdb80000";
|
jpegd = "/jpegd@fdb90000";
|
jpegd_mmu = "/iommu@fdb90480";
|
jpege0 = "/jpege-core@fdba0000";
|
jpege0_mmu = "/iommu@fdba0800";
|
jpege1 = "/jpege-core@fdba4000";
|
jpege1_mmu = "/iommu@fdba4800";
|
jpege2 = "/jpege-core@fdba8000";
|
jpege2_mmu = "/iommu@fdba8800";
|
jpege3 = "/jpege-core@fdbac000";
|
jpege3_mmu = "/iommu@fdbac800";
|
iep = "/iep@fdbb0000";
|
iep_mmu = "/iommu@fdbb0800";
|
rkvenc0 = "/rkvenc-core@fdbd0000";
|
rkvenc0_mmu = "/iommu@fdbdf000";
|
rkvenc1 = "/rkvenc-core@fdbe0000";
|
rkvenc1_mmu = "/iommu@fdbef000";
|
venc_opp_table = "/venc-opp-table";
|
rkvdec_ccu = "/rkvdec-ccu@fdc30000";
|
rkvdec0 = "/rkvdec-core@fdc38000";
|
rkvdec0_mmu = "/iommu@fdc38700";
|
rkvdec1 = "/rkvdec-core@fdc48000";
|
rkvdec1_mmu = "/iommu@fdc48700";
|
av1d = "/av1d@fdc70000";
|
av1d_mmu = "/iommu@fdca0000";
|
rkisp_unite = "/rkisp-unite@fdcb0000";
|
rkisp0 = "/rkisp@fdcb0000";
|
rkisp_unite_mmu = "/rkisp-unite-mmu@fdcb7f00";
|
isp0_mmu = "/iommu@fdcb7f00";
|
rkisp1 = "/rkisp@fdcc0000";
|
isp1_mmu = "/iommu@fdcc7f00";
|
rkispp0 = "/rkispp@fdcd0000";
|
fec0_mmu = "/iommu@fdcd0f00";
|
rkispp1 = "/rkispp@fdcd8000";
|
fec1_mmu = "/iommu@fdcd8f00";
|
rkcif = "/rkcif@fdce0000";
|
rkcif_mmu = "/iommu@fdce0800";
|
mipi0_csi2_hw = "/mipi0-csi2-hw@fdd10000";
|
mipi1_csi2_hw = "/mipi1-csi2-hw@fdd20000";
|
mipi2_csi2_hw = "/mipi2-csi2-hw@fdd30000";
|
mipi3_csi2_hw = "/mipi3-csi2-hw@fdd40000";
|
mipi4_csi2_hw = "/mipi4-csi2-hw@fdd50000";
|
mipi5_csi2_hw = "/mipi5-csi2-hw@fdd60000";
|
vop = "/vop@fdd90000";
|
vop_out = "/vop@fdd90000/ports";
|
vp0 = "/vop@fdd90000/ports/port@0";
|
vp0_out_dp0 = "/vop@fdd90000/ports/port@0/endpoint@0";
|
vp0_out_edp0 = "/vop@fdd90000/ports/port@0/endpoint@1";
|
vp0_out_hdmi0 = "/vop@fdd90000/ports/port@0/endpoint@2";
|
vp0_out_dp1 = "/vop@fdd90000/ports/port@0/endpoint@3";
|
vp0_out_edp1 = "/vop@fdd90000/ports/port@0/endpoint@4";
|
vp0_out_hdmi1 = "/vop@fdd90000/ports/port@0/endpoint@5";
|
vp1 = "/vop@fdd90000/ports/port@1";
|
vp1_out_dp0 = "/vop@fdd90000/ports/port@1/endpoint@0";
|
vp1_out_edp0 = "/vop@fdd90000/ports/port@1/endpoint@1";
|
vp1_out_hdmi0 = "/vop@fdd90000/ports/port@1/endpoint@2";
|
vp1_out_dp1 = "/vop@fdd90000/ports/port@1/endpoint@3";
|
vp1_out_edp1 = "/vop@fdd90000/ports/port@1/endpoint@4";
|
vp1_out_hdmi1 = "/vop@fdd90000/ports/port@1/endpoint@5";
|
vp2 = "/vop@fdd90000/ports/port@2";
|
vp2_out_dp0 = "/vop@fdd90000/ports/port@2/endpoint@0";
|
vp2_out_edp0 = "/vop@fdd90000/ports/port@2/endpoint@1";
|
vp2_out_hdmi0 = "/vop@fdd90000/ports/port@2/endpoint@2";
|
vp2_out_dsi0 = "/vop@fdd90000/ports/port@2/endpoint@3";
|
vp2_out_dsi1 = "/vop@fdd90000/ports/port@2/endpoint@4";
|
vp2_out_dp1 = "/vop@fdd90000/ports/port@2/endpoint@5";
|
vp2_out_edp1 = "/vop@fdd90000/ports/port@2/endpoint@6";
|
vp2_out_hdmi1 = "/vop@fdd90000/ports/port@2/endpoint@7";
|
vp3 = "/vop@fdd90000/ports/port@3";
|
vp3_out_dsi0 = "/vop@fdd90000/ports/port@3/endpoint@0";
|
vp3_out_dsi1 = "/vop@fdd90000/ports/port@3/endpoint@1";
|
vp3_out_rgb = "/vop@fdd90000/ports/port@3/endpoint@2";
|
vop_mmu = "/iommu@fdd97e00";
|
spdif_tx2 = "/spdif-tx@fddb0000";
|
i2s4_8ch = "/i2s@fddc0000";
|
spdif_tx3 = "/spdif-tx@fdde0000";
|
i2s5_8ch = "/i2s@fddf0000";
|
i2s9_8ch = "/i2s@fddfc000";
|
spdif_rx0 = "/spdif-rx@fde08000";
|
dsi0 = "/dsi@fde20000";
|
dsi0_in = "/dsi@fde20000/ports/port@0";
|
dsi0_in_vp2 = "/dsi@fde20000/ports/port@0/endpoint@0";
|
dsi0_in_vp3 = "/dsi@fde20000/ports/port@0/endpoint@1";
|
dsi_out_panel = "/dsi@fde20000/ports/port@1/endpoint";
|
dsi0_panel = "/dsi@fde20000/panel@0";
|
disp_timings0 = "/dsi@fde20000/panel@0/display-timings";
|
dsi0_timing0 = "/dsi@fde20000/panel@0/display-timings/timing0";
|
panel_in_dsi = "/dsi@fde20000/panel@0/ports/port@0/endpoint";
|
dsi1 = "/dsi@fde30000";
|
dsi1_in = "/dsi@fde30000/ports/port@0";
|
dsi1_in_vp2 = "/dsi@fde30000/ports/port@0/endpoint@0";
|
dsi1_in_vp3 = "/dsi@fde30000/ports/port@0/endpoint@1";
|
dsi1_out_panel = "/dsi@fde30000/ports/port@1/endpoint";
|
dsi1_panel = "/dsi@fde30000/panel@0";
|
disp_timings1 = "/dsi@fde30000/panel@0/display-timings";
|
dsi1_timing0 = "/dsi@fde30000/panel@0/display-timings/timing0";
|
panel_in_dsi1 = "/dsi@fde30000/panel@0/ports/port@0/endpoint";
|
hdcp0 = "/hdcp@fde40000";
|
dp0 = "/dp@fde50000";
|
dp0_in_vp0 = "/dp@fde50000/ports/port@0/endpoint@0";
|
dp0_in_vp1 = "/dp@fde50000/ports/port@0/endpoint@1";
|
dp0_in_vp2 = "/dp@fde50000/ports/port@0/endpoint@2";
|
dp0_out = "/dp@fde50000/ports/port@1/endpoint";
|
hdcp1 = "/hdcp@fde70000";
|
hdmi0 = "/hdmi@fde80000";
|
hdmi0_in = "/hdmi@fde80000/ports/port@0";
|
hdmi0_in_vp0 = "/hdmi@fde80000/ports/port@0/endpoint@0";
|
hdmi0_in_vp1 = "/hdmi@fde80000/ports/port@0/endpoint@1";
|
hdmi0_in_vp2 = "/hdmi@fde80000/ports/port@0/endpoint@2";
|
edp0 = "/edp@fdec0000";
|
edp0_in_vp0 = "/edp@fdec0000/ports/port@0/endpoint@0";
|
edp0_in_vp1 = "/edp@fdec0000/ports/port@0/endpoint@1";
|
edp0_in_vp2 = "/edp@fdec0000/ports/port@0/endpoint@2";
|
edp0_out = "/edp@fdec0000/ports/port@1/endpoint";
|
qos_gpu_m0 = "/qos@fdf35000";
|
qos_gpu_m1 = "/qos@fdf35200";
|
qos_gpu_m2 = "/qos@fdf35400";
|
qos_gpu_m3 = "/qos@fdf35600";
|
qos_rga3_1 = "/qos@fdf36000";
|
qos_sdio = "/qos@fdf39000";
|
qos_sdmmc = "/qos@fdf3d800";
|
qos_usb3_1 = "/qos@fdf3e000";
|
qos_usb3_0 = "/qos@fdf3e200";
|
qos_usb2host_0 = "/qos@fdf3e400";
|
qos_usb2host_1 = "/qos@fdf3e600";
|
qos_fisheye0 = "/qos@fdf40000";
|
qos_fisheye1 = "/qos@fdf40200";
|
qos_isp0_mro = "/qos@fdf40400";
|
qos_isp0_mwo = "/qos@fdf40500";
|
qos_vicap_m0 = "/qos@fdf40600";
|
qos_vicap_m1 = "/qos@fdf40800";
|
qos_isp1_mwo = "/qos@fdf41000";
|
qos_isp1_mro = "/qos@fdf41100";
|
qos_rkvenc0_m0ro = "/qos@fdf60000";
|
qos_rkvenc0_m1ro = "/qos@fdf60200";
|
qos_rkvenc0_m2wo = "/qos@fdf60400";
|
qos_rkvenc1_m0ro = "/qos@fdf61000";
|
qos_rkvenc1_m1ro = "/qos@fdf61200";
|
qos_rkvenc1_m2wo = "/qos@fdf61400";
|
qos_rkvdec0 = "/qos@fdf62000";
|
qos_rkvdec1 = "/qos@fdf63000";
|
qos_av1 = "/qos@fdf64000";
|
qos_iep = "/qos@fdf66000";
|
qos_jpeg_dec = "/qos@fdf66200";
|
qos_jpeg_enc0 = "/qos@fdf66400";
|
qos_jpeg_enc1 = "/qos@fdf66600";
|
qos_jpeg_enc2 = "/qos@fdf66800";
|
qos_jpeg_enc3 = "/qos@fdf66a00";
|
qos_rga2_mro = "/qos@fdf66c00";
|
qos_rga2_mwo = "/qos@fdf66e00";
|
qos_rga3_0 = "/qos@fdf67000";
|
qos_vdpu = "/qos@fdf67200";
|
qos_npu1 = "/qos@fdf70000";
|
qos_npu2 = "/qos@fdf71000";
|
qos_npu0_mwr = "/qos@fdf72000";
|
qos_npu0_mro = "/qos@fdf72200";
|
qos_mcu_npu = "/qos@fdf72400";
|
qos_hdcp0 = "/qos@fdf80000";
|
qos_hdcp1 = "/qos@fdf81000";
|
qos_hdmirx = "/qos@fdf81200";
|
qos_vop_m0 = "/qos@fdf82000";
|
qos_vop_m1 = "/qos@fdf82200";
|
dfi = "/dfi@fe060000";
|
pcie2x1l1 = "/pcie@fe180000";
|
pcie2x1l1_intc = "/pcie@fe180000/legacy-interrupt-controller";
|
pcie2x1l2 = "/pcie@fe190000";
|
pcie2x1l2_intc = "/pcie@fe190000/legacy-interrupt-controller";
|
gmac_uio1 = "/uio@fe1c0000";
|
gmac1 = "/ethernet@fe1c0000";
|
mdio1 = "/ethernet@fe1c0000/mdio";
|
rgmii_phy = "/ethernet@fe1c0000/mdio/phy@1";
|
gmac1_stmmac_axi_setup = "/ethernet@fe1c0000/stmmac-axi-config";
|
gmac1_mtl_rx_setup = "/ethernet@fe1c0000/rx-queues-config";
|
gmac1_mtl_tx_setup = "/ethernet@fe1c0000/tx-queues-config";
|
sata0 = "/sata@fe210000";
|
sata2 = "/sata@fe230000";
|
sfc = "/spi@fe2b0000";
|
sdmmc = "/mmc@fe2c0000";
|
sdio = "/mmc@fe2d0000";
|
sdhci = "/mmc@fe2e0000";
|
crypto = "/crypto@fe370000";
|
rng = "/rng@fe378000";
|
i2s0_8ch = "/i2s@fe470000";
|
i2s1_8ch = "/i2s@fe480000";
|
i2s2_2ch = "/i2s@fe490000";
|
i2s3_2ch = "/i2s@fe4a0000";
|
pdm0 = "/pdm@fe4b0000";
|
pdm1 = "/pdm@fe4c0000";
|
vad = "/vad@fe4d0000";
|
spdif_tx0 = "/spdif-tx@fe4e0000";
|
spdif_tx1 = "/spdif-tx@fe4f0000";
|
acdcdig_dsm = "/codec-digital@fe500000";
|
hwlock = "/hwspinlock@fe5a0000";
|
gic = "/interrupt-controller@fe600000";
|
its0 = "/interrupt-controller@fe600000/msi-controller@fe640000";
|
its1 = "/interrupt-controller@fe600000/msi-controller@fe660000";
|
dmac0 = "/dma-controller@fea10000";
|
dmac1 = "/dma-controller@fea30000";
|
can0 = "/can@fea50000";
|
can1 = "/can@fea60000";
|
can2 = "/can@fea70000";
|
hw_decompress = "/decompress@fea80000";
|
i2c1 = "/i2c@fea90000";
|
vdd_npu_s0 = "/i2c@fea90000/rk8602@42";
|
vdd_npu_mem_s0 = "/i2c@fea90000/rk8602@42";
|
i2c2 = "/i2c@feaa0000";
|
i2c3 = "/i2c@feab0000";
|
es8316 = "/i2c@feab0000/es8316@10";
|
i2c4 = "/i2c@feac0000";
|
ls_stk3332 = "/i2c@feac0000/light@47";
|
ps_stk3332 = "/i2c@feac0000/proximity@47";
|
icm42607_acc = "/i2c@feac0000/icm_acc@68";
|
icm42607_gyro = "/i2c@feac0000/icm_gyro@68";
|
i2c5 = "/i2c@fead0000";
|
gt1x = "/i2c@fead0000/gt1x@14";
|
rktimer = "/timer@feae0000";
|
wdt = "/watchdog@feaf0000";
|
spi0 = "/spi@feb00000";
|
spi1 = "/spi@feb10000";
|
spi2 = "/spi@feb20000";
|
rk806single = "/spi@feb20000/rk806single@0";
|
pinctrl_rk806 = "/spi@feb20000/rk806single@0/pinctrl_rk806";
|
rk806_dvs1_null = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_null";
|
rk806_dvs1_slp = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_slp";
|
rk806_dvs1_pwrdn = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_pwrdn";
|
rk806_dvs1_rst = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_rst";
|
rk806_dvs2_null = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_null";
|
rk806_dvs2_slp = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_slp";
|
rk806_dvs2_pwrdn = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_pwrdn";
|
rk806_dvs2_rst = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_rst";
|
rk806_dvs2_dvs = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_dvs";
|
rk806_dvs2_gpio = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_gpio";
|
rk806_dvs3_null = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_null";
|
rk806_dvs3_slp = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_slp";
|
rk806_dvs3_pwrdn = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_pwrdn";
|
rk806_dvs3_rst = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_rst";
|
rk806_dvs3_dvs = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_dvs";
|
rk806_dvs3_gpio = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_gpio";
|
vdd_gpu_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG1";
|
vdd_gpu_mem_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG1";
|
vdd_cpu_lit_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG2";
|
vdd_cpu_lit_mem_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG2";
|
vdd_log_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG3";
|
vdd_vdenc_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG4";
|
vdd_vdenc_mem_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG4";
|
vdd_ddr_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG5";
|
vdd2_ddr_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG6";
|
vcc_2v0_pldo_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG7";
|
vcc_3v3_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG8";
|
vddq_ddr_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG9";
|
vcc_1v8_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG10";
|
avcc_1v8_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG1";
|
vcc_1v8_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG2";
|
avdd_1v2_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG3";
|
vcc_3v3_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG4";
|
vccio_sd_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG5";
|
pldo6_s3 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG6";
|
vdd_0v75_s3 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG1";
|
vdd_ddr_pll_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG2";
|
avdd_0v75_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG3";
|
vdd_0v85_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG4";
|
vdd_0v75_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG5";
|
spi3 = "/spi@feb30000";
|
uart1 = "/serial@feb40000";
|
uart2 = "/serial@feb50000";
|
uart3 = "/serial@feb60000";
|
uart4 = "/serial@feb70000";
|
uart5 = "/serial@feb80000";
|
uart6 = "/serial@feb90000";
|
uart7 = "/serial@feba0000";
|
uart8 = "/serial@febb0000";
|
uart9 = "/serial@febc0000";
|
pwm4 = "/pwm@febd0000";
|
pwm5 = "/pwm@febd0010";
|
pwm6 = "/pwm@febd0020";
|
pwm7 = "/pwm@febd0030";
|
pwm8 = "/pwm@febe0000";
|
pwm9 = "/pwm@febe0010";
|
pwm10 = "/pwm@febe0020";
|
pwm11 = "/pwm@febe0030";
|
pwm12 = "/pwm@febf0000";
|
pwm13 = "/pwm@febf0010";
|
pwm14 = "/pwm@febf0020";
|
pwm15 = "/pwm@febf0030";
|
tsadc = "/tsadc@fec00000";
|
saradc = "/saradc@fec10000";
|
mailbox0 = "/mailbox@fec60000";
|
mailbox1 = "/mailbox@fec70000";
|
i2c6 = "/i2c@fec80000";
|
hym8563 = "/i2c@fec80000/hym8563@51";
|
i2c7 = "/i2c@fec90000";
|
i2c8 = "/i2c@feca0000";
|
spi4 = "/spi@fecb0000";
|
otp = "/otp@fecc0000";
|
cpu_code = "/otp@fecc0000/cpu-code@2";
|
package_serial_number_high = "/otp@fecc0000/package-serial-number-high@5";
|
package_serial_number_low = "/otp@fecc0000/package-serial-number-low@6";
|
specification_serial_number = "/otp@fecc0000/specification-serial-number@6";
|
otp_id = "/otp@fecc0000/id@7";
|
otp_cpu_version = "/otp@fecc0000/cpu-version@1c";
|
cpub0_leakage = "/otp@fecc0000/cpub0-leakage@17";
|
cpub1_leakage = "/otp@fecc0000/cpub1-leakage@18";
|
cpul_leakage = "/otp@fecc0000/cpul-leakage@19";
|
log_leakage = "/otp@fecc0000/log-leakage@1a";
|
gpu_leakage = "/otp@fecc0000/gpu-leakage@1b";
|
npu_leakage = "/otp@fecc0000/npu-leakage@28";
|
codec_leakage = "/otp@fecc0000/codec-leakage@29";
|
cpul_opp_info = "/otp@fecc0000/cpul-opp-info@3d";
|
cpub01_opp_info = "/otp@fecc0000/cpub01-opp-info@43";
|
cpub23_opp_info = "/otp@fecc0000/cpub23-opp-info@49";
|
gpu_opp_info = "/otp@fecc0000/gpu-opp-info@4f";
|
npu_opp_info = "/otp@fecc0000/npu-opp-info@55";
|
dmc_opp_info = "/otp@fecc0000/dmc-opp-info@5b";
|
vop_opp_info = "/otp@fecc0000/vop-opp-info@61";
|
venc_opp_info = "/otp@fecc0000/venc-opp-info@67";
|
mailbox2 = "/mailbox@fece0000";
|
dmac2 = "/dma-controller@fed10000";
|
hdptxphy0 = "/phy@fed60000";
|
hdptxphy_hdmi0 = "/hdmiphy@fed60000";
|
hdptxphy_hdmi_clk0 = "/hdmiphy@fed60000/clk-port";
|
usbdp_phy0 = "/phy@fed80000";
|
usbdp_phy0_dp = "/phy@fed80000/dp-port";
|
usbdp_phy0_u3 = "/phy@fed80000/u3-port";
|
mipidcphy0 = "/phy@feda0000";
|
mipidcphy1 = "/phy@fedb0000";
|
csi2_dphy0_hw = "/csi2-dphy0-hw@fedc0000";
|
csi2_dphy1_hw = "/csi2-dphy1-hw@fedc8000";
|
combphy0_ps = "/phy@fee00000";
|
combphy2_psu = "/phy@fee20000";
|
syssram = "/sram@ff001000";
|
rkvdec0_sram = "/sram@ff001000/rkvdec-sram@0";
|
rkvdec1_sram = "/sram@ff001000/rkvdec-sram@78000";
|
pinctrl = "/pinctrl";
|
gpio0 = "/pinctrl/gpio@fd8a0000";
|
gpio1 = "/pinctrl/gpio@fec20000";
|
gpio2 = "/pinctrl/gpio@fec30000";
|
gpio3 = "/pinctrl/gpio@fec40000";
|
gpio4 = "/pinctrl/gpio@fec50000";
|
pcfg_pull_up = "/pinctrl/pcfg-pull-up";
|
pcfg_pull_down = "/pinctrl/pcfg-pull-down";
|
pcfg_pull_none = "/pinctrl/pcfg-pull-none";
|
pcfg_pull_none_drv_level_0 = "/pinctrl/pcfg-pull-none-drv-level-0";
|
pcfg_pull_none_drv_level_1 = "/pinctrl/pcfg-pull-none-drv-level-1";
|
pcfg_pull_none_drv_level_2 = "/pinctrl/pcfg-pull-none-drv-level-2";
|
pcfg_pull_none_drv_level_3 = "/pinctrl/pcfg-pull-none-drv-level-3";
|
pcfg_pull_none_drv_level_4 = "/pinctrl/pcfg-pull-none-drv-level-4";
|
pcfg_pull_none_drv_level_5 = "/pinctrl/pcfg-pull-none-drv-level-5";
|
pcfg_pull_none_drv_level_6 = "/pinctrl/pcfg-pull-none-drv-level-6";
|
pcfg_pull_up_drv_level_0 = "/pinctrl/pcfg-pull-up-drv-level-0";
|
pcfg_pull_up_drv_level_1 = "/pinctrl/pcfg-pull-up-drv-level-1";
|
pcfg_pull_up_drv_level_2 = "/pinctrl/pcfg-pull-up-drv-level-2";
|
pcfg_pull_up_drv_level_3 = "/pinctrl/pcfg-pull-up-drv-level-3";
|
pcfg_pull_up_drv_level_4 = "/pinctrl/pcfg-pull-up-drv-level-4";
|
pcfg_pull_up_drv_level_5 = "/pinctrl/pcfg-pull-up-drv-level-5";
|
pcfg_pull_up_drv_level_6 = "/pinctrl/pcfg-pull-up-drv-level-6";
|
pcfg_pull_down_drv_level_0 = "/pinctrl/pcfg-pull-down-drv-level-0";
|
pcfg_pull_down_drv_level_1 = "/pinctrl/pcfg-pull-down-drv-level-1";
|
pcfg_pull_down_drv_level_2 = "/pinctrl/pcfg-pull-down-drv-level-2";
|
pcfg_pull_down_drv_level_3 = "/pinctrl/pcfg-pull-down-drv-level-3";
|
pcfg_pull_down_drv_level_4 = "/pinctrl/pcfg-pull-down-drv-level-4";
|
pcfg_pull_down_drv_level_5 = "/pinctrl/pcfg-pull-down-drv-level-5";
|
pcfg_pull_down_drv_level_6 = "/pinctrl/pcfg-pull-down-drv-level-6";
|
pcfg_pull_up_smt = "/pinctrl/pcfg-pull-up-smt";
|
pcfg_pull_down_smt = "/pinctrl/pcfg-pull-down-smt";
|
pcfg_pull_none_smt = "/pinctrl/pcfg-pull-none-smt";
|
pcfg_pull_none_drv_level_0_smt = "/pinctrl/pcfg-pull-none-drv-level-0-smt";
|
pcfg_pull_none_drv_level_1_smt = "/pinctrl/pcfg-pull-none-drv-level-1-smt";
|
pcfg_pull_none_drv_level_2_smt = "/pinctrl/pcfg-pull-none-drv-level-2-smt";
|
pcfg_pull_none_drv_level_3_smt = "/pinctrl/pcfg-pull-none-drv-level-3-smt";
|
pcfg_pull_none_drv_level_4_smt = "/pinctrl/pcfg-pull-none-drv-level-4-smt";
|
pcfg_pull_none_drv_level_5_smt = "/pinctrl/pcfg-pull-none-drv-level-5-smt";
|
pcfg_pull_none_drv_level_6_smt = "/pinctrl/pcfg-pull-none-drv-level-6-smt";
|
pcfg_output_high = "/pinctrl/pcfg-output-high";
|
pcfg_output_high_pull_up = "/pinctrl/pcfg-output-high-pull-up";
|
pcfg_output_high_pull_down = "/pinctrl/pcfg-output-high-pull-down";
|
pcfg_output_high_pull_none = "/pinctrl/pcfg-output-high-pull-none";
|
pcfg_output_low = "/pinctrl/pcfg-output-low";
|
pcfg_output_low_pull_up = "/pinctrl/pcfg-output-low-pull-up";
|
pcfg_output_low_pull_down = "/pinctrl/pcfg-output-low-pull-down";
|
pcfg_output_low_pull_none = "/pinctrl/pcfg-output-low-pull-none";
|
auddsm_pins = "/pinctrl/auddsm/auddsm-pins";
|
bt1120_pins = "/pinctrl/bt1120/bt1120-pins";
|
can0m0_pins = "/pinctrl/can0/can0m0-pins";
|
can0m1_pins = "/pinctrl/can0/can0m1-pins";
|
can1m0_pins = "/pinctrl/can1/can1m0-pins";
|
can1m1_pins = "/pinctrl/can1/can1m1-pins";
|
can2m0_pins = "/pinctrl/can2/can2m0-pins";
|
can2m1_pins = "/pinctrl/can2/can2m1-pins";
|
cif_clk = "/pinctrl/cif/cif-clk";
|
cif_dvp_clk = "/pinctrl/cif/cif-dvp-clk";
|
cif_dvp_bus16 = "/pinctrl/cif/cif-dvp-bus16";
|
cif_dvp_bus8 = "/pinctrl/cif/cif-dvp-bus8";
|
clk32k_in = "/pinctrl/clk32k/clk32k-in";
|
clk32k_out0 = "/pinctrl/clk32k/clk32k-out0";
|
clk32k_out1 = "/pinctrl/clk32k/clk32k-out1";
|
cpu_pins = "/pinctrl/cpu/cpu-pins";
|
ddrphych0_pins = "/pinctrl/ddrphych0/ddrphych0-pins";
|
ddrphych1_pins = "/pinctrl/ddrphych1/ddrphych1-pins";
|
ddrphych2_pins = "/pinctrl/ddrphych2/ddrphych2-pins";
|
ddrphych3_pins = "/pinctrl/ddrphych3/ddrphych3-pins";
|
dp0m0_pins = "/pinctrl/dp0/dp0m0-pins";
|
dp0m1_pins = "/pinctrl/dp0/dp0m1-pins";
|
dp0m2_pins = "/pinctrl/dp0/dp0m2-pins";
|
dp1m0_pins = "/pinctrl/dp1/dp1m0-pins";
|
dp1m1_pins = "/pinctrl/dp1/dp1m1-pins";
|
dp1m2_pins = "/pinctrl/dp1/dp1m2-pins";
|
emmc_rstnout = "/pinctrl/emmc/emmc-rstnout";
|
emmc_bus8 = "/pinctrl/emmc/emmc-bus8";
|
emmc_clk = "/pinctrl/emmc/emmc-clk";
|
emmc_cmd = "/pinctrl/emmc/emmc-cmd";
|
emmc_data_strobe = "/pinctrl/emmc/emmc-data-strobe";
|
eth1_pins = "/pinctrl/eth1/eth1-pins";
|
fspim0_pins = "/pinctrl/fspi/fspim0-pins";
|
fspim0_cs1 = "/pinctrl/fspi/fspim0-cs1";
|
fspim2_pins = "/pinctrl/fspi/fspim2-pins";
|
fspim2_cs1 = "/pinctrl/fspi/fspim2-cs1";
|
fspim1_pins = "/pinctrl/fspi/fspim1-pins";
|
fspim1_cs1 = "/pinctrl/fspi/fspim1-cs1";
|
gmac1_miim = "/pinctrl/gmac1/gmac1-miim";
|
gmac1_clkinout = "/pinctrl/gmac1/gmac1-clkinout";
|
gmac1_rx_bus2 = "/pinctrl/gmac1/gmac1-rx-bus2";
|
gmac1_tx_bus2 = "/pinctrl/gmac1/gmac1-tx-bus2";
|
gmac1_rgmii_clk = "/pinctrl/gmac1/gmac1-rgmii-clk";
|
gmac1_rgmii_bus = "/pinctrl/gmac1/gmac1-rgmii-bus";
|
gmac1_ppsclk = "/pinctrl/gmac1/gmac1-ppsclk";
|
gmac1_ppstrig = "/pinctrl/gmac1/gmac1-ppstrig";
|
gmac1_ptp_ref_clk = "/pinctrl/gmac1/gmac1-ptp-ref-clk";
|
gmac1_txer = "/pinctrl/gmac1/gmac1-txer";
|
gpu_pins = "/pinctrl/gpu/gpu-pins";
|
hdmim0_rx_cec = "/pinctrl/hdmi/hdmim0-rx-cec";
|
hdmim0_rx_hpdin = "/pinctrl/hdmi/hdmim0-rx-hpdin";
|
hdmim0_rx_scl = "/pinctrl/hdmi/hdmim0-rx-scl";
|
hdmim0_rx_sda = "/pinctrl/hdmi/hdmim0-rx-sda";
|
hdmim0_tx0_cec = "/pinctrl/hdmi/hdmim0-tx0-cec";
|
hdmim0_tx0_hpd = "/pinctrl/hdmi/hdmim0-tx0-hpd";
|
hdmim0_tx0_scl = "/pinctrl/hdmi/hdmim0-tx0-scl";
|
hdmim0_tx0_sda = "/pinctrl/hdmi/hdmim0-tx0-sda";
|
hdmim0_tx1_hpd = "/pinctrl/hdmi/hdmim0-tx1-hpd";
|
hdmim1_rx = "/pinctrl/hdmi/hdmim1-rx";
|
hdmim1_rx_cec = "/pinctrl/hdmi/hdmim1-rx-cec";
|
hdmim1_rx_hpdin = "/pinctrl/hdmi/hdmim1-rx-hpdin";
|
hdmim1_rx_scl = "/pinctrl/hdmi/hdmim1-rx-scl";
|
hdmim1_rx_sda = "/pinctrl/hdmi/hdmim1-rx-sda";
|
hdmim1_tx0_cec = "/pinctrl/hdmi/hdmim1-tx0-cec";
|
hdmim1_tx0_hpd = "/pinctrl/hdmi/hdmim1-tx0-hpd";
|
hdmim1_tx0_scl = "/pinctrl/hdmi/hdmim1-tx0-scl";
|
hdmim1_tx0_sda = "/pinctrl/hdmi/hdmim1-tx0-sda";
|
hdmim1_tx1_cec = "/pinctrl/hdmi/hdmim1-tx1-cec";
|
hdmim1_tx1_hpd = "/pinctrl/hdmi/hdmim1-tx1-hpd";
|
hdmim1_tx1_scl = "/pinctrl/hdmi/hdmim1-tx1-scl";
|
hdmim1_tx1_sda = "/pinctrl/hdmi/hdmim1-tx1-sda";
|
hdmim2_rx_cec = "/pinctrl/hdmi/hdmim2-rx-cec";
|
hdmim2_rx_hpdin = "/pinctrl/hdmi/hdmim2-rx-hpdin";
|
hdmim2_rx_scl = "/pinctrl/hdmi/hdmim2-rx-scl";
|
hdmim2_rx_sda = "/pinctrl/hdmi/hdmim2-rx-sda";
|
hdmim2_tx0_scl = "/pinctrl/hdmi/hdmim2-tx0-scl";
|
hdmim2_tx0_sda = "/pinctrl/hdmi/hdmim2-tx0-sda";
|
hdmim2_tx1_cec = "/pinctrl/hdmi/hdmim2-tx1-cec";
|
hdmim2_tx1_scl = "/pinctrl/hdmi/hdmim2-tx1-scl";
|
hdmim2_tx1_sda = "/pinctrl/hdmi/hdmim2-tx1-sda";
|
hdmi_debug0 = "/pinctrl/hdmi/hdmi-debug0";
|
hdmi_debug1 = "/pinctrl/hdmi/hdmi-debug1";
|
hdmi_debug2 = "/pinctrl/hdmi/hdmi-debug2";
|
hdmi_debug3 = "/pinctrl/hdmi/hdmi-debug3";
|
hdmi_debug4 = "/pinctrl/hdmi/hdmi-debug4";
|
hdmi_debug5 = "/pinctrl/hdmi/hdmi-debug5";
|
hdmi_debug6 = "/pinctrl/hdmi/hdmi-debug6";
|
hdmim0_tx1_cec = "/pinctrl/hdmi/hdmim0-tx1-cec";
|
hdmim0_tx1_scl = "/pinctrl/hdmi/hdmim0-tx1-scl";
|
hdmim0_tx1_sda = "/pinctrl/hdmi/hdmim0-tx1-sda";
|
hdmirx_det = "/pinctrl/hdmi/hdmirx-det";
|
i2c0m0_xfer = "/pinctrl/i2c0/i2c0m0-xfer";
|
i2c0m2_xfer = "/pinctrl/i2c0/i2c0m2-xfer";
|
i2c0m1_xfer = "/pinctrl/i2c0/i2c0m1-xfer";
|
i2c1m0_xfer = "/pinctrl/i2c1/i2c1m0-xfer";
|
i2c1m1_xfer = "/pinctrl/i2c1/i2c1m1-xfer";
|
i2c1m2_xfer = "/pinctrl/i2c1/i2c1m2-xfer";
|
i2c1m3_xfer = "/pinctrl/i2c1/i2c1m3-xfer";
|
i2c1m4_xfer = "/pinctrl/i2c1/i2c1m4-xfer";
|
i2c2m0_xfer = "/pinctrl/i2c2/i2c2m0-xfer";
|
i2c2m2_xfer = "/pinctrl/i2c2/i2c2m2-xfer";
|
i2c2m3_xfer = "/pinctrl/i2c2/i2c2m3-xfer";
|
i2c2m4_xfer = "/pinctrl/i2c2/i2c2m4-xfer";
|
i2c2m1_xfer = "/pinctrl/i2c2/i2c2m1-xfer";
|
i2c3m0_xfer = "/pinctrl/i2c3/i2c3m0-xfer";
|
i2c3m1_xfer = "/pinctrl/i2c3/i2c3m1-xfer";
|
i2c3m2_xfer = "/pinctrl/i2c3/i2c3m2-xfer";
|
i2c3m4_xfer = "/pinctrl/i2c3/i2c3m4-xfer";
|
i2c3m3_xfer = "/pinctrl/i2c3/i2c3m3-xfer";
|
i2c4m0_xfer = "/pinctrl/i2c4/i2c4m0-xfer";
|
i2c4m2_xfer = "/pinctrl/i2c4/i2c4m2-xfer";
|
i2c4m3_xfer = "/pinctrl/i2c4/i2c4m3-xfer";
|
i2c4m4_xfer = "/pinctrl/i2c4/i2c4m4-xfer";
|
i2c4m1_xfer = "/pinctrl/i2c4/i2c4m1-xfer";
|
i2c5m0_xfer = "/pinctrl/i2c5/i2c5m0-xfer";
|
i2c5m1_xfer = "/pinctrl/i2c5/i2c5m1-xfer";
|
i2c5m2_xfer = "/pinctrl/i2c5/i2c5m2-xfer";
|
i2c5m3_xfer = "/pinctrl/i2c5/i2c5m3-xfer";
|
i2c5m4_xfer = "/pinctrl/i2c5/i2c5m4-xfer";
|
i2c6m0_xfer = "/pinctrl/i2c6/i2c6m0-xfer";
|
i2c6m1_xfer = "/pinctrl/i2c6/i2c6m1-xfer";
|
i2c6m3_xfer = "/pinctrl/i2c6/i2c6m3-xfer";
|
i2c6m4_xfer = "/pinctrl/i2c6/i2c6m4-xfer";
|
i2c6m2_xfer = "/pinctrl/i2c6/i2c6m2-xfer";
|
i2c7m0_xfer = "/pinctrl/i2c7/i2c7m0-xfer";
|
i2c7m2_xfer = "/pinctrl/i2c7/i2c7m2-xfer";
|
i2c7m3_xfer = "/pinctrl/i2c7/i2c7m3-xfer";
|
i2c7m1_xfer = "/pinctrl/i2c7/i2c7m1-xfer";
|
i2c8m0_xfer = "/pinctrl/i2c8/i2c8m0-xfer";
|
i2c8m2_xfer = "/pinctrl/i2c8/i2c8m2-xfer";
|
i2c8m3_xfer = "/pinctrl/i2c8/i2c8m3-xfer";
|
i2c8m4_xfer = "/pinctrl/i2c8/i2c8m4-xfer";
|
i2c8m1_xfer = "/pinctrl/i2c8/i2c8m1-xfer";
|
i2s0_idle = "/pinctrl/i2s0/i2s0-idle";
|
i2s0_lrck = "/pinctrl/i2s0/i2s0-lrck";
|
i2s0_mclk = "/pinctrl/i2s0/i2s0-mclk";
|
i2s0_sclk = "/pinctrl/i2s0/i2s0-sclk";
|
i2s0_sdi0 = "/pinctrl/i2s0/i2s0-sdi0";
|
i2s0_sdi1 = "/pinctrl/i2s0/i2s0-sdi1";
|
i2s0_sdi2 = "/pinctrl/i2s0/i2s0-sdi2";
|
i2s0_sdi3 = "/pinctrl/i2s0/i2s0-sdi3";
|
i2s0_sdo0 = "/pinctrl/i2s0/i2s0-sdo0";
|
i2s0_sdo1 = "/pinctrl/i2s0/i2s0-sdo1";
|
i2s0_sdo2 = "/pinctrl/i2s0/i2s0-sdo2";
|
i2s0_sdo3 = "/pinctrl/i2s0/i2s0-sdo3";
|
i2s1m0_lrck = "/pinctrl/i2s1/i2s1m0-lrck";
|
i2s1m0_mclk = "/pinctrl/i2s1/i2s1m0-mclk";
|
i2s1m0_sclk = "/pinctrl/i2s1/i2s1m0-sclk";
|
i2s1m0_sdi0 = "/pinctrl/i2s1/i2s1m0-sdi0";
|
i2s1m0_sdi1 = "/pinctrl/i2s1/i2s1m0-sdi1";
|
i2s1m0_sdi2 = "/pinctrl/i2s1/i2s1m0-sdi2";
|
i2s1m0_sdi3 = "/pinctrl/i2s1/i2s1m0-sdi3";
|
i2s1m0_sdo0 = "/pinctrl/i2s1/i2s1m0-sdo0";
|
i2s1m0_sdo1 = "/pinctrl/i2s1/i2s1m0-sdo1";
|
i2s1m0_sdo2 = "/pinctrl/i2s1/i2s1m0-sdo2";
|
i2s1m0_sdo3 = "/pinctrl/i2s1/i2s1m0-sdo3";
|
i2s1m1_lrck = "/pinctrl/i2s1/i2s1m1-lrck";
|
i2s1m1_mclk = "/pinctrl/i2s1/i2s1m1-mclk";
|
i2s1m1_sclk = "/pinctrl/i2s1/i2s1m1-sclk";
|
i2s1m1_sdi0 = "/pinctrl/i2s1/i2s1m1-sdi0";
|
i2s1m1_sdi1 = "/pinctrl/i2s1/i2s1m1-sdi1";
|
i2s1m1_sdi2 = "/pinctrl/i2s1/i2s1m1-sdi2";
|
i2s1m1_sdi3 = "/pinctrl/i2s1/i2s1m1-sdi3";
|
i2s1m1_sdo0 = "/pinctrl/i2s1/i2s1m1-sdo0";
|
i2s1m1_sdo1 = "/pinctrl/i2s1/i2s1m1-sdo1";
|
i2s1m1_sdo2 = "/pinctrl/i2s1/i2s1m1-sdo2";
|
i2s1m1_sdo3 = "/pinctrl/i2s1/i2s1m1-sdo3";
|
i2s2m1_idle = "/pinctrl/i2s2/i2s2m1-idle";
|
i2s2m1_lrck = "/pinctrl/i2s2/i2s2m1-lrck";
|
i2s2m1_mclk = "/pinctrl/i2s2/i2s2m1-mclk";
|
i2s2m1_sclk = "/pinctrl/i2s2/i2s2m1-sclk";
|
i2s2m1_sdi = "/pinctrl/i2s2/i2s2m1-sdi";
|
i2s2m1_sdo = "/pinctrl/i2s2/i2s2m1-sdo";
|
i2s2m0_idle = "/pinctrl/i2s2/i2s2m0-idle";
|
i2s2m0_lrck = "/pinctrl/i2s2/i2s2m0-lrck";
|
i2s2m0_mclk = "/pinctrl/i2s2/i2s2m0-mclk";
|
i2s2m0_sclk = "/pinctrl/i2s2/i2s2m0-sclk";
|
i2s2m0_sdi = "/pinctrl/i2s2/i2s2m0-sdi";
|
i2s2m0_sdo = "/pinctrl/i2s2/i2s2m0-sdo";
|
i2s3_idle = "/pinctrl/i2s3/i2s3-idle";
|
i2s3_lrck = "/pinctrl/i2s3/i2s3-lrck";
|
i2s3_mclk = "/pinctrl/i2s3/i2s3-mclk";
|
i2s3_sclk = "/pinctrl/i2s3/i2s3-sclk";
|
i2s3_sdi = "/pinctrl/i2s3/i2s3-sdi";
|
i2s3_sdo = "/pinctrl/i2s3/i2s3-sdo";
|
jtagm0_pins = "/pinctrl/jtag/jtagm0-pins";
|
jtagm1_pins = "/pinctrl/jtag/jtagm1-pins";
|
jtagm2_pins = "/pinctrl/jtag/jtagm2-pins";
|
litcpu_pins = "/pinctrl/litcpu/litcpu-pins";
|
mcum0_pins = "/pinctrl/mcu/mcum0-pins";
|
mcum1_pins = "/pinctrl/mcu/mcum1-pins";
|
mipim0_camera0_clk = "/pinctrl/mipi/mipim0-camera0-clk";
|
mipim0_camera1_clk = "/pinctrl/mipi/mipim0-camera1-clk";
|
mipim0_camera2_clk = "/pinctrl/mipi/mipim0-camera2-clk";
|
mipim0_camera3_clk = "/pinctrl/mipi/mipim0-camera3-clk";
|
mipim0_camera4_clk = "/pinctrl/mipi/mipim0-camera4-clk";
|
mipim1_camera0_clk = "/pinctrl/mipi/mipim1-camera0-clk";
|
mipim1_camera1_clk = "/pinctrl/mipi/mipim1-camera1-clk";
|
mipim1_camera2_clk = "/pinctrl/mipi/mipim1-camera2-clk";
|
mipim1_camera3_clk = "/pinctrl/mipi/mipim1-camera3-clk";
|
mipim1_camera4_clk = "/pinctrl/mipi/mipim1-camera4-clk";
|
mipi_te0 = "/pinctrl/mipi/mipi-te0";
|
mipi_te1 = "/pinctrl/mipi/mipi-te1";
|
npu_pins = "/pinctrl/npu/npu-pins";
|
pcie20x1m0_pins = "/pinctrl/pcie20x1/pcie20x1m0-pins";
|
pcie20x1m1_pins = "/pinctrl/pcie20x1/pcie20x1m1-pins";
|
pcie20x1_2_button_rstn = "/pinctrl/pcie20x1/pcie20x1-2-button-rstn";
|
pcie30phy_pins = "/pinctrl/pcie30phy/pcie30phy-pins";
|
pcie30x1m0_pins = "/pinctrl/pcie30x1/pcie30x1m0-pins";
|
pcie30x1m1_pins = "/pinctrl/pcie30x1/pcie30x1m1-pins";
|
pcie30x1m2_pins = "/pinctrl/pcie30x1/pcie30x1m2-pins";
|
pcie30x1_0_button_rstn = "/pinctrl/pcie30x1/pcie30x1-0-button-rstn";
|
pcie30x1_1_button_rstn = "/pinctrl/pcie30x1/pcie30x1-1-button-rstn";
|
pcie30x2m0_pins = "/pinctrl/pcie30x2/pcie30x2m0-pins";
|
pcie30x2m1_pins = "/pinctrl/pcie30x2/pcie30x2m1-pins";
|
pcie30x2m2_pins = "/pinctrl/pcie30x2/pcie30x2m2-pins";
|
pcie30x2m3_pins = "/pinctrl/pcie30x2/pcie30x2m3-pins";
|
pcie30x2_button_rstn = "/pinctrl/pcie30x2/pcie30x2-button-rstn";
|
pcie30x4m0_pins = "/pinctrl/pcie30x4/pcie30x4m0-pins";
|
pcie30x4m1_pins = "/pinctrl/pcie30x4/pcie30x4m1-pins";
|
pcie30x4m2_pins = "/pinctrl/pcie30x4/pcie30x4m2-pins";
|
pcie30x4m3_pins = "/pinctrl/pcie30x4/pcie30x4m3-pins";
|
pcie30x4_button_rstn = "/pinctrl/pcie30x4/pcie30x4-button-rstn";
|
pcie30x4_clkreqn_m1 = "/pinctrl/pcie30x4/pcie30x4-clkreqn-m1";
|
pdm0m0_clk = "/pinctrl/pdm0/pdm0m0-clk";
|
pdm0m0_clk1 = "/pinctrl/pdm0/pdm0m0-clk1";
|
pdm0m0_idle = "/pinctrl/pdm0/pdm0m0-idle";
|
pdm0m0_sdi0 = "/pinctrl/pdm0/pdm0m0-sdi0";
|
pdm0m0_sdi1 = "/pinctrl/pdm0/pdm0m0-sdi1";
|
pdm0m0_sdi2 = "/pinctrl/pdm0/pdm0m0-sdi2";
|
pdm0m0_sdi3 = "/pinctrl/pdm0/pdm0m0-sdi3";
|
pdm0m1_clk = "/pinctrl/pdm0/pdm0m1-clk";
|
pdm0m1_clk1 = "/pinctrl/pdm0/pdm0m1-clk1";
|
pdm0m1_idle = "/pinctrl/pdm0/pdm0m1-idle";
|
pdm0m1_sdi0 = "/pinctrl/pdm0/pdm0m1-sdi0";
|
pdm0m1_sdi1 = "/pinctrl/pdm0/pdm0m1-sdi1";
|
pdm0m1_sdi2 = "/pinctrl/pdm0/pdm0m1-sdi2";
|
pdm0m1_sdi3 = "/pinctrl/pdm0/pdm0m1-sdi3";
|
pdm1m0_clk = "/pinctrl/pdm1/pdm1m0-clk";
|
pdm1m0_clk1 = "/pinctrl/pdm1/pdm1m0-clk1";
|
pdm1m0_idle = "/pinctrl/pdm1/pdm1m0-idle";
|
pdm1m0_sdi0 = "/pinctrl/pdm1/pdm1m0-sdi0";
|
pdm1m0_sdi1 = "/pinctrl/pdm1/pdm1m0-sdi1";
|
pdm1m0_sdi2 = "/pinctrl/pdm1/pdm1m0-sdi2";
|
pdm1m0_sdi3 = "/pinctrl/pdm1/pdm1m0-sdi3";
|
pdm1m1_clk = "/pinctrl/pdm1/pdm1m1-clk";
|
pdm1m1_clk1 = "/pinctrl/pdm1/pdm1m1-clk1";
|
pdm1m1_idle = "/pinctrl/pdm1/pdm1m1-idle";
|
pdm1m1_sdi0 = "/pinctrl/pdm1/pdm1m1-sdi0";
|
pdm1m1_sdi1 = "/pinctrl/pdm1/pdm1m1-sdi1";
|
pdm1m1_sdi2 = "/pinctrl/pdm1/pdm1m1-sdi2";
|
pdm1m1_sdi3 = "/pinctrl/pdm1/pdm1m1-sdi3";
|
pmic_pins = "/pinctrl/pmic/pmic-pins";
|
pmu_pins = "/pinctrl/pmu/pmu-pins";
|
pwm0m0_pins = "/pinctrl/pwm0/pwm0m0-pins";
|
pwm0m1_pins = "/pinctrl/pwm0/pwm0m1-pins";
|
pwm0m2_pins = "/pinctrl/pwm0/pwm0m2-pins";
|
pwm1m0_pins = "/pinctrl/pwm1/pwm1m0-pins";
|
pwm1m1_pins = "/pinctrl/pwm1/pwm1m1-pins";
|
pwm1m2_pins = "/pinctrl/pwm1/pwm1m2-pins";
|
pwm2m0_pins = "/pinctrl/pwm2/pwm2m0-pins";
|
pwm2m1_pins = "/pinctrl/pwm2/pwm2m1-pins";
|
pwm2m2_pins = "/pinctrl/pwm2/pwm2m2-pins";
|
pwm3m0_pins = "/pinctrl/pwm3/pwm3m0-pins";
|
pwm3m1_pins = "/pinctrl/pwm3/pwm3m1-pins";
|
pwm3m2_pins = "/pinctrl/pwm3/pwm3m2-pins";
|
pwm3m3_pins = "/pinctrl/pwm3/pwm3m3-pins";
|
pwm4m0_pins = "/pinctrl/pwm4/pwm4m0-pins";
|
pwm4m1_pins = "/pinctrl/pwm4/pwm4m1-pins";
|
pwm5m0_pins = "/pinctrl/pwm5/pwm5m0-pins";
|
pwm5m1_pins = "/pinctrl/pwm5/pwm5m1-pins";
|
pwm5m2_pins = "/pinctrl/pwm5/pwm5m2-pins";
|
pwm6m0_pins = "/pinctrl/pwm6/pwm6m0-pins";
|
pwm6m1_pins = "/pinctrl/pwm6/pwm6m1-pins";
|
pwm6m2_pins = "/pinctrl/pwm6/pwm6m2-pins";
|
pwm7m0_pins = "/pinctrl/pwm7/pwm7m0-pins";
|
pwm7m1_pins = "/pinctrl/pwm7/pwm7m1-pins";
|
pwm7m2_pins = "/pinctrl/pwm7/pwm7m2-pins";
|
pwm7m3_pins = "/pinctrl/pwm7/pwm7m3-pins";
|
pwm8m0_pins = "/pinctrl/pwm8/pwm8m0-pins";
|
pwm8m1_pins = "/pinctrl/pwm8/pwm8m1-pins";
|
pwm8m2_pins = "/pinctrl/pwm8/pwm8m2-pins";
|
pwm9m0_pins = "/pinctrl/pwm9/pwm9m0-pins";
|
pwm9m1_pins = "/pinctrl/pwm9/pwm9m1-pins";
|
pwm9m2_pins = "/pinctrl/pwm9/pwm9m2-pins";
|
pwm10m0_pins = "/pinctrl/pwm10/pwm10m0-pins";
|
pwm10m1_pins = "/pinctrl/pwm10/pwm10m1-pins";
|
pwm10m2_pins = "/pinctrl/pwm10/pwm10m2-pins";
|
pwm11m0_pins = "/pinctrl/pwm11/pwm11m0-pins";
|
pwm11m1_pins = "/pinctrl/pwm11/pwm11m1-pins";
|
pwm11m2_pins = "/pinctrl/pwm11/pwm11m2-pins";
|
pwm11m3_pins = "/pinctrl/pwm11/pwm11m3-pins";
|
pwm12m0_pins = "/pinctrl/pwm12/pwm12m0-pins";
|
pwm12m1_pins = "/pinctrl/pwm12/pwm12m1-pins";
|
pwm13m0_pins = "/pinctrl/pwm13/pwm13m0-pins";
|
pwm13m1_pins = "/pinctrl/pwm13/pwm13m1-pins";
|
pwm13m2_pins = "/pinctrl/pwm13/pwm13m2-pins";
|
pwm14m0_pins = "/pinctrl/pwm14/pwm14m0-pins";
|
pwm14m1_pins = "/pinctrl/pwm14/pwm14m1-pins";
|
pwm14m2_pins = "/pinctrl/pwm14/pwm14m2-pins";
|
pwm15m0_pins = "/pinctrl/pwm15/pwm15m0-pins";
|
pwm15m1_pins = "/pinctrl/pwm15/pwm15m1-pins";
|
pwm15m2_pins = "/pinctrl/pwm15/pwm15m2-pins";
|
pwm15m3_pins = "/pinctrl/pwm15/pwm15m3-pins";
|
refclk_pins = "/pinctrl/refclk/refclk-pins";
|
sata_pins = "/pinctrl/sata/sata-pins";
|
sata0m0_pins = "/pinctrl/sata0/sata0m0-pins";
|
sata0m1_pins = "/pinctrl/sata0/sata0m1-pins";
|
sata1m0_pins = "/pinctrl/sata1/sata1m0-pins";
|
sata1m1_pins = "/pinctrl/sata1/sata1m1-pins";
|
sata2m0_pins = "/pinctrl/sata2/sata2m0-pins";
|
sata2m1_pins = "/pinctrl/sata2/sata2m1-pins";
|
sdiom1_pins = "/pinctrl/sdio/sdiom1-pins";
|
sdiom0_pins = "/pinctrl/sdio/sdiom0-pins";
|
sdmmc_bus4 = "/pinctrl/sdmmc/sdmmc-bus4";
|
sdmmc_clk = "/pinctrl/sdmmc/sdmmc-clk";
|
sdmmc_cmd = "/pinctrl/sdmmc/sdmmc-cmd";
|
sdmmc_det = "/pinctrl/sdmmc/sdmmc-det";
|
sdmmc_pwren = "/pinctrl/sdmmc/sdmmc-pwren";
|
spdif0m0_tx = "/pinctrl/spdif0/spdif0m0-tx";
|
spdif0m1_tx = "/pinctrl/spdif0/spdif0m1-tx";
|
spdif1m0_tx = "/pinctrl/spdif1/spdif1m0-tx";
|
spdif1m1_tx = "/pinctrl/spdif1/spdif1m1-tx";
|
spdif1m2_tx = "/pinctrl/spdif1/spdif1m2-tx";
|
spi0m0_pins = "/pinctrl/spi0/spi0m0-pins";
|
spi0m0_cs0 = "/pinctrl/spi0/spi0m0-cs0";
|
spi0m0_cs1 = "/pinctrl/spi0/spi0m0-cs1";
|
spi0m1_pins = "/pinctrl/spi0/spi0m1-pins";
|
spi0m1_cs0 = "/pinctrl/spi0/spi0m1-cs0";
|
spi0m1_cs1 = "/pinctrl/spi0/spi0m1-cs1";
|
spi0m2_pins = "/pinctrl/spi0/spi0m2-pins";
|
spi0m2_cs0 = "/pinctrl/spi0/spi0m2-cs0";
|
spi0m2_cs1 = "/pinctrl/spi0/spi0m2-cs1";
|
spi0m3_pins = "/pinctrl/spi0/spi0m3-pins";
|
spi0m3_cs0 = "/pinctrl/spi0/spi0m3-cs0";
|
spi0m3_cs1 = "/pinctrl/spi0/spi0m3-cs1";
|
spi1m1_pins = "/pinctrl/spi1/spi1m1-pins";
|
spi1m1_cs0 = "/pinctrl/spi1/spi1m1-cs0";
|
spi1m1_cs1 = "/pinctrl/spi1/spi1m1-cs1";
|
spi1m2_pins = "/pinctrl/spi1/spi1m2-pins";
|
spi1m2_cs0 = "/pinctrl/spi1/spi1m2-cs0";
|
spi1m2_cs1 = "/pinctrl/spi1/spi1m2-cs1";
|
spi1m0_pins = "/pinctrl/spi1/spi1m0-pins";
|
spi1m0_cs0 = "/pinctrl/spi1/spi1m0-cs0";
|
spi1m0_cs1 = "/pinctrl/spi1/spi1m0-cs1";
|
spi2m0_pins = "/pinctrl/spi2/spi2m0-pins";
|
spi2m0_cs0 = "/pinctrl/spi2/spi2m0-cs0";
|
spi2m0_cs1 = "/pinctrl/spi2/spi2m0-cs1";
|
spi2m1_pins = "/pinctrl/spi2/spi2m1-pins";
|
spi2m1_cs0 = "/pinctrl/spi2/spi2m1-cs0";
|
spi2m1_cs1 = "/pinctrl/spi2/spi2m1-cs1";
|
spi2m2_pins = "/pinctrl/spi2/spi2m2-pins";
|
spi2m2_cs0 = "/pinctrl/spi2/spi2m2-cs0";
|
spi2m2_cs1 = "/pinctrl/spi2/spi2m2-cs1";
|
spi3m1_pins = "/pinctrl/spi3/spi3m1-pins";
|
spi3m1_cs0 = "/pinctrl/spi3/spi3m1-cs0";
|
spi3m1_cs1 = "/pinctrl/spi3/spi3m1-cs1";
|
spi3m2_pins = "/pinctrl/spi3/spi3m2-pins";
|
spi3m2_cs0 = "/pinctrl/spi3/spi3m2-cs0";
|
spi3m2_cs1 = "/pinctrl/spi3/spi3m2-cs1";
|
spi3m3_pins = "/pinctrl/spi3/spi3m3-pins";
|
spi3m3_cs0 = "/pinctrl/spi3/spi3m3-cs0";
|
spi3m3_cs1 = "/pinctrl/spi3/spi3m3-cs1";
|
spi3m0_pins = "/pinctrl/spi3/spi3m0-pins";
|
spi3m0_cs0 = "/pinctrl/spi3/spi3m0-cs0";
|
spi3m0_cs1 = "/pinctrl/spi3/spi3m0-cs1";
|
spi4m0_pins = "/pinctrl/spi4/spi4m0-pins";
|
spi4m0_cs0 = "/pinctrl/spi4/spi4m0-cs0";
|
spi4m0_cs1 = "/pinctrl/spi4/spi4m0-cs1";
|
spi4m1_pins = "/pinctrl/spi4/spi4m1-pins";
|
spi4m1_cs0 = "/pinctrl/spi4/spi4m1-cs0";
|
spi4m1_cs1 = "/pinctrl/spi4/spi4m1-cs1";
|
spi4m2_pins = "/pinctrl/spi4/spi4m2-pins";
|
spi4m2_cs0 = "/pinctrl/spi4/spi4m2-cs0";
|
tsadcm1_shut = "/pinctrl/tsadc/tsadcm1-shut";
|
tsadc_shut = "/pinctrl/tsadc/tsadc-shut";
|
tsadc_shut_org = "/pinctrl/tsadc/tsadc-shut-org";
|
uart0m0_xfer = "/pinctrl/uart0/uart0m0-xfer";
|
uart0m1_xfer = "/pinctrl/uart0/uart0m1-xfer";
|
uart0m2_xfer = "/pinctrl/uart0/uart0m2-xfer";
|
uart0_ctsn = "/pinctrl/uart0/uart0-ctsn";
|
uart0_rtsn = "/pinctrl/uart0/uart0-rtsn";
|
uart1m1_xfer = "/pinctrl/uart1/uart1m1-xfer";
|
uart1m1_ctsn = "/pinctrl/uart1/uart1m1-ctsn";
|
uart1m1_rtsn = "/pinctrl/uart1/uart1m1-rtsn";
|
uart1m2_xfer = "/pinctrl/uart1/uart1m2-xfer";
|
uart1m2_ctsn = "/pinctrl/uart1/uart1m2-ctsn";
|
uart1m2_rtsn = "/pinctrl/uart1/uart1m2-rtsn";
|
uart1m0_xfer = "/pinctrl/uart1/uart1m0-xfer";
|
uart1m0_ctsn = "/pinctrl/uart1/uart1m0-ctsn";
|
uart1m0_rtsn = "/pinctrl/uart1/uart1m0-rtsn";
|
uart2m0_xfer = "/pinctrl/uart2/uart2m0-xfer";
|
uart2m1_xfer = "/pinctrl/uart2/uart2m1-xfer";
|
uart2m2_xfer = "/pinctrl/uart2/uart2m2-xfer";
|
uart2_ctsn = "/pinctrl/uart2/uart2-ctsn";
|
uart2_rtsn = "/pinctrl/uart2/uart2-rtsn";
|
uart3m0_xfer = "/pinctrl/uart3/uart3m0-xfer";
|
uart3m1_xfer = "/pinctrl/uart3/uart3m1-xfer";
|
uart3m2_xfer = "/pinctrl/uart3/uart3m2-xfer";
|
uart3_ctsn = "/pinctrl/uart3/uart3-ctsn";
|
uart3_rtsn = "/pinctrl/uart3/uart3-rtsn";
|
uart4m0_xfer = "/pinctrl/uart4/uart4m0-xfer";
|
uart4m1_xfer = "/pinctrl/uart4/uart4m1-xfer";
|
uart4m2_xfer = "/pinctrl/uart4/uart4m2-xfer";
|
uart4_ctsn = "/pinctrl/uart4/uart4-ctsn";
|
uart4_rtsn = "/pinctrl/uart4/uart4-rtsn";
|
uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer";
|
uart5m0_ctsn = "/pinctrl/uart5/uart5m0-ctsn";
|
uart5m0_rtsn = "/pinctrl/uart5/uart5m0-rtsn";
|
uart5m1_xfer = "/pinctrl/uart5/uart5m1-xfer";
|
uart5m1_ctsn = "/pinctrl/uart5/uart5m1-ctsn";
|
uart5m1_rtsn = "/pinctrl/uart5/uart5m1-rtsn";
|
uart5m2_xfer = "/pinctrl/uart5/uart5m2-xfer";
|
uart6m1_xfer = "/pinctrl/uart6/uart6m1-xfer";
|
uart6m1_ctsn = "/pinctrl/uart6/uart6m1-ctsn";
|
uart6m1_rtsn = "/pinctrl/uart6/uart6m1-rtsn";
|
uart6m2_xfer = "/pinctrl/uart6/uart6m2-xfer";
|
uart6m0_xfer = "/pinctrl/uart6/uart6m0-xfer";
|
uart6m0_ctsn = "/pinctrl/uart6/uart6m0-ctsn";
|
uart6m0_rtsn = "/pinctrl/uart6/uart6m0-rtsn";
|
uart7m1_xfer = "/pinctrl/uart7/uart7m1-xfer";
|
uart7m1_ctsn = "/pinctrl/uart7/uart7m1-ctsn";
|
uart7m1_rtsn = "/pinctrl/uart7/uart7m1-rtsn";
|
uart7m2_xfer = "/pinctrl/uart7/uart7m2-xfer";
|
uart7m0_xfer = "/pinctrl/uart7/uart7m0-xfer";
|
uart7m0_ctsn = "/pinctrl/uart7/uart7m0-ctsn";
|
uart7m0_rtsn = "/pinctrl/uart7/uart7m0-rtsn";
|
uart8m0_xfer = "/pinctrl/uart8/uart8m0-xfer";
|
uart8m0_ctsn = "/pinctrl/uart8/uart8m0-ctsn";
|
uart8m0_rtsn = "/pinctrl/uart8/uart8m0-rtsn";
|
uart8m1_xfer = "/pinctrl/uart8/uart8m1-xfer";
|
uart8m1_ctsn = "/pinctrl/uart8/uart8m1-ctsn";
|
uart8m1_rtsn = "/pinctrl/uart8/uart8m1-rtsn";
|
uart8_xfer = "/pinctrl/uart8/uart8-xfer";
|
uart9m1_xfer = "/pinctrl/uart9/uart9m1-xfer";
|
uart9m1_ctsn = "/pinctrl/uart9/uart9m1-ctsn";
|
uart9m1_rtsn = "/pinctrl/uart9/uart9m1-rtsn";
|
uart9m2_xfer = "/pinctrl/uart9/uart9m2-xfer";
|
uart9m2_ctsn = "/pinctrl/uart9/uart9m2-ctsn";
|
uart9m2_rtsn = "/pinctrl/uart9/uart9m2-rtsn";
|
uart9m0_xfer = "/pinctrl/uart9/uart9m0-xfer";
|
uart9m0_ctsn = "/pinctrl/uart9/uart9m0-ctsn";
|
uart9m0_rtsn = "/pinctrl/uart9/uart9m0-rtsn";
|
vop_pins = "/pinctrl/vop/vop-pins";
|
bt656_pins = "/pinctrl/bt656/bt656-pins";
|
tsadc_gpio_func = "/pinctrl/gpio-func/tsadc-gpio-func";
|
pcfg_pull_none_drv_level_7 = "/pinctrl/pcfg-pull-none-drv-level-7";
|
pcfg_pull_none_drv_level_8 = "/pinctrl/pcfg-pull-none-drv-level-8";
|
pcfg_pull_none_drv_level_9 = "/pinctrl/pcfg-pull-none-drv-level-9";
|
pcfg_pull_none_drv_level_10 = "/pinctrl/pcfg-pull-none-drv-level-10";
|
pcfg_pull_none_drv_level_11 = "/pinctrl/pcfg-pull-none-drv-level-11";
|
pcfg_pull_none_drv_level_12 = "/pinctrl/pcfg-pull-none-drv-level-12";
|
pcfg_pull_none_drv_level_13 = "/pinctrl/pcfg-pull-none-drv-level-13";
|
pcfg_pull_none_drv_level_14 = "/pinctrl/pcfg-pull-none-drv-level-14";
|
pcfg_pull_none_drv_level_15 = "/pinctrl/pcfg-pull-none-drv-level-15";
|
pcfg_pull_up_drv_level_7 = "/pinctrl/pcfg-pull-up-drv-level-7";
|
pcfg_pull_up_drv_level_8 = "/pinctrl/pcfg-pull-up-drv-level-8";
|
pcfg_pull_up_drv_level_9 = "/pinctrl/pcfg-pull-up-drv-level-9";
|
pcfg_pull_up_drv_level_10 = "/pinctrl/pcfg-pull-up-drv-level-10";
|
pcfg_pull_up_drv_level_11 = "/pinctrl/pcfg-pull-up-drv-level-11";
|
pcfg_pull_up_drv_level_12 = "/pinctrl/pcfg-pull-up-drv-level-12";
|
pcfg_pull_up_drv_level_13 = "/pinctrl/pcfg-pull-up-drv-level-13";
|
pcfg_pull_up_drv_level_14 = "/pinctrl/pcfg-pull-up-drv-level-14";
|
pcfg_pull_up_drv_level_15 = "/pinctrl/pcfg-pull-up-drv-level-15";
|
pcfg_pull_down_drv_level_7 = "/pinctrl/pcfg-pull-down-drv-level-7";
|
pcfg_pull_down_drv_level_8 = "/pinctrl/pcfg-pull-down-drv-level-8";
|
pcfg_pull_down_drv_level_9 = "/pinctrl/pcfg-pull-down-drv-level-9";
|
pcfg_pull_down_drv_level_10 = "/pinctrl/pcfg-pull-down-drv-level-10";
|
pcfg_pull_down_drv_level_11 = "/pinctrl/pcfg-pull-down-drv-level-11";
|
pcfg_pull_down_drv_level_12 = "/pinctrl/pcfg-pull-down-drv-level-12";
|
pcfg_pull_down_drv_level_13 = "/pinctrl/pcfg-pull-down-drv-level-13";
|
pcfg_pull_down_drv_level_14 = "/pinctrl/pcfg-pull-down-drv-level-14";
|
pcfg_pull_down_drv_level_15 = "/pinctrl/pcfg-pull-down-drv-level-15";
|
eth0_pins = "/pinctrl/eth0/eth0-pins";
|
gmac0_miim = "/pinctrl/gmac0/gmac0-miim";
|
gmac0_clkinout = "/pinctrl/gmac0/gmac0-clkinout";
|
gmac0_rx_bus2 = "/pinctrl/gmac0/gmac0-rx-bus2";
|
gmac0_tx_bus2 = "/pinctrl/gmac0/gmac0-tx-bus2";
|
gmac0_rgmii_clk = "/pinctrl/gmac0/gmac0-rgmii-clk";
|
gmac0_rgmii_bus = "/pinctrl/gmac0/gmac0-rgmii-bus";
|
gmac0_ppsclk = "/pinctrl/gmac0/gmac0-ppsclk";
|
gmac0_ppstring = "/pinctrl/gmac0/gmac0-ppstring";
|
gmac0_ptp_refclk = "/pinctrl/gmac0/gmac0-ptp-refclk";
|
gmac0_txer = "/pinctrl/gmac0/gmac0-txer";
|
mipicsi0_pwr = "/pinctrl/cam/mipicsi0-pwr";
|
mipicsi1_pwr = "/pinctrl/cam/mipicsi1-pwr";
|
mipidcphy0_pwr = "/pinctrl/cam/mipidcphy0-pwr";
|
vga_hpdin_l = "/pinctrl/vga/vga-hpdin-l";
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hp_det = "/pinctrl/headphone/hp-det";
|
spk_con = "/pinctrl/headphone/spk-con";
|
hym8563_int = "/pinctrl/hym8563/hym8563-int";
|
lcd_rst_gpio = "/pinctrl/lcd/lcd-rst-gpio";
|
wifi_enable_h = "/pinctrl/sdio-pwrseq/wifi-enable-h";
|
touch_gpio = "/pinctrl/touch/touch-gpio";
|
vcc5v0_host_en = "/pinctrl/usb/vcc5v0-host-en";
|
uart9_gpios = "/pinctrl/wireless-bluetooth/uart9-gpios";
|
bt_reset_gpio = "/pinctrl/wireless-bluetooth/bt-reset-gpio";
|
ndj_io_gpio = "/pinctrl/ndj_io_init/ndj_io_gpio_col";
|
rkcif_mipi_lvds4 = "/rkcif-mipi-lvds4";
|
rkcif_mipi_lvds4_sditf = "/rkcif-mipi-lvds4-sditf";
|
rkcif_mipi_lvds4_sditf_vir1 = "/rkcif-mipi-lvds4-sditf-vir1";
|
rkcif_mipi_lvds4_sditf_vir2 = "/rkcif-mipi-lvds4-sditf-vir2";
|
rkcif_mipi_lvds4_sditf_vir3 = "/rkcif-mipi-lvds4-sditf-vir3";
|
rkcif_mipi_lvds5 = "/rkcif-mipi-lvds5";
|
rkcif_mipi_lvds5_sditf = "/rkcif-mipi-lvds5-sditf";
|
rkcif_mipi_lvds5_sditf_vir1 = "/rkcif-mipi-lvds5-sditf-vir1";
|
rkcif_mipi_lvds5_sditf_vir2 = "/rkcif-mipi-lvds5-sditf-vir2";
|
rkcif_mipi_lvds5_sditf_vir3 = "/rkcif-mipi-lvds5-sditf-vir3";
|
usbdrd3_1 = "/usbdrd3_1";
|
usbdrd_dwc3_1 = "/usbdrd3_1/usb@fc400000";
|
pcie30_phy_grf = "/syscon@fd5b8000";
|
pipe_phy1_grf = "/syscon@fd5c0000";
|
usbdpphy1_grf = "/syscon@fd5cc000";
|
usb2phy1_grf = "/syscon@fd5d4000";
|
u2phy1 = "/syscon@fd5d4000/usb2-phy@4000";
|
u2phy1_otg = "/syscon@fd5d4000/usb2-phy@4000/otg-port";
|
hdptxphy1_grf = "/syscon@fd5e4000";
|
spdif_tx5 = "/spdif-tx@fddb8000";
|
i2s8_8ch = "/i2s@fddc8000";
|
spdif_tx4 = "/spdif-tx@fdde8000";
|
i2s6_8ch = "/i2s@fddf4000";
|
i2s7_8ch = "/i2s@fddf8000";
|
i2s10_8ch = "/i2s@fde00000";
|
spdif_rx1 = "/spdif-rx@fde10000";
|
spdif_rx2 = "/spdif-rx@fde18000";
|
dp1 = "/dp@fde60000";
|
dp1_in_vp0 = "/dp@fde60000/ports/port@0/endpoint@0";
|
dp1_in_vp1 = "/dp@fde60000/ports/port@0/endpoint@1";
|
dp1_in_vp2 = "/dp@fde60000/ports/port@0/endpoint@2";
|
dp1_out = "/dp@fde60000/ports/port@1/endpoint";
|
hdmi1 = "/hdmi@fdea0000";
|
hdmi1_in = "/hdmi@fdea0000/ports/port@0";
|
hdmi1_in_vp0 = "/hdmi@fdea0000/ports/port@0/endpoint@0";
|
hdmi1_in_vp1 = "/hdmi@fdea0000/ports/port@0/endpoint@1";
|
hdmi1_in_vp2 = "/hdmi@fdea0000/ports/port@0/endpoint@2";
|
edp1 = "/edp@fded0000";
|
edp1_in_vp0 = "/edp@fded0000/ports/port@0/endpoint@0";
|
edp1_in_vp1 = "/edp@fded0000/ports/port@0/endpoint@1";
|
edp1_in_vp2 = "/edp@fded0000/ports/port@0/endpoint@2";
|
edp1_out_panel = "/edp@fded0000/ports/port@1/endpoint";
|
edp1_out = "/edp@fded0000/ports/port@1/endpoint";
|
hdmirx_ctrler = "/hdmirx-controller@fdee0000";
|
pcie3x4 = "/pcie@fe150000";
|
pcie3x4_intc = "/pcie@fe150000/legacy-interrupt-controller";
|
pcie3x2 = "/pcie@fe160000";
|
pcie3x2_intc = "/pcie@fe160000/legacy-interrupt-controller";
|
pcie2x1l0 = "/pcie@fe170000";
|
pcie2x1l0_intc = "/pcie@fe170000/legacy-interrupt-controller";
|
gmac_uio0 = "/uio@fe1b0000";
|
gmac0 = "/ethernet@fe1b0000";
|
mdio0 = "/ethernet@fe1b0000/mdio";
|
gmac0_stmmac_axi_setup = "/ethernet@fe1b0000/stmmac-axi-config";
|
gmac0_mtl_rx_setup = "/ethernet@fe1b0000/rx-queues-config";
|
gmac0_mtl_tx_setup = "/ethernet@fe1b0000/tx-queues-config";
|
sata1 = "/sata@fe220000";
|
hdptxphy1 = "/phy@fed70000";
|
hdptxphy_hdmi1 = "/hdmiphy@fed70000";
|
hdptxphy_hdmi_clk1 = "/hdmiphy@fed70000/clk-port";
|
usbdp_phy1 = "/phy@fed90000";
|
usbdp_phy1_dp = "/phy@fed90000/dp-port";
|
usbdp_phy1_u3 = "/phy@fed90000/u3-port";
|
combphy1_ps = "/phy@fee10000";
|
pcie30phy = "/phy@fee80000";
|
adc_keys = "/adc-keys";
|
backlight = "/backlight";
|
backlight1 = "/backlight1";
|
bt_sco = "/bt-sco";
|
bt_sound = "/bt-sound";
|
hdmi0_sound = "/hdmi0-sound";
|
hdmi1_sound = "/hdmi1-sound";
|
dp0_sound = "/dp0-sound";
|
dp1_sound = "/dp1-sound";
|
leds = "/leds";
|
work_led = "/leds/sys_led";
|
spdif_tx0_dc = "/spdif-tx0-dc";
|
spdif_tx0_sound = "/spdif-tx0-sound";
|
spdif_tx1_dc = "/spdif-tx1-dc";
|
spdif_tx1_sound = "/spdif-tx1-sound";
|
vcc12v_dcin = "/vcc12v-dcin";
|
vcc5v0_sys = "/vcc5v0-sys";
|
vcc5v0_usbdcin = "/vcc5v0-usbdcin";
|
vcc5v0_usb = "/vcc5v0-usb";
|
drm_logo = "/reserved-memory/drm-logo@00000000";
|
drm_cubic_lut = "/reserved-memory/drm-cubic-lut@00000000";
|
ramoops = "/reserved-memory/ramoops@110000";
|
es8316_sound = "/es8316-sound";
|
fan = "/pwm-fan";
|
pcie20_avdd0v85 = "/pcie20-avdd0v85";
|
pcie20_avdd1v8 = "/pcie20-avdd1v8";
|
pcie30_avdd0v75 = "/pcie30-avdd0v75";
|
pcie30_avdd1v8 = "/pcie30-avdd1v8";
|
sdio_pwrseq = "/sdio-pwrseq";
|
rk_headset = "/rk-headset";
|
vcc_1v1_nldo_s3 = "/vcc-1v1-nldo-s3";
|
vcc3v3_lcd_n = "/vcc3v3-lcd0-n";
|
vcc3v3_pcie30 = "/vcc3v3-pcie30";
|
vcc5v0_host = "/vcc5v0-host";
|
vcc_3v3_sd_s0 = "/vcc-3v3-sd-s0-regulator";
|
wireless_bluetooth = "/wireless-bluetooth";
|
wireless_wlan = "/wireless-wlan";
|
panel = "/panel";
|
timing0 = "/panel/display-timings/timing0";
|
panel_in_edp1 = "/panel/port/endpoint";
|
chosen = "/chosen";
|
cspmu = "/cspmu@fd10c000";
|
debug = "/debug@fd104000";
|
fiq_debugger = "/fiq-debugger";
|
};
|
};
|
