/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _IIO_REGS_H_
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#define _IIO_REGS_H_
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/**
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==================================================================================================
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================================== General Defintions ==================================
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==================================================================================================
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**/
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#define NUMBER_PORTS_PER_SOCKET 21
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#define IIO_UPLINK_PORT_INDEX 5 //Port 2A is the uplink port in Neon-City ///TODO Check if this is required for SKX/Purley SKX_TTEST
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#define MaxIIO MAX_SOCKET
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#if MAX_SOCKET > 4
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#define TOTAL_CB3_DEVICES 64 // Todo Check SKX CB3 devices (IOAT_TOTAL_FUNCS * MAX_SOCKET). Note: this covers up to 8S.
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#define MAX_TOTAL_PORTS 168 //NUMBER_PORTS_PER_SOCKET * MaxIIO. As now, treats setup S0-S3 = S4_S7 as optimal
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#else
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#define TOTAL_CB3_DEVICES 32 // Todo Check SKX CB3 devices.
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#define MAX_TOTAL_PORTS 84 //NUMBER_PORTS_PER_SOCKET * MaxIIO
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#endif
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#if MAX_SOCKET > 4
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#define TOTAL_IIO_STACKS 48 // MAX_SOCKET * MAX_IIO_STACK. Not reflect architecture but only sysHost structure!
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#define TOTAL_SYSTEM_IIO_STACKS 32 // In term of system architecture support
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#else
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#define TOTAL_IIO_STACKS 24 // MAX_SOCKET * MAX_IIO_STACK
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#define TOTAL_SYSTEM_IIO_STACKS 24 // In term of system architecture support
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#endif
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#define NUMBER_NTB_PORTS_PER_SOCKET 3
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#if MAX_SOCKET > 4
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#define MAX_NTB_PORTS 24 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET
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#else
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#define MAX_NTB_PORTS 12 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET
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#endif
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#define VMD_STACK_PER_SOCKET 3
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#define VMD_PORT_PER_STACK 4
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#define VMD_PORTS_PER_SOCKET 12
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#if MAX_SOCKET > 4
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#define MAX_VMD_PORTS 96 // VMD_PORTS_PER_SOCKET * MAX_SOCKET
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#define MAX_VMD_STACKS 24 // VMD_STACK_PER_SOCKET * MAX_SOCKET
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#else
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#define MAX_VMD_PORTS 48 // VMD_PORTS_PER_SOCKET * MAX_SOCKET
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#define MAX_VMD_STACKS 12 // VMD_STACK_PER_SOCKET * MAX_SOCKET
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#endif
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#define VARIABLE_FUNC3_ELEMENTS 4
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#if MAX_SOCKET > 4
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#define MAX_TOTAL_CORE_HIDE 32 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS)
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#else
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#define MAX_TOTAL_CORE_HIDE 16 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS)
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#endif
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#define MAX_IOU_PORT_DEVICES 4
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/**
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==================================================================================================
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================================== IIO Root Port Defintions ====================
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==================================================================================================
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**/
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typedef enum {
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IioPortA = 0,
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IioPortB = 1,
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IioPortC = 2,
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IioPortD = 3
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}IIOPORTS;
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typedef enum {
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IioIou0 = 0,
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IioIou1,
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IioIou2,
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IioMcp0,
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IioMcp1,
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IioIouMax
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} IIOIOUS;
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//
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// Bifurcation control register shorthand
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//
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#define IIO_BIFURCATE_AUTO 0xFF
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// Ports 1D-1A, 2D-2A, 3D-3A
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//
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#define IIO_BIFURCATE_x4x4x4x4 0
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#define IIO_BIFURCATE_x4x4xxx8 1
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#define IIO_BIFURCATE_xxx8x4x4 2
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#define IIO_BIFURCATE_xxx8xxx8 3
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#define IIO_BIFURCATE_xxxxxx16 4
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#define IIO_BIFURCATE_xxxxxxxx 0xF
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#define PORT_0_INDEX 0
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#define PCIE_PORT_2_DEV 0x02
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// IOU2
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#define PORT_1A_INDEX 1
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#define PORT_1B_INDEX 2
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#define PORT_1C_INDEX 3
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#define PORT_1D_INDEX 4
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// IOU0
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#define PORT_2A_INDEX 5
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#define PORT_2B_INDEX 6
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#define PORT_2C_INDEX 7
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#define PORT_2D_INDEX 8
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// IOU1
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#define PORT_3A_INDEX 9
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#define PORT_3B_INDEX 10
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#define PORT_3C_INDEX 11
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#define PORT_3D_INDEX 12
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//MCP0
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#define PORT_4A_INDEX 13
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#define PORT_4B_INDEX 14
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#define PORT_4C_INDEX 15
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#define PORT_4D_INDEX 16
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//MCP1
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#define PORT_5A_INDEX 17
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#define PORT_5B_INDEX 18
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#define PORT_5C_INDEX 19
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#define PORT_5D_INDEX 20
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//
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#define SOCKET_0_INDEX 0
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#define SOCKET_1_INDEX 21
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#define SOCKET_2_INDEX 42
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#define SOCKET_3_INDEX 63
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#define SOCKET_4_INDEX 84
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#define SOCKET_5_INDEX 105
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#define SOCKET_6_INDEX 126
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#define SOCKET_7_INDEX 147
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#define PCIE_PORT_0_DEV 0x00
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#define PCIE_PORT_0_FUNC 0x00
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#define PCIE_PORT_1A_DEV 0x00
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#define PCIE_PORT_1B_DEV 0x01
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#define PCIE_PORT_1C_DEV 0x02
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#define PCIE_PORT_1D_DEV 0x03
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#define PCIE_PORT_1A_FUNC 0x00
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#define PCIE_PORT_1B_FUNC 0x00
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#define PCIE_PORT_1C_FUNC 0x00
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#define PCIE_PORT_1D_FUNC 0x00
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#define PCIE_PORT_2A_DEV 0x00
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#define PCIE_PORT_2B_DEV 0x01
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#define PCIE_PORT_2C_DEV 0x02
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#define PCIE_PORT_2D_DEV 0x03
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#define PCIE_PORT_2A_FUNC 0x00
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#define PCIE_PORT_2B_FUNC 0x00
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#define PCIE_PORT_2C_FUNC 0x00
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#define PCIE_PORT_2D_FUNC 0x00
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#define PCIE_PORT_3A_DEV 0x00
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#define PCIE_PORT_3B_DEV 0x01
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#define PCIE_PORT_3C_DEV 0x02
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#define PCIE_PORT_3D_DEV 0x03
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#define PCIE_PORT_3A_FUNC 0x00
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#define PCIE_PORT_3B_FUNC 0x00
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#define PCIE_PORT_3C_FUNC 0x00
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#define PCIE_PORT_3D_FUNC 0x00
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#define PCIE_PORT_4A_DEV 0x00
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#define PCIE_PORT_4B_DEV 0x01
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#define PCIE_PORT_4C_DEV 0x02
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#define PCIE_PORT_4D_DEV 0x03
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#define PCIE_PORT_4A_FUNC 0x00
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#define PCIE_PORT_4B_FUNC 0x00
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#define PCIE_PORT_4C_FUNC 0x00
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#define PCIE_PORT_4D_FUNC 0x00
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#define PCIE_PORT_5A_DEV 0x00
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#define PCIE_PORT_5B_DEV 0x01
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#define PCIE_PORT_5C_DEV 0x02
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#define PCIE_PORT_5D_DEV 0x03
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#define PCIE_PORT_5A_FUNC 0x00
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#define PCIE_PORT_5B_FUNC 0x00
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#define PCIE_PORT_5C_FUNC 0x00
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#define PCIE_PORT_5D_FUNC 0x00
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#define PCIE_PORT_GLOBAL_RTO_DEV 0x07
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#define PCIE_PORT_GLOBAL_RTO_FUNC 0x07
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#define PCIE_PORT_0_RTO_DEV 0x07
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#define PCIE_PORT_0_RTO_FUNC 0x00
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#define PCIE_PORT_1A_RTO_DEV 0x07
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#define PCIE_PORT_1A_RTO_FUNC 0x00
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#define PCIE_PORT_1B_RTO_DEV 0x07
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#define PCIE_PORT_1B_RTO_FUNC 0x01
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#define PCIE_PORT_1C_RTO_DEV 0x07
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#define PCIE_PORT_1C_RTO_FUNC 0x02
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#define PCIE_PORT_1D_RTO_DEV 0x07
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#define PCIE_PORT_1D_RTO_FUNC 0x03
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#define PCIE_PORT_2A_RTO_DEV 0x07
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#define PCIE_PORT_2A_RTO_FUNC 0x00
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#define PCIE_PORT_2B_RTO_DEV 0x07
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#define PCIE_PORT_2B_RTO_FUNC 0x01
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#define PCIE_PORT_2C_RTO_DEV 0x07
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#define PCIE_PORT_2C_RTO_FUNC 0x02
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#define PCIE_PORT_2D_RTO_DEV 0x07
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#define PCIE_PORT_2D_RTO_FUNC 0x03
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#define PCIE_PORT_3A_RTO_DEV 0x07
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#define PCIE_PORT_3A_RTO_FUNC 0x00
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#define PCIE_PORT_3B_RTO_DEV 0x07
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#define PCIE_PORT_3B_RTO_FUNC 0x01
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#define PCIE_PORT_3C_RTO_DEV 0x07
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#define PCIE_PORT_3C_RTO_FUNC 0x02
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#define PCIE_PORT_3D_RTO_DEV 0x07
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#define PCIE_PORT_3D_RTO_FUNC 0x03
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#define PCIE_PORT_4A_RTO_DEV 0x07
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#define PCIE_PORT_4A_RTO_FUNC 0x00
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#define PCIE_PORT_4B_RTO_DEV 0x07
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#define PCIE_PORT_4B_RTO_FUNC 0x01
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#define PCIE_PORT_4C_RTO_DEV 0x07
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#define PCIE_PORT_4C_RTO_FUNC 0x02
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#define PCIE_PORT_4D_RTO_DEV 0x07
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#define PCIE_PORT_4D_RTO_FUNC 0x03
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#define PCIE_PORT_5A_RTO_DEV 0x07
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#define PCIE_PORT_5A_RTO_FUNC 0x00
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#define PCIE_PORT_5B_RTO_DEV 0x07
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#define PCIE_PORT_5B_RTO_FUNC 0x01
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#define PCIE_PORT_5C_RTO_DEV 0x07
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#define PCIE_PORT_5C_RTO_FUNC 0x02
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#define PCIE_PORT_5D_RTO_DEV 0x07
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#define PCIE_PORT_5D_RTO_FUNC 0x03
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#define PCIE_PORT_0_LINK_SEL 0x00
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#define PCIE_PORT_1A_LINK_SEL 0x00
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#define PCIE_PORT_1B_LINK_SEL 0x01
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#define PCIE_PORT_1C_LINK_SEL 0x02
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#define PCIE_PORT_1D_LINK_SEL 0x03
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#define PCIE_PORT_2A_LINK_SEL 0x00
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#define PCIE_PORT_2B_LINK_SEL 0x01
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#define PCIE_PORT_2C_LINK_SEL 0x02
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#define PCIE_PORT_2D_LINK_SEL 0x03
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#define PCIE_PORT_3A_LINK_SEL 0x00
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#define PCIE_PORT_3B_LINK_SEL 0x01
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#define PCIE_PORT_3C_LINK_SEL 0x02
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#define PCIE_PORT_3D_LINK_SEL 0x03
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#define PCIE_PORT_4A_LINK_SEL 0x00
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#define PCIE_PORT_4B_LINK_SEL 0x01
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#define PCIE_PORT_4C_LINK_SEL 0x02
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#define PCIE_PORT_4D_LINK_SEL 0x03
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#define PCIE_PORT_5A_LINK_SEL 0x00
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#define PCIE_PORT_5B_LINK_SEL 0x01
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#define PCIE_PORT_5C_LINK_SEL 0x02
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#define PCIE_PORT_5D_LINK_SEL 0x03
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#define PCIE_PORT_0_SUPER_CLUSTER_PORT 0x00
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#define PCIE_PORT_1A_SUPER_CLUSTER_PORT 0x01
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#define PCIE_PORT_1B_SUPER_CLUSTER_PORT 0x01
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#define PCIE_PORT_1C_SUPER_CLUSTER_PORT 0x01
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#define PCIE_PORT_1D_SUPER_CLUSTER_PORT 0x01
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#define PCIE_PORT_2A_SUPER_CLUSTER_PORT 0x05
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#define PCIE_PORT_2B_SUPER_CLUSTER_PORT 0x05
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#define PCIE_PORT_2C_SUPER_CLUSTER_PORT 0x05
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#define PCIE_PORT_2D_SUPER_CLUSTER_PORT 0x05
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#define PCIE_PORT_3A_SUPER_CLUSTER_PORT 0x09
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#define PCIE_PORT_3B_SUPER_CLUSTER_PORT 0x09
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#define PCIE_PORT_3C_SUPER_CLUSTER_PORT 0x09
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#define PCIE_PORT_3D_SUPER_CLUSTER_PORT 0x09
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#define PCIE_PORT_4A_SUPER_CLUSTER_PORT 0x0D
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#define PCIE_PORT_4B_SUPER_CLUSTER_PORT 0x0D
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#define PCIE_PORT_4C_SUPER_CLUSTER_PORT 0x0D
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#define PCIE_PORT_4D_SUPER_CLUSTER_PORT 0x0D
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#define PCIE_PORT_5A_SUPER_CLUSTER_PORT 0x11
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#define PCIE_PORT_5B_SUPER_CLUSTER_PORT 0x11
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#define PCIE_PORT_5C_SUPER_CLUSTER_PORT 0x11
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#define PCIE_PORT_5D_SUPER_CLUSTER_PORT 0x11
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#define PORT_LINK_WIDTH_x16 16
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#define PORT_LINK_WIDTH_x8 8
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#define PORT_LINK_WIDTH_x4 4
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#define PORT_LINK_WIDTH_x2 2
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#define PORT_LINK_WIDTH_x1 1
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//
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// Port Config Mode
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//
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#define REGULAR_PCIE_OWNERSHIP 0
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#define PCIE_PORT_REGULAR_MODE 1
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#define PCIE_PORT_NTB_MODE 2
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#define VMD_OWNERSHIP 3
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#define PCIEAIC_OCL_OWNERSHIP 4
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/**
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==================================================================================================
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================================== Devide Hide Definitions =======================================
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==================================================================================================
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**/
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#define NUM_DEVHIDE_REGS 8
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// Hide all 8 Devices for every Stack
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#define MAX_DEVHIDE_REGS (MAX_IIO_STACK * NUM_DEVHIDE_REGS)
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#if MaxIIO > 4
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#define MAX_DEVHIDE_REGS_PER_SYSTEM 384 //(MAX_DEVHIDE_REGS * MaxIIO)
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#else
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#define MAX_DEVHIDE_REGS_PER_SYSTEM 192 //(MAX_DEVHIDE_REGS * MaxIIO)
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#endif
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#endif //_IIO_REGS_H_
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