/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _IIO_PLATFORM_DATA_H_
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#define _IIO_PLATFORM_DATA_H_
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#include <SysRegs.h>
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#include <KtiSi.h>
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#include <IioRegs.h>
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#include <IioConfig.h>
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#ifndef MINIBIOS_BUILD
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#ifndef IA32
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#include <Uefi.h>
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#include <PiDxe.h>
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#include <Protocol/CpuCsrAccess.h>
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#define IIO_CPU_CSR_ACCESS EFI_CPU_CSR_ACCESS_PROTOCOL
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#endif
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#endif
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#define IIO_HANDLE VOID *
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#define IIO_STATUS UINT32
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typedef struct {
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UINT8 Register;
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UINT8 Function;
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UINT8 Device;
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UINT8 Bus;
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UINT32 ExtendedRegister;
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} PCI_ROOT_BRIDGE_PCI_ADDRESS;
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typedef enum {
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DmiTypeVc0,
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DmiTypeVc1,
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DmiTypeVcm,
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MaxDmiVcType
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} DMI_VC_TYPE;
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typedef enum {
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IioDmiTc0,
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IioDmiTc1,
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IioDmiTc2,
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IioDmiTc3,
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IioDmiTc4,
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IioDmiTc5,
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IioDmiTc6,
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IioDmiTc7,
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IioMaxDmiTc
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} IIO_DMI_TC;
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typedef enum {
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IIOInitPhase1 = 1,
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IIOInitPhase2 = 2,
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IIOInitPhase3 = 4,
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} IIO_INIT_PHASE;
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typedef enum {
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IioBeforeBifurcation, // Point before IOU Bi-fucuation and link training, no generic inbound access at this point
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IioAfterBifurcation, // Point immediately after IOU bifurcation and link training but before any PCIe root port initialization
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IioPortEnumeration, // Point before Port initialization, no generic inbound access at this point
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IioPortEnumProgramMISCCTRL, // Inside IioPortInit.PcieSlotInit
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IioEnumEnd,
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IioVtDPreEn,
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IioVtDInit,
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IioVtDEn, // At this point it has been decided to enable VtD through setup IioVtdInit.VtdInitialization
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IioPostInitEnd, // this is the last stage of IIO PCIe port init
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IioBeforeResources, // At this point IIO Ports configuration has been completed
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IioAfterResources, // At this point PCIe Resources allocation has been completed
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IioReadyToBoot
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} IIO_INIT_ENUMERATION;
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extern const CHAR* IioPortLabel[];
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#define IIO_PORT_LABEL(x) ( ((x) < NUMBER_PORTS_PER_SOCKET) ? (IioPortLabel[(x)]) : IioPortLabel[NUMBER_PORTS_PER_SOCKET] )
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#pragma pack(1)
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typedef union{
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struct{
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UINT32 Value;
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UINT32 ValueHigh;
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}Address32bit;
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UINT64 Address64bit;
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}IIO_PTR_ADDRESS;
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typedef struct {
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UINT32 Device;
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UINT32 Function;
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UINT32 RegOffset;
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UINT32 AndMask;
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UINT32 OrMask;
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} PCI_OP_STRUCT;
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typedef struct {
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UINT32 Instance;
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UINT32 RegOffset;
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UINT32 AndMask;
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UINT32 OrMask;
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} CSR_ACCESS_OP_STRUCT;
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typedef struct {
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UINT8 Isoc;
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UINT32 meRequestedSize;
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UINT8 Vc1_pri_en;
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UINT8 Isoc_Enable;
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} ISOC_VC_TABLE_STRUCT;
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/*
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* Following are the data structure defined to support multiple CBDMA types on a system
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*/
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typedef struct{
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UINT32 DcaSupported : 1;
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UINT32 NoSnoopSupported : 1;
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UINT32 RelaxOrderSupported : 1;
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}CB_CONFIG_CAPABILITY;
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typedef struct{
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UINT8 CB_VER;
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UINT8 BusNo;
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UINT8 DevNo;
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UINT8 FunNo;
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UINT8 MaxNoChannels;
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CB_CONFIG_CAPABILITY CBConfigCap;
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}CBDMA_CONTROLLER;
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typedef struct{
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CBDMA_CONTROLLER CbDmaDevice;
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}DMA_HOST;
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// <<<< end of CBDMA data structures >>>>
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typedef union {
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struct {
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UINT32 Dev0 : 1;
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UINT32 Dev1 : 1;
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UINT32 Dev2 : 1;
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UINT32 Dev3 : 1;
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UINT32 Dev4 : 1;
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UINT32 Dev5 : 1;
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UINT32 Dev6 : 1;
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UINT32 Dev7 : 1;
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UINT32 Dev8 : 1;
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UINT32 Dev9 : 1;
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UINT32 Dev10 : 1;
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UINT32 Dev11 : 1;
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UINT32 Dev12 : 1;
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UINT32 Dev13 : 1;
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UINT32 Dev14 : 1;
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UINT32 Dev15 : 1;
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UINT32 Dev16 : 1;
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UINT32 Dev17 : 1;
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UINT32 Dev18 : 1;
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UINT32 Dev19 : 1;
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UINT32 Dev20 : 1;
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UINT32 Dev21 : 1;
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UINT32 Dev22 : 1;
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UINT32 Dev23 : 1;
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UINT32 Dev24 : 1;
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UINT32 Dev25 : 1;
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UINT32 Dev26 : 1;
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UINT32 Dev27 : 1;
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UINT32 Dev28 : 1;
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UINT32 Dev29 : 1;
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UINT32 Dev30 : 1;
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UINT32 Dev31 : 1;
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} Bits;
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UINT32 Data;
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} DEVHIDE_FIELD;
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typedef struct{
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UINT32 DevToHide[NUM_DEVHIDE_REGS];
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} IIO_DEVFUNHIDE;
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typedef struct{
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IIO_DEVFUNHIDE IioStackDevHide[MAX_IIO_STACK];
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}IIO_DEVFUNHIDE_TABLE;
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typedef struct {
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UINT8 CpuType;
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UINT8 CpuStepping;
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UINT8 CpuSubType;
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UINT8 SystemRasType;
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UINT8 IsocEnable;
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UINT8 EVMode;
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UINT32 meRequestedSize;
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UINT8 DmiVc[MaxDmiVcType];
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UINT8 DmiVcId[MaxDmiVcType];
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DMI_VC_TYPE DmiTc[IioMaxDmiTc];
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UINT8 PlatformType;
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UINT8 IOxAPICCallbackBootEvent;
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UINT8 RasOperation;
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UINT8 SocketUnderOnline;
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UINT8 CompletedReadyToBootEventServices;
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UINT8 SocketPresent[MaxIIO];
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UINT8 SocketBaseBusNumber[MaxIIO];
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UINT8 SocketLimitBusNumber[MaxIIO];
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UINT8 StackPresentBitmap[MaxIIO];
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UINT64_STRUCT SegMmcfgBase[MaxIIO];
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UINT8 SegmentSocket[MaxIIO];
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UINT8 SocketStackPersonality[MaxIIO][MAX_IIO_STACK];
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UINT8 SocketStackBus[MaxIIO][MAX_IIO_STACK];
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UINT8 SocketStackBaseBusNumber[MaxIIO][MAX_IIO_STACK];
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UINT8 SocketStackLimitBusNumber[MaxIIO][MAX_IIO_STACK];
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UINT8 SocketPortBusNumber[MaxIIO][NUMBER_PORTS_PER_SOCKET];
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UINT8 StackPerPort[MaxIIO][NUMBER_PORTS_PER_SOCKET];
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UINT8 SocketUncoreBusNumber[MaxIIO];
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UINT32 PchIoApicBase;
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UINT32 PciResourceMem32Base[MaxIIO];
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UINT32 PciResourceMem32Limit[MaxIIO];
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UINT8 Pci64BitResourceAllocation;
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UINT32 StackPciResourceMem32Limit[MaxIIO][MAX_IIO_STACK];
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UINT32 VtdBarAddress[MaxIIO][MAX_IIO_STACK];
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UINT32 IoApicBase[MaxIIO][MAX_IIO_STACK];
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UINT32 RcBaseAddress;
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UINT64 PciExpressBase;
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UINT32 PmBase;
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UINT32 PchSegRegBaseAddress;
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UINT8 PcieRiser1Type;
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UINT8 PcieRiser2Type;
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UINT8 DmiVc1;
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UINT8 DmiVcm;
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UINT8 Emulation;
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UINT8 SkuPersonality[MAX_SOCKET];
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UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK];
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UINT8 IODC;
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UINT8 MultiPch;
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UINT8 FpgaActive[MaxIIO];
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} IIO_V_DATA;
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typedef struct {
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UINT8 Device;
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UINT8 Function;
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} IIO_PORT_INFO;
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typedef struct {
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UINT8 Valid;
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UINT8 IioUplinkPortIndex; //defines platform specific uplink port index (if any else FF)
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IIO_PORT_INFO UplinkPortInfo;
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}IIO_UPLINK_PORT_INFO;
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typedef struct _INTEL_IIO_PORT_INFO {
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UINT8 Device;
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UINT8 Function;
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UINT8 RtoDevice;
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UINT8 RtoFunction;
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UINT8 RtoClusterDevice;
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UINT8 RtoClusterFunction;
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UINT8 RtoReutLinkSel;
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UINT8 SuperClusterPort;
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} INTEL_IIO_PORT_INFO;
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typedef struct _INTEL_DMI_PCIE_INFO {
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INTEL_IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET];
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} INTEL_DMI_PCIE_INFO;
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typedef struct _INTEL_IIO_PRELINK_DATA {
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INTEL_DMI_PCIE_INFO PcieInfo;
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IIO_UPLINK_PORT_INFO UplinkInfo[MaxIIO];
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} INTEL_IIO_PRELINK_DATA;
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typedef struct {
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UINT8 PciePortPresent[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 PciePortConfig[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 PciePortOwnership[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 CurrentPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 MaxPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 LinkedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 SpeedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 LaneReversedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 PciePortMaxWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 PciePortNegWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 PciePortNegSpeed[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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IIO_PTR_ADDRESS PtrAddress;
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IIO_PTR_ADDRESS PtrPcieTopology;
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UINT64 McastRsvdMemory;
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DMA_HOST DMAhost[MaxIIO];
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UINT8 resetRequired;
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} IIO_OUT_DATA;
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typedef struct {
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IIO_V_DATA IioVData;
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INTEL_IIO_PRELINK_DATA PreLinkData;
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IIO_OUT_DATA IioOutData;
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} IIO_VAR;
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typedef struct {
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IIO_CONFIG SetupData;
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IIO_VAR IioVar;
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} IIO_GLOBALS;
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#pragma pack()
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#endif //_IIO_PLATFORM_DATA_H_
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