/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _IIO_CONFIG_H
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#define _IIO_CONFIG_H
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#pragma pack(1) //to align members on byte boundary
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typedef struct {
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/**
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==================================================================================================
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================================== VTd Setup Options ==================================
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==================================================================================================
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**/
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UINT8 VTdSupport;
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UINT8 InterruptRemap;
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UINT8 CoherencySupport;
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UINT8 ATS;
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UINT8 PostedInterrupt;
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UINT8 PassThroughDma;
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/**
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==================================================================================================
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================================== PCIE Setup Options ==================================
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==================================================================================================
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**/
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UINT8 IioPresent[MAX_SOCKET];
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UINT8 VtdAcsWa;
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// Platform data needs to update these PCI Configuration settings
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UINT8 SLOTIMP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Implemented - PCIE Capabilities (D0-10 / F0 / R0x92 / B8)
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UINT16 SLOTPSP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Physical slot Number - Slot Capabilities (D0-10 / F0 / R0xA4 / B31:19). Change to use 13 bits instead of 8
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UINT8 SLOTEIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
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UINT8 SLOTSPLS[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Power Limit Scale - Slot Capabilities (D0-10 / F0 / R0xA4 / B16:15)
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UINT8 SLOTSPLV[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Power Limit Value - Slot Capabilities (D0-10 / F0 / R0xA4 / B14:7)
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UINT8 SLOTHPCAP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6)
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UINT8 SLOTHPSUP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
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UINT8 SLOTPIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
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UINT8 SLOTAIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
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UINT8 SLOTMRLSP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2)
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UINT8 SLOTPCP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1)
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UINT8 SLOTABP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
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UINT8 PcieSSDCapable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Indicate if Port will PcieSSD capable.
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// General PCIE Configuration
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UINT8 ConfigIOU0[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P5p6p7p8)
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UINT8 ConfigIOU1[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P9p10p11p12)
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UINT8 ConfigIOU2[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4)
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UINT8 ConfigMCP0[MAX_SOCKET]; // 04-x16 (p13)
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UINT8 ConfigMCP1[MAX_SOCKET]; // 04-x16 (p14)
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UINT8 CompletionTimeoutGlobal; //
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UINT8 CompletionTimeoutGlobalValue;
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UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup
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UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup
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UINT8 CoherentReadPart;
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UINT8 CoherentReadFull;
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UINT8 PcieGlobalAspm; //
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UINT8 StopAndScream; //
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UINT8 SnoopResponseHoldOff; //
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//
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// PCIE capability
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//
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UINT8 PCIe_LTR; //
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UINT8 PcieExtendedTagField; //
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UINT8 PCIe_AtomicOpReq; //
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UINT8 PcieMaxReadRequestSize; //
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UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup
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UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup
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UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup
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// mixc PCIE configuration
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UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup
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UINT8 PcieAspm[MAX_TOTAL_PORTS]; // On Setup
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UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup
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UINT8 PcieMaxPayload[MAX_TOTAL_PORTS]; // On Setup PRD
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UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup
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UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; //On Setup
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UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; //On Setup
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UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup
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UINT8 ExtendedSync[MAX_TOTAL_PORTS]; // On Setup
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UINT8 InbandPresenceDetect[MAX_TOTAL_PORTS]; // Not implemented in code
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UINT8 PciePortDisable[MAX_TOTAL_PORTS]; // Not implemented in code
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UINT8 PciePmeIntEn[MAX_TOTAL_PORTS]; // Not implemented in code
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UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup
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//
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// VPP Control
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//
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UINT8 VppEnable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -- Disable, 01 -- Enable //no setup option defined- aj
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UINT8 VppPort[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -- Port 0, 01 -- Port 1 //no setup option defined- aj
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UINT8 VppAddress[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 01-07 for SMBUS address of Vpp //no setup option defined- aj
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//
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// PCIE setup options for Link Control2
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//
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UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS]; //on Setup
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UINT8 ComplianceMode[MAX_TOTAL_PORTS]; // On Setup PRD
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UINT8 PciePortLinkMaxWidth[MAX_TOTAL_PORTS]; // On Setup
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UINT8 DeEmphasis[MAX_TOTAL_PORTS]; // On Setup
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//
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// PCIE setup options for MISCCTRLSTS
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//
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UINT8 EOI[MAX_TOTAL_PORTS]; // On Setup
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UINT8 MSIFATEN[MAX_TOTAL_PORTS]; //On Setup.
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UINT8 MSINFATEN[MAX_TOTAL_PORTS]; //On Setup.
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UINT8 MSICOREN[MAX_TOTAL_PORTS]; //On Setup.
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UINT8 ACPIPMEn[MAX_TOTAL_PORTS]; //On Setup
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UINT8 DISL0STx[MAX_TOTAL_PORTS]; //On Setup
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UINT8 P2PWrtDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 Peer
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UINT8 P2PRdDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 peer
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UINT8 DisPMETOAck[MAX_TOTAL_PORTS]; //On Setup
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UINT8 ACPIHP[MAX_TOTAL_PORTS]; //On Setup
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UINT8 ACPIPM[MAX_TOTAL_PORTS]; //On Setup
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UINT8 SRIS[MAX_TOTAL_PORTS]; //On Setup
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UINT8 TXEQ[MAX_TOTAL_PORTS]; //On Setup
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UINT8 ECRC[MAX_TOTAL_PORTS]; //On Setup
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//
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// PCIE RAS (Errors)
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//
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UINT8 PcieUnsupportedRequests[MAX_TOTAL_PORTS]; // Unsupported Request per-port option
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UINT8 Serr;
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UINT8 Perr;
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UINT8 IioErrorEn;
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UINT8 LerEn;
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UINT8 WheaPcieErrInjEn;
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//
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// PciePll
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//
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UINT8 PciePllSsc; //On Setup
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//
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// PCIE Link Training Ctrl
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//
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/**
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==================================================================================================
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================================== Crystal Beach 3 Setup Options ===========================
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==================================================================================================
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**/
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UINT8 Reserved1[MAX_SOCKET]; // on setup
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UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup
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UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup
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UINT8 DisableTPH;
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UINT8 PrioritizeTPH;
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UINT8 CbRelaxedOrdering;
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/**
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==================================================================================================
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================================== MISC IOH Setup Options ==========================
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==================================================================================================
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**/
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// The following are for hiding each individual device and function
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UINT8 PEXPHIDE[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD
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UINT8 PCUF6Hide; // Hide Device PCU Device 30, Function 6
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UINT8 EN1K; // Enable/Disable 1K granularity of IO for P2P bridges 0:20:0:98 bit 2
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UINT8 DualCvIoFlow; // Dual CV IO Flow
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UINT8 PcieBiosTrainEnable; // Used as a work around for A0 PCIe
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UINT8 MultiCastEnable; // MultiCastEnable test enable
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UINT8 McastBaseAddrRegion; // McastBaseAddrRegion
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UINT8 McastIndexPosition; // McastIndexPosition
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UINT8 McastNumGroup; // McastNumGroup
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UINT8 MctpEn;
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UINT8 LegacyVgaSoc;
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UINT8 LegacyVgaStack;
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UINT8 HidePEXPMenu[MAX_TOTAL_PORTS]; // to suppress /display the PCIe port menu
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/**
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==================================================================================================
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================================== NTB Related Setup Options ==========================
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==================================================================================================
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**/
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UINT8 NtbPpd[MAX_NTB_PORTS]; //on setup option
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UINT8 NtbBarSizeOverride[MAX_NTB_PORTS]; //on setup option
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UINT8 NtbSplitBar[MAX_NTB_PORTS]; //on setup option
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UINT8 NtbBarSizePBar23[MAX_NTB_PORTS]; //on setup option
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UINT8 NtbBarSizePBar45[MAX_NTB_PORTS]; //on setup option
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UINT8 NtbBarSizePBar4[MAX_NTB_PORTS]; //on setup option
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UINT8 NtbBarSizePBar5[MAX_NTB_PORTS]; //on setup option
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UINT8 NtbBarSizeSBar23[MAX_NTB_PORTS]; //on setup option
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UINT8 NtbBarSizeSBar45[MAX_NTB_PORTS]; //on setup option
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UINT8 NtbBarSizeSBar4[MAX_NTB_PORTS]; //on setup option
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UINT8 NtbBarSizeSBar5[MAX_NTB_PORTS]; //on setup option
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UINT8 NtbSBar01Prefetch[MAX_NTB_PORTS]; //on setup option
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UINT8 NtbXlinkCtlOverride[MAX_NTB_PORTS]; //on setup option
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/**
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==================================================================================================
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================================== VMD Related Setup Options ==========================
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==================================================================================================
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**/
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UINT8 VMDEnabled[MAX_VMD_STACKS];
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UINT8 VMDPortEnable[MAX_VMD_PORTS];
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UINT8 VMDHotPlugEnable[MAX_VMD_STACKS];
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UINT8 VMDCfgBarSz[MAX_VMD_STACKS];
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UINT8 VMDCfgBarAttr[MAX_VMD_STACKS];
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UINT8 VMDMemBarSz1[MAX_VMD_STACKS];
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UINT8 VMDMemBar1Attr[MAX_VMD_STACKS];
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UINT8 VMDMemBarSz2[MAX_VMD_STACKS];
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UINT8 VMDMemBar2Attr[MAX_VMD_STACKS];
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/**
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==================================================================================================
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================================== PcieSSD Related Setup Options ==========================
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==================================================================================================
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**/
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UINT8 PcieAICEnabled[MAX_VMD_STACKS]; // Indicate if PCIE AIC Device will be connected behind an specific IOUx
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UINT8 PcieAICPortEnable[MAX_VMD_PORTS];
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UINT8 PcieAICHotPlugEnable[MAX_VMD_STACKS];
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/**
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==================================================================================================
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================================== Gen3 Related Setup Options ==========================
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==================================================================================================
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**/
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//PCIE Global Option
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UINT8 NoSnoopRdCfg; //on Setup
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UINT8 NoSnoopWrCfg; //on Setup
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UINT8 MaxReadCompCombSize; //on Setup
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UINT8 ProblematicPort; //on Setup
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UINT8 DmiAllocatingFlow; //on Setup
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UINT8 PcieAllocatingFlow; //on Setup
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UINT8 PcieHotPlugEnable; //on Setup
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UINT8 PcieAcpiHotPlugEnable; //on Setup
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UINT8 HaltOnDmiDegraded; //on Setup
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UINT8 RxClockWA;
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UINT8 GlobalPme2AckTOCtrl; //on Setup
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UINT8 PcieSlotOprom1; //On Setup
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UINT8 PcieSlotOprom2; //On Setup
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UINT8 PcieSlotOprom3; //On Setup
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UINT8 PcieSlotOprom4; //On Setup
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UINT8 PcieSlotOprom5; //On Setup
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UINT8 PcieSlotOprom6; //On Setup
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UINT8 PcieSlotOprom7; //On Setup
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UINT8 PcieSlotOprom8; //On Setup
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UINT8 PcieSlotItemCtrl; //On Setup
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UINT8 PcieRelaxedOrdering; //On Setup
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UINT8 PciePhyTestMode; //On setup
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/**
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==================================================================================================
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================================== IOAPIC Related Setup Options ==========================
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==================================================================================================
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**/
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UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS];
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/**
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==================================================================================================
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================================== Security Related Setup Options ==========================
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==================================================================================================
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**/
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UINT8 LockChipset;
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UINT8 PeciInTrustControlBit;
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UINT8 ProcessorX2apic;
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UINT8 ProcessorMsrLockControl;
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/**
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==================================================================================================
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================================== Iio Related Setup Options ==========================
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==================================================================================================
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**/
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UINT8 RtoEnable; // On Setup
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UINT8 RtoLtssmLogger; // On Setup
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UINT8 RtoLtssmLoggerStop; // On Setup
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UINT8 RtoLtssmLoggerSpeed; // On Setup
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UINT8 RtoLtssmLoggerMask; // On Setup
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UINT8 RtoJitterLogger; // On Setup
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UINT32 RtoSocketDevFuncHide[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup
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UINT8 RtoGen3NTBTestCard[MAX_TOTAL_PORTS]; // On Setup
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UINT8 RtoGen3OverrideMode[MAX_TOTAL_PORTS]; //On Setup
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UINT8 RtoGen3TestCard[MAX_TOTAL_PORTS]; //On Setup
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UINT8 RtoGen3ManualPh2_Precursor[MAX_TOTAL_PORTS]; //On Setup
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UINT8 RtoGen3ManualPh2_Cursor[MAX_TOTAL_PORTS]; //On Setup
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UINT8 RtoGen3ManualPh2_Postcursor[MAX_TOTAL_PORTS]; //On Setup
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UINT8 RtoGen3ManualPh3_Precursor[MAX_TOTAL_PORTS]; //On Setup
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UINT8 RtoGen3ManualPh3_Cursor[MAX_TOTAL_PORTS]; //On Setup
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UINT8 RtoGen3ManualPh3_Postcursor[MAX_TOTAL_PORTS]; //On Setup
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UINT8 RtoDnTxPreset[MAX_TOTAL_PORTS]; //On Setup
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UINT8 RtoRxPreset[MAX_TOTAL_PORTS]; //On Setup
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UINT8 RtoUpTxPreset[MAX_TOTAL_PORTS]; //On Setup
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UINT8 InboundConfiguration[MAX_TOTAL_PORTS]; //On Setup
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} IIO_CONFIG;
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#pragma pack()
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#endif // _IIO_CONFIG_H
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