/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __KIRIN_DRM_DSI_H__
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#define __KIRIN_DRM_DSI_H__
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/of_graph.h>
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#include <linux/iopoll.h>
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#include <video/mipi_display.h>
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#include <linux/gpio/consumer.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <drm/drm_of.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_encoder_slave.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_panel.h>
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#define ROUND(x, y) ((x) / (y) + ((x) % (y) * 10 / (y) >= 5 ? 1 : 0))
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#define PHY_REF_CLK_RATE 19200000
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#define PHY_REF_CLK_PERIOD_PS (1000000000 / (PHY_REF_CLK_RATE / 1000))
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#define encoder_to_dsi(encoder) container_of(encoder, struct dw_dsi, encoder)
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#define host_to_dsi(host) container_of(host, struct dw_dsi, host)
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#define connector_to_dsi(connector) \
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container_of(connector, struct dw_dsi, connector)
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enum dsi_output_client { OUT_HDMI = 0, OUT_PANEL, OUT_MAX };
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struct dsi_phy_range {
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u32 min_range_kHz;
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u32 max_range_kHz;
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u32 pll_vco_750M;
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u32 hstx_ckg_sel;
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};
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static const struct dsi_phy_range dphy_range_info[] = {
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{ 46875, 62500, 1, 7 },
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{ 62500, 93750, 0, 7 },
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{ 93750, 125000, 1, 6 },
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{ 125000, 187500, 0, 6 },
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{ 187500, 250000, 1, 5 },
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{ 250000, 375000, 0, 5 },
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{ 375000, 500000, 1, 4 },
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{ 500000, 750000, 0, 4 },
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{ 750000, 1000000, 1, 0 },
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{ 1000000, 1500000, 0, 0 }
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};
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struct dsi_hw_ctx {
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void __iomem *base;
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char __iomem *peri_crg_base;
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struct clk *pclk;
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struct clk *dss_dphy0_ref_clk;
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struct clk *dss_dphy1_ref_clk;
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struct clk *dss_dphy0_cfg_clk;
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struct clk *dss_dphy1_cfg_clk;
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struct clk *dss_pclk_dsi0_clk;
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struct clk *dss_pclk_dsi1_clk;
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};
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struct mipi_panel_info {
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u8 dsi_version;
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u8 vc;
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u8 lane_nums;
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u8 lane_nums_select_support;
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u8 color_mode;
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u32 dsi_bit_clk; /* clock lane(p/n) */
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u32 burst_mode;
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u32 max_tx_esc_clk;
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u8 non_continue_en;
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u32 dsi_bit_clk_val1;
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u32 dsi_bit_clk_val2;
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u32 dsi_bit_clk_val3;
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u32 dsi_bit_clk_val4;
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u32 dsi_bit_clk_val5;
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u32 dsi_bit_clk_upt;
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/*uint32_t dsi_pclk_rate;*/
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u32 hs_wr_to_time;
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/* dphy config parameter adjust*/
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u32 clk_post_adjust;
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u32 clk_pre_adjust;
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u32 clk_pre_delay_adjust;
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u32 clk_t_hs_exit_adjust;
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u32 clk_t_hs_trial_adjust;
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u32 clk_t_hs_prepare_adjust;
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int clk_t_lpx_adjust;
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u32 clk_t_hs_zero_adjust;
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u32 data_post_delay_adjust;
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int data_t_lpx_adjust;
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u32 data_t_hs_prepare_adjust;
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u32 data_t_hs_zero_adjust;
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u32 data_t_hs_trial_adjust;
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u32 rg_vrefsel_vcm_adjust;
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/*only for Chicago<3660> use*/
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u32 rg_vrefsel_vcm_clk_adjust;
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u32 rg_vrefsel_vcm_data_adjust;
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};
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struct mipi_phy_params {
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u32 clk_t_lpx;
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u32 clk_t_hs_prepare;
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u32 clk_t_hs_zero;
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u32 clk_t_hs_trial;
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u32 clk_t_wakeup;
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u32 data_t_lpx;
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u32 data_t_hs_prepare;
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u32 data_t_hs_zero;
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u32 data_t_hs_trial;
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u32 data_t_ta_go;
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u32 data_t_ta_get;
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u32 data_t_wakeup;
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u32 hstx_ckg_sel;
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u32 pll_fbd_div5f;
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u32 pll_fbd_div1f;
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u32 pll_fbd_2p;
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u32 pll_enbwt;
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u32 pll_fbd_p;
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u32 pll_fbd_s;
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u32 pll_pre_div1p;
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u32 pll_pre_p;
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u32 pll_vco_750M;
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u32 pll_lpf_rs;
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u32 pll_lpf_cs;
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u32 clk_division;
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/********for hikey620************/
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u32 clklp2hs_time;
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u32 clkhs2lp_time;
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u32 lp2hs_time;
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u32 hs2lp_time;
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u32 clk_to_data_delay;
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u32 data_to_clk_delay;
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u32 lane_byte_clk_kHz;
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/*****************/
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/****for hikey960*****/
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u64 lane_byte_clk;
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u32 clk_lane_lp2hs_time;
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u32 clk_lane_hs2lp_time;
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u32 data_lane_lp2hs_time;
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u32 data_lane_hs2lp_time;
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u32 clk2data_delay;
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u32 data2clk_delay;
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u32 clk_pre_delay;
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u32 clk_post_delay;
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u32 data_pre_delay;
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u32 data_post_delay;
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u32 phy_stop_wait_time;
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u32 rg_vrefsel_vcm;
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u32 rg_pll_enswc;
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u32 rg_pll_chp;
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u32 pll_register_override; /*0x1E[0]*/
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u32 pll_power_down; /*0x1E[1]*/
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u32 rg_band_sel; /*0x1E[2]*/
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u32 rg_phase_gen_en; /*0x1E[3]*/
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u32 reload_sel; /*0x1E[4]*/
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u32 rg_pll_cp_p; /*0x1E[7:5]*/
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u32 rg_pll_refsel; /*0x16[1:0]*/
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u32 rg_pll_cp; /*0x16[7:5]*/
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u32 load_command;
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/*********/
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};
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struct ldi_panel_info {
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u32 h_back_porch;
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u32 h_front_porch;
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u32 h_pulse_width;
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/*
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* note: vbp > 8 if used overlay compose,
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* also lcd vbp > 8 in lcd power on sequence
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*/
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u32 v_back_porch;
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u32 v_front_porch;
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u32 v_pulse_width;
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u8 hsync_plr;
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u8 vsync_plr;
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u8 pixelclk_plr;
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u8 data_en_plr;
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/* for cabc */
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u8 dpi0_overlap_size;
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u8 dpi1_overlap_size;
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};
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struct dw_dsi_client {
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u32 lanes;
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u32 phy_clock; /* in kHz */
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enum mipi_dsi_pixel_format format;
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unsigned long mode_flags;
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};
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struct dw_dsi {
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struct drm_encoder encoder;
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struct drm_bridge *bridge;
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struct drm_panel *panel;
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struct mipi_dsi_host host;
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struct drm_connector connector; /* connector for panel */
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struct drm_display_mode cur_mode;
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struct dsi_hw_ctx *ctx;
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struct mipi_phy_params phy;
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struct mipi_panel_info mipi;
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struct ldi_panel_info ldi;
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u32 lanes;
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enum mipi_dsi_pixel_format format;
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unsigned long mode_flags;
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struct gpio_desc *gpio_mux;
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struct dw_dsi_client client[OUT_MAX];
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enum dsi_output_client cur_client;
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bool enable;
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};
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struct dsi_data {
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struct dw_dsi dsi;
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struct dsi_hw_ctx ctx;
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};
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enum kirin_dsi_version {
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KIRIN620_DSI = 0,
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KIRIN960_DSI
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};
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/* display controller init/cleanup ops */
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struct kirin_dsi_ops {
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enum kirin_dsi_version version;
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int (*parse_dt)(struct platform_device *pdev, struct dw_dsi *dsi);
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int (*host_init)(struct device *dev, struct dw_dsi *dsi);
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void (*encoder_enable)(struct drm_encoder *encoder);
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enum drm_mode_status (*encoder_valid)(
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struct drm_encoder *encoder,
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const struct drm_display_mode *mode);
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};
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#ifdef CONFIG_DRM_HISI_KIRIN960
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extern const struct kirin_dsi_ops kirin_dsi_960;
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#endif
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#ifdef CONFIG_DRM_HISI_KIRIN620
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extern const struct kirin_dsi_ops kirin_dsi_620;
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#endif
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#endif /* __KIRIN_DRM_DSI_H__ */
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