/* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright (c) 2016 Linaro Limited.
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* Copyright (c) 2014-2016 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __KIRIN_DPE_REG_H__
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#define __KIRIN_DPE_REG_H__
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#define BIT_MMU_IRPT_NS BIT(28)
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#define BIT_ITF0_INTS BIT(16)
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#define BIT_DPP_INTS BIT(15)
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#define BIT_VACTIVE0_END BIT(8)
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#define BIT_VACTIVE0_START BIT(7)
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#define BIT_VSYNC BIT(4)
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#define BIT_LDI_UNFLOW BIT(2)
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#define DFS_TIME (80)
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#define DFS_TIME_MIN (50)
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#define DFS_TIME_MIN_4K (10)
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#define DBUF0_DEPTH (1408)
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#define DBUF_WIDTH_BIT (144)
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#define PERRSTDIS3 (0x088)
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#define DPE_GLB0_OFFSET (0x12000)
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#define DPE_DBG_OFFSET (0x11000)
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#define DPE_CMDLIST_OFFSET (0x02000)
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#define DPE_SMMU_OFFSET (0x08000)
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#define DPE_MIF_OFFSET (0x0A000)
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#define DPE_MCTRL_SYS_OFFSET (0x10000)
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#define DPE_MCTRL_CTL0_OFFSET (0x10800)
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#define DPE_RCH_VG0_DMA_OFFSET (0x20000)
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#define DPE_RCH_VG0_SCL_OFFSET (0x20200)
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#define DPE_RCH_VG0_ARSR_OFFSET (0x20300)
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#define DPE_RCH_VG1_DMA_OFFSET (0x28000)
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#define DPE_RCH_VG1_SCL_OFFSET (0x28200)
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#define DPE_RCH_VG2_DMA_OFFSET (0x30000)
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#define DPE_RCH_VG2_SCL_OFFSET (0x30200)
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#define DPE_RCH_G0_DMA_OFFSET (0x38000)
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#define DPE_RCH_G0_SCL_OFFSET (0x38200)
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#define DPE_RCH_G1_DMA_OFFSET (0x40000)
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#define DPE_RCH_G1_SCL_OFFSET (0x40200)
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#define DPE_RCH_D2_DMA_OFFSET (0x50000)
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#define DPE_RCH_D3_DMA_OFFSET (0x51000)
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#define DPE_RCH_D0_DMA_OFFSET (0x52000)
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#define DPE_RCH_D0_DFC_OFFSET (0x52100)
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#define DPE_RCH_D1_DMA_OFFSET (0x53000)
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#define DPE_WCH0_DMA_OFFSET (0x5A000)
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#define DPE_WCH1_DMA_OFFSET (0x5C000)
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#define DPE_WCH2_DMA_OFFSET (0x5E000)
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#define DPE_WCH2_DFC_OFFSET (0x5E100)
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#define DPE_OVL0_OFFSET (0x60000)
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#define DPE_DBUF0_OFFSET (0x6D000)
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#define DPE_DPP_OFFSET (0x70000)
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#define DPE_DPP_DITHER_OFFSET (0x70200)
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#define DPE_LDI0_OFFSET (0x7D000)
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#define DPE_IFBC_OFFSET (0x7D800)
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#define DPE_DSC_OFFSET (0x7DC00)
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#define GLB_CPU_PDP_INTS (DPE_GLB0_OFFSET + 0x224)
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#define GLB_CPU_PDP_INT_MSK (DPE_GLB0_OFFSET + 0x228)
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#define GLB_CPU_SDP_INTS (DPE_GLB0_OFFSET + 0x22C)
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#define GLB_CPU_SDP_INT_MSK (DPE_GLB0_OFFSET + 0x230)
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#define DBG_MCTL_INTS (0x023C)
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#define DBG_MCTL_INT_MSK (0x0240)
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#define DBG_WCH0_INTS (0x0244)
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#define DBG_WCH0_INT_MSK (0x0248)
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#define DBG_WCH1_INTS (0x024C)
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#define DBG_WCH1_INT_MSK (0x0250)
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#define DBG_RCH0_INTS (0x0254)
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#define DBG_RCH0_INT_MSK (0x0258)
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#define DBG_RCH1_INTS (0x025C)
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#define DBG_RCH1_INT_MSK (0x0260)
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#define DBG_RCH2_INTS (0x0264)
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#define DBG_RCH2_INT_MSK (0x0268)
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#define DBG_RCH3_INTS (0x026C)
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#define DBG_RCH3_INT_MSK (0x0270)
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#define DBG_RCH4_INTS (0x0274)
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#define DBG_RCH4_INT_MSK (0x0278)
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#define DBG_RCH5_INTS (0x027C)
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#define DBG_RCH5_INT_MSK (0x0280)
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#define DBG_RCH6_INTS (0x0284)
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#define DBG_RCH6_INT_MSK (0x0288)
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#define DBG_RCH7_INTS (0x028C)
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#define DBG_RCH7_INT_MSK (0x0290)
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#define DBG_DPE_GLB_INTS (0x0294)
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#define DBG_DPE_GLB_INT_MSK (0x0298)
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#define AIF0_CH0_OFFSET (0x7000)
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#define AIF0_CH0_ADD_OFFSET (0x7004)
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#define MIF_ENABLE (0x0000)
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#define MIF_MEM_CTRL (0x0004)
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#define MIF_CTRL0 (0x0000)
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#define MIF_CTRL1 (0x0004)
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#define MIF_CTRL2 (0x0008)
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#define MIF_CTRL3 (0x000C)
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#define MIF_CTRL4 (0x0010)
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#define MIF_CTRL5 (0x0014)
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#define MIF_CTRL_OFFSET (0x0020)
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#define MIF_CH0_OFFSET (DPE_MIF_OFFSET + MIF_CTRL_OFFSET * 1)
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#define SMMU_SCR (0x0000)
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#define SMMU_MEMCTRL (0x0004)
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#define SMMU_LP_CTRL (0x0008)
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#define SMMU_INTMASK_NS (0x0010)
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#define SMMU_INTRAW_NS (0x0014)
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#define SMMU_INTSTAT_NS (0x0018)
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#define SMMU_INTCLR_NS (0x001C)
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#define SMMU_SMRx_NS (0x0020)
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#define DMA_OFT_X0 (0x0000)
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#define DMA_OFT_Y0 (0x0004)
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#define DMA_OFT_X1 (0x0008)
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#define DMA_OFT_Y1 (0x000C)
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#define DMA_MASK0 (0x0010)
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#define DMA_MASK1 (0x0014)
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#define DMA_STRETCH_SIZE_VRT (0x0018)
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#define DMA_CTRL (0x001C)
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#define DMA_TILE_SCRAM (0x0020)
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#define DMA_PULSE (0x0028)
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#define DMA_CORE_GT (0x002C)
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#define DMA_DATA_ADDR0 (0x0060)
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#define DMA_STRIDE0 (0x0064)
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#define DMA_STRETCH_STRIDE0 (0x0068)
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#define DMA_DATA_NUM0 (0x006C)
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#define DMA_CH_CTL (0x00D4)
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#define DMA_CH_REG_DEFAULT (0x0A00)
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#define DMA_ALIGN_BYTES (128 / BITS_PER_BYTE)
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#define DMA_ADDR_ALIGN (128 / BITS_PER_BYTE)
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#define DMA_STRIDE_ALIGN (128 / BITS_PER_BYTE)
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#define DFC_DISP_SIZE (0x0000)
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#define DFC_PIX_IN_NUM (0x0004)
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#define DFC_GLB_ALPHA (0x0008)
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#define DFC_DISP_FMT (0x000C)
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#define DFC_CLIP_CTL_HRZ (0x0010)
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#define DFC_CLIP_CTL_VRZ (0x0014)
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#define DFC_CTL_CLIP_EN (0x0018)
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#define DFC_ICG_MODULE (0x001C)
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#define DFC_DITHER_ENABLE (0x0020)
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#define DFC_PADDING_CTL (0x0024)
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#define MCTL_CTL_EN (0x0000)
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#define MCTL_CTL_MUTEX (0x0004)
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#define MCTL_CTL_MUTEX_STATUS (0x0008)
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#define MCTL_CTL_MUTEX_ITF (0x000C)
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#define MCTL_CTL_MUTEX_DBUF (0x0010)
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#define MCTL_CTL_MUTEX_SCF (0x0014)
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#define MCTL_CTL_MUTEX_OV (0x0018)
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#define MCTL_CTL_MUTEX_WCH0 (0x0020)
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#define MCTL_CTL_MUTEX_RCH0 (0x0030)
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#define MCTL_CTL_TOP (0x0050)
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#define MCTL_CTL_DBG (0x00E0)
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#define MCTL_RCH0_FLUSH_EN (0x0100)
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#define MCTL_OV0_FLUSH_EN (0x0128)
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#define MCTL_RCH0_OV_OEN (0x0160)
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#define MCTL_RCH_OV0_SEL (0x0180)
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#define OVL_SIZE (0x0000)
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#define OVL_BG_COLOR (0x0004)
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#define OVL_DST_STARTPOS (0x0008)
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#define OVL_DST_ENDPOS (0x000C)
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#define OVL_GCFG (0x0010)
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#define OVL_LAYER0_POS (0x0014)
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#define OVL_LAYER0_SIZE (0x0018)
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#define OVL_LAYER0_ALPHA (0x0030)
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#define OVL_LAYER0_CFG (0x0034)
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#define OVL6_REG_DEFAULT (0x01A8)
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#define DBUF_FRM_SIZE (0x0000)
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#define DBUF_FRM_HSIZE (0x0004)
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#define DBUF_SRAM_VALID_NUM (0x0008)
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#define DBUF_WBE_EN (0x000C)
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#define DBUF_THD_FILL_LEV0 (0x0010)
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#define DBUF_DFS_FILL_LEV1 (0x0014)
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#define DBUF_THD_RQOS (0x0018)
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#define DBUF_THD_WQOS (0x001C)
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#define DBUF_THD_CG (0x0020)
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#define DBUF_THD_OTHER (0x0024)
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#define DBUF_ONLINE_FILL_LEVEL (0x003C)
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#define DBUF_WB_FILL_LEVEL (0x0040)
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#define DBUF_DFS_STATUS (0x0044)
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#define DBUF_THD_FLUX_REQ_BEF (0x0048)
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#define DBUF_DFS_LP_CTRL (0x004C)
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#define DBUF_RD_SHADOW_SEL (0x0050)
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#define DBUF_MEM_CTRL (0x0054)
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#define DBUF_THD_FLUX_REQ_AFT (0x0064)
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#define DBUF_THD_DFS_OK (0x0068)
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#define DBUF_FLUX_REQ_CTRL (0x006C)
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#define DBUF_REG_DEFAULT (0x00A4)
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#define DPP_IMG_SIZE_BEF_SR (0x000C)
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#define DPP_IMG_SIZE_AFT_SR (0x0010)
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#define DPP_INTS (0x0040)
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#define DPP_INT_MSK (0x0044)
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#define SCF_COEF_MEM_CTRL (0x0018)
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#define IFBC_MEM_CTRL (0x001C)
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#define DITHER_MEM_CTRL (0x002C)
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#define DSC_MEM_CTRL (0x0084)
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#define ARSR2P_LB_MEM_CTRL (0x0084)
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#define SCF_LB_MEM_CTRL (0x0090)
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#define ROT_MEM_CTRL (0x0538)
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#define VPP_MEM_CTRL (0x0704)
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#define CMD_MEM_CTRL (0x073C)
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#define DMA_BUF_MEM_CTRL (0x0854)
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#define AFBCD_MEM_CTRL (0x093C)
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#define AFBCE_MEM_CTRL (0x0924)
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#define LDI_DPI0_HRZ_CTRL0 (0x0000)
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#define LDI_DPI0_HRZ_CTRL1 (0x0004)
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#define LDI_DPI0_HRZ_CTRL2 (0x0008)
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#define LDI_VRT_CTRL0 (0x000C)
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#define LDI_VRT_CTRL1 (0x0010)
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#define LDI_VRT_CTRL2 (0x0014)
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#define LDI_PLR_CTRL (0x0018)
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#define LDI_CTRL (0x0024)
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#define LDI_WORK_MODE (0x0028)
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#define LDI_DSI_CMD_MOD_CTRL (0x0030)
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#define LDI_VINACT_MSK_LEN (0x0050)
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#define LDI_CMD_EVENT_SEL (0x0060)
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#define LDI_MEM_CTRL (0x0100)
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#define LDI_PXL0_DIV2_GT_EN (0x0210)
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#define LDI_PXL0_DIV4_GT_EN (0x0214)
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#define LDI_PXL0_GT_EN (0x0218)
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#define LDI_PXL0_DSI_GT_EN (0x021C)
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#define LDI_PXL0_DIVXCFG (0x0220)
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#define LDI_VESA_CLK_SEL (0x0228)
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#define LDI_CPU_ITF_INTS (0x0248)
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#define LDI_CPU_ITF_INT_MSK (0x024C)
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#define MIPIDSI_VERSION_OFFSET (0x0000)
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#define MIPIDSI_PWR_UP_OFFSET (0x0004)
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#define MIPIDSI_CLKMGR_CFG_OFFSET (0x0008)
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#define MIPIDSI_DPI_VCID_OFFSET (0x000c)
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#define MIPIDSI_DPI_COLOR_CODING_OFFSET (0x0010)
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#define MIPIDSI_DPI_CFG_POL_OFFSET (0x0014)
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#define MIPIDSI_DPI_LP_CMD_TIM_OFFSET (0x0018)
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#define MIPIDSI_PCKHDL_CFG_OFFSET (0x002c)
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#define MIPIDSI_GEN_VCID_OFFSET (0x0030)
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#define MIPIDSI_MODE_CFG_OFFSET (0x0034)
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#define MIPIDSI_VID_MODE_CFG_OFFSET (0x0038)
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#define MIPIDSI_VID_PKT_SIZE_OFFSET (0x003c)
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#define MIPIDSI_VID_NUM_CHUNKS_OFFSET (0x0040)
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#define MIPIDSI_VID_NULL_SIZE_OFFSET (0x0044)
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#define MIPIDSI_VID_HSA_TIME_OFFSET (0x0048)
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#define MIPIDSI_VID_HBP_TIME_OFFSET (0x004c)
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#define MIPIDSI_VID_HLINE_TIME_OFFSET (0x0050)
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#define MIPIDSI_VID_VSA_LINES_OFFSET (0x0054)
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#define MIPIDSI_VID_VBP_LINES_OFFSET (0x0058)
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#define MIPIDSI_VID_VFP_LINES_OFFSET (0x005c)
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#define MIPIDSI_VID_VACTIVE_LINES_OFFSET (0x0060)
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#define MIPIDSI_EDPI_CMD_SIZE_OFFSET (0x0064)
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#define MIPIDSI_CMD_MODE_CFG_OFFSET (0x0068)
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#define MIPIDSI_GEN_HDR_OFFSET (0x006c)
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#define MIPIDSI_GEN_PLD_DATA_OFFSET (0x0070)
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#define MIPIDSI_CMD_PKT_STATUS_OFFSET (0x0074)
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#define MIPIDSI_TO_CNT_CFG_OFFSET (0x0078)
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#define MIPIDSI_BTA_TO_CNT_OFFSET (0x008C)
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#define MIPIDSI_SDF_3D_OFFSET (0x0090)
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#define MIPIDSI_LPCLK_CTRL_OFFSET (0x0094)
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#define MIPIDSI_PHY_TMR_LPCLK_CFG_OFFSET (0x0098)
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#define MIPIDSI_PHY_TMR_CFG_OFFSET (0x009c)
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#define MIPIDSI_PHY_RSTZ_OFFSET (0x00a0)
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#define MIPIDSI_PHY_IF_CFG_OFFSET (0x00a4)
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#define MIPIDSI_PHY_ULPS_CTRL_OFFSET (0x00a8)
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#define MIPIDSI_PHY_TX_TRIGGERS_OFFSET (0x00ac)
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#define MIPIDSI_PHY_STATUS_OFFSET (0x00b0)
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#define MIPIDSI_PHY_TST_CTRL0_OFFSET (0x00b4)
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#define MIPIDSI_PHY_TST_CTRL1_OFFSET (0x00b8)
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#define MIPIDSI_PHY_TMR_RD_CFG_OFFSET (0x00f4)
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enum XRES_DIV {
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XRES_DIV_1 = 1,
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XRES_DIV_2,
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};
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enum YRES_DIV {
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YRES_DIV_1 = 1,
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YRES_DIV_2,
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};
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enum PXL0_DIVCFG {
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PXL0_DIVCFG_0 = 0,
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PXL0_DIVCFG_1,
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};
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enum PXL0_DIV2_GT_EN {
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PXL0_DIV2_GT_EN_CLOSE = 0,
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PXL0_DIV2_GT_EN_OPEN,
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};
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enum PXL0_DIV4_GT_EN {
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PXL0_DIV4_GT_EN_CLOSE = 0,
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PXL0_DIV4_GT_EN_OPEN,
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};
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enum PXL0_DSI_GT_EN {
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PXL0_DSI_GT_EN_0 = 0,
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PXL0_DSI_GT_EN_1,
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};
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enum lcd_format {
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LCD_RGB888 = 0,
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LCD_RGB101010,
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LCD_RGB565,
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};
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enum lcd_rgb_order {
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LCD_RGB = 0,
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LCD_BGR,
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};
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enum dpe_dfc_format {
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DFC_PIXEL_FORMAT_RGB_565 = 0,
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DFC_PIXEL_FORMAT_XRGB_4444,
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DFC_PIXEL_FORMAT_ARGB_4444,
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DFC_PIXEL_FORMAT_XRGB_5551,
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DFC_PIXEL_FORMAT_ARGB_5551,
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DFC_PIXEL_FORMAT_XRGB_8888,
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DFC_PIXEL_FORMAT_ARGB_8888,
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DFC_PIXEL_FORMAT_BGR_565,
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DFC_PIXEL_FORMAT_XBGR_4444,
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DFC_PIXEL_FORMAT_ABGR_4444,
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DFC_PIXEL_FORMAT_XBGR_5551,
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DFC_PIXEL_FORMAT_ABGR_5551,
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DFC_PIXEL_FORMAT_XBGR_8888,
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DFC_PIXEL_FORMAT_ABGR_8888,
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DFC_PIXEL_FORMAT_YUV444,
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DFC_PIXEL_FORMAT_YVU444,
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DFC_PIXEL_FORMAT_YUYV422,
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DFC_PIXEL_FORMAT_YVYU422,
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DFC_PIXEL_FORMAT_VYUY422,
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DFC_PIXEL_FORMAT_UYVY422,
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};
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enum dpe_dma_format {
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DMA_PIXEL_FORMAT_RGB_565 = 0,
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DMA_PIXEL_FORMAT_ARGB_4444,
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DMA_PIXEL_FORMAT_XRGB_4444,
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DMA_PIXEL_FORMAT_ARGB_5551,
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DMA_PIXEL_FORMAT_XRGB_5551,
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DMA_PIXEL_FORMAT_ARGB_8888,
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DMA_PIXEL_FORMAT_XRGB_8888,
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DMA_PIXEL_FORMAT_RESERVED0,
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DMA_PIXEL_FORMAT_YUYV_422_Pkg,
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DMA_PIXEL_FORMAT_YUV_420_SP_HP,
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DMA_PIXEL_FORMAT_YUV_420_P_HP,
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DMA_PIXEL_FORMAT_YUV_422_SP_HP,
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DMA_PIXEL_FORMAT_YUV_422_P_HP,
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DMA_PIXEL_FORMAT_AYUV_4444,
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};
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enum dpe_fb_format {
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DPE_RGB_565 = 0,
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DPE_RGBX_4444,
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DPE_RGBA_4444,
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DPE_RGBX_5551,
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DPE_RGBA_5551,
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DPE_RGBX_8888,
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DPE_RGBA_8888,
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DPE_BGR_565,
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DPE_BGRX_4444,
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DPE_BGRA_4444,
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DPE_BGRX_5551,
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DPE_BGRA_5551,
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DPE_BGRX_8888,
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DPE_BGRA_8888,
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DPE_YUV_422_I,
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/* YUV Semi-planar */
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DPE_YCbCr_422_SP,
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DPE_YCrCb_422_SP,
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DPE_YCbCr_420_SP,
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DPE_YCrCb_420_SP,
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/* YUV Planar */
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DPE_YCbCr_422_P,
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DPE_YCrCb_422_P,
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DPE_YCbCr_420_P,
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DPE_YCrCb_420_P,
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/* YUV Package */
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DPE_YUYV_422_Pkg,
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DPE_UYVY_422_Pkg,
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DPE_YVYU_422_Pkg,
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DPE_VYUY_422_Pkg,
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};
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#endif
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