/*
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* arch/ppc/5xxx_io/fec.h
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*
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* Header file for the MPC5xxx Fast Ethernet Controller driver
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*
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* Author: Dale Farnsworth <dfarnsworth@mvista.com>
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*
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* Copyright 2003 MontaVista Software
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*
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* 2003 (c) MontaVista, Software, Inc. This file is licensed under the terms
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* of the GNU General Public License version 2. This program is licensed
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* "as is" without any warranty of any kind, whether express or implied.
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*/
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#ifndef __RT_MPC52XX_FEC_H_
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#define __RT_MPC52XX_FEC_H_
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/mii.h>
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#include <linux/skbuff.h>
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#include <asm/mpc5xxx.h>
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#include <bestcomm_api.h>
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/* Define board specific options */
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#define CONFIG_XENO_DRIVERS_NET_USE_MDIO
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#define CONFIG_XENO_DRIVERS_NET_FEC_GENERIC_PHY
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#define CONFIG_XENO_DRIVERS_NET_FEC_LXT971
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#undef CONFIG_XENO_DRIVERS_NET_FEC_DP83847
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/* Tunable constants */
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#define MPC5xxx_FEC_RECV_BUFFER_SIZE 1518 /* max receive packet size */
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#define MPC5xxx_FEC_RECV_BUFFER_SIZE_BC 2048 /* max receive packet size */
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#define MPC5xxx_FEC_TBD_NUM 256 /* max transmit packets */
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#define MPC5xxx_FEC_RBD_NUM 256 /* max receive packets */
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struct mpc5xxx_fec {
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volatile u32 fec_id; /* FEC + 0x000 */
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volatile u32 ievent; /* FEC + 0x004 */
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volatile u32 imask; /* FEC + 0x008 */
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volatile u32 reserved0[1]; /* FEC + 0x00C */
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volatile u32 r_des_active; /* FEC + 0x010 */
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volatile u32 x_des_active; /* FEC + 0x014 */
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volatile u32 r_des_active_cl; /* FEC + 0x018 */
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volatile u32 x_des_active_cl; /* FEC + 0x01C */
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volatile u32 ivent_set; /* FEC + 0x020 */
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volatile u32 ecntrl; /* FEC + 0x024 */
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volatile u32 reserved1[6]; /* FEC + 0x028-03C */
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volatile u32 mii_data; /* FEC + 0x040 */
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volatile u32 mii_speed; /* FEC + 0x044 */
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volatile u32 mii_status; /* FEC + 0x048 */
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volatile u32 reserved2[5]; /* FEC + 0x04C-05C */
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volatile u32 mib_data; /* FEC + 0x060 */
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volatile u32 mib_control; /* FEC + 0x064 */
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volatile u32 reserved3[6]; /* FEC + 0x068-7C */
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volatile u32 r_activate; /* FEC + 0x080 */
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volatile u32 r_cntrl; /* FEC + 0x084 */
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volatile u32 r_hash; /* FEC + 0x088 */
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volatile u32 r_data; /* FEC + 0x08C */
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volatile u32 ar_done; /* FEC + 0x090 */
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volatile u32 r_test; /* FEC + 0x094 */
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volatile u32 r_mib; /* FEC + 0x098 */
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volatile u32 r_da_low; /* FEC + 0x09C */
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volatile u32 r_da_high; /* FEC + 0x0A0 */
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volatile u32 reserved4[7]; /* FEC + 0x0A4-0BC */
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volatile u32 x_activate; /* FEC + 0x0C0 */
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volatile u32 x_cntrl; /* FEC + 0x0C4 */
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volatile u32 backoff; /* FEC + 0x0C8 */
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volatile u32 x_data; /* FEC + 0x0CC */
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volatile u32 x_status; /* FEC + 0x0D0 */
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volatile u32 x_mib; /* FEC + 0x0D4 */
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volatile u32 x_test; /* FEC + 0x0D8 */
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volatile u32 fdxfc_da1; /* FEC + 0x0DC */
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volatile u32 fdxfc_da2; /* FEC + 0x0E0 */
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volatile u32 paddr1; /* FEC + 0x0E4 */
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volatile u32 paddr2; /* FEC + 0x0E8 */
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volatile u32 op_pause; /* FEC + 0x0EC */
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volatile u32 reserved5[4]; /* FEC + 0x0F0-0FC */
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volatile u32 instr_reg; /* FEC + 0x100 */
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volatile u32 context_reg; /* FEC + 0x104 */
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volatile u32 test_cntrl; /* FEC + 0x108 */
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volatile u32 acc_reg; /* FEC + 0x10C */
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volatile u32 ones; /* FEC + 0x110 */
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volatile u32 zeros; /* FEC + 0x114 */
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volatile u32 iaddr1; /* FEC + 0x118 */
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volatile u32 iaddr2; /* FEC + 0x11C */
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volatile u32 gaddr1; /* FEC + 0x120 */
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volatile u32 gaddr2; /* FEC + 0x124 */
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volatile u32 random; /* FEC + 0x128 */
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volatile u32 rand1; /* FEC + 0x12C */
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volatile u32 tmp; /* FEC + 0x130 */
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volatile u32 reserved6[3]; /* FEC + 0x134-13C */
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volatile u32 fifo_id; /* FEC + 0x140 */
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volatile u32 x_wmrk; /* FEC + 0x144 */
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volatile u32 fcntrl; /* FEC + 0x148 */
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volatile u32 r_bound; /* FEC + 0x14C */
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volatile u32 r_fstart; /* FEC + 0x150 */
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volatile u32 r_count; /* FEC + 0x154 */
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volatile u32 r_lag; /* FEC + 0x158 */
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volatile u32 r_read; /* FEC + 0x15C */
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volatile u32 r_write; /* FEC + 0x160 */
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volatile u32 x_count; /* FEC + 0x164 */
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volatile u32 x_lag; /* FEC + 0x168 */
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volatile u32 x_retry; /* FEC + 0x16C */
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volatile u32 x_write; /* FEC + 0x170 */
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volatile u32 x_read; /* FEC + 0x174 */
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volatile u32 reserved7[2]; /* FEC + 0x178-17C */
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volatile u32 fm_cntrl; /* FEC + 0x180 */
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volatile u32 rfifo_data; /* FEC + 0x184 */
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volatile u32 rfifo_status; /* FEC + 0x188 */
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volatile u32 rfifo_cntrl; /* FEC + 0x18C */
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volatile u32 rfifo_lrf_ptr; /* FEC + 0x190 */
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volatile u32 rfifo_lwf_ptr; /* FEC + 0x194 */
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volatile u32 rfifo_alarm; /* FEC + 0x198 */
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volatile u32 rfifo_rdptr; /* FEC + 0x19C */
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volatile u32 rfifo_wrptr; /* FEC + 0x1A0 */
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volatile u32 tfifo_data; /* FEC + 0x1A4 */
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volatile u32 tfifo_status; /* FEC + 0x1A8 */
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volatile u32 tfifo_cntrl; /* FEC + 0x1AC */
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volatile u32 tfifo_lrf_ptr; /* FEC + 0x1B0 */
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volatile u32 tfifo_lwf_ptr; /* FEC + 0x1B4 */
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volatile u32 tfifo_alarm; /* FEC + 0x1B8 */
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volatile u32 tfifo_rdptr; /* FEC + 0x1BC */
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volatile u32 tfifo_wrptr; /* FEC + 0x1C0 */
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volatile u32 reset_cntrl; /* FEC + 0x1C4 */
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volatile u32 xmit_fsm; /* FEC + 0x1C8 */
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volatile u32 reserved8[3]; /* FEC + 0x1CC-1D4 */
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volatile u32 rdes_data0; /* FEC + 0x1D8 */
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volatile u32 rdes_data1; /* FEC + 0x1DC */
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volatile u32 r_length; /* FEC + 0x1E0 */
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volatile u32 x_length; /* FEC + 0x1E4 */
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volatile u32 x_addr; /* FEC + 0x1E8 */
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volatile u32 cdes_data; /* FEC + 0x1EC */
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volatile u32 status; /* FEC + 0x1F0 */
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volatile u32 dma_control; /* FEC + 0x1F4 */
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volatile u32 des_cmnd; /* FEC + 0x1F8 */
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volatile u32 data; /* FEC + 0x1FC */
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volatile u32 rmon_t_drop; /* FEC + 0x200 */
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volatile u32 rmon_t_packets; /* FEC + 0x204 */
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volatile u32 rmon_t_bc_pkt; /* FEC + 0x208 */
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volatile u32 rmon_t_mc_pkt; /* FEC + 0x20C */
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volatile u32 rmon_t_crc_align; /* FEC + 0x210 */
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volatile u32 rmon_t_undersize; /* FEC + 0x214 */
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volatile u32 rmon_t_oversize; /* FEC + 0x218 */
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volatile u32 rmon_t_frag; /* FEC + 0x21C */
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volatile u32 rmon_t_jab; /* FEC + 0x220 */
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volatile u32 rmon_t_col; /* FEC + 0x224 */
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volatile u32 rmon_t_p64; /* FEC + 0x228 */
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volatile u32 rmon_t_p65to127; /* FEC + 0x22C */
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volatile u32 rmon_t_p128to255; /* FEC + 0x230 */
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volatile u32 rmon_t_p256to511; /* FEC + 0x234 */
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volatile u32 rmon_t_p512to1023; /* FEC + 0x238 */
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volatile u32 rmon_t_p1024to2047; /* FEC + 0x23C */
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volatile u32 rmon_t_p_gte2048; /* FEC + 0x240 */
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volatile u32 rmon_t_octets; /* FEC + 0x244 */
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volatile u32 ieee_t_drop; /* FEC + 0x248 */
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volatile u32 ieee_t_frame_ok; /* FEC + 0x24C */
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volatile u32 ieee_t_1col; /* FEC + 0x250 */
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volatile u32 ieee_t_mcol; /* FEC + 0x254 */
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volatile u32 ieee_t_def; /* FEC + 0x258 */
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volatile u32 ieee_t_lcol; /* FEC + 0x25C */
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volatile u32 ieee_t_excol; /* FEC + 0x260 */
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volatile u32 ieee_t_macerr; /* FEC + 0x264 */
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volatile u32 ieee_t_cserr; /* FEC + 0x268 */
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volatile u32 ieee_t_sqe; /* FEC + 0x26C */
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volatile u32 t_fdxfc; /* FEC + 0x270 */
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volatile u32 ieee_t_octets_ok; /* FEC + 0x274 */
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volatile u32 reserved9[2]; /* FEC + 0x278-27C */
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volatile u32 rmon_r_drop; /* FEC + 0x280 */
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volatile u32 rmon_r_packets; /* FEC + 0x284 */
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volatile u32 rmon_r_bc_pkt; /* FEC + 0x288 */
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volatile u32 rmon_r_mc_pkt; /* FEC + 0x28C */
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volatile u32 rmon_r_crc_align; /* FEC + 0x290 */
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volatile u32 rmon_r_undersize; /* FEC + 0x294 */
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volatile u32 rmon_r_oversize; /* FEC + 0x298 */
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volatile u32 rmon_r_frag; /* FEC + 0x29C */
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volatile u32 rmon_r_jab; /* FEC + 0x2A0 */
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volatile u32 rmon_r_resvd_0; /* FEC + 0x2A4 */
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volatile u32 rmon_r_p64; /* FEC + 0x2A8 */
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volatile u32 rmon_r_p65to127; /* FEC + 0x2AC */
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volatile u32 rmon_r_p128to255; /* FEC + 0x2B0 */
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volatile u32 rmon_r_p256to511; /* FEC + 0x2B4 */
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volatile u32 rmon_r_p512to1023; /* FEC + 0x2B8 */
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volatile u32 rmon_r_p1024to2047; /* FEC + 0x2BC */
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volatile u32 rmon_r_p_gte2048; /* FEC + 0x2C0 */
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volatile u32 rmon_r_octets; /* FEC + 0x2C4 */
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volatile u32 ieee_r_drop; /* FEC + 0x2C8 */
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volatile u32 ieee_r_frame_ok; /* FEC + 0x2CC */
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volatile u32 ieee_r_crc; /* FEC + 0x2D0 */
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volatile u32 ieee_r_align; /* FEC + 0x2D4 */
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volatile u32 r_macerr; /* FEC + 0x2D8 */
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volatile u32 r_fdxfc; /* FEC + 0x2DC */
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volatile u32 ieee_r_octets_ok; /* FEC + 0x2E0 */
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volatile u32 reserved10[6]; /* FEC + 0x2E4-2FC */
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volatile u32 reserved11[64]; /* FEC + 0x300-3FF */
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};
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#define MPC5xxx_FEC_MIB_DISABLE 0x80000000
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#define MPC5xxx_FEC_IEVENT_HBERR 0x80000000
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#define MPC5xxx_FEC_IEVENT_BABR 0x40000000
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#define MPC5xxx_FEC_IEVENT_BABT 0x20000000
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#define MPC5xxx_FEC_IEVENT_GRA 0x10000000
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#define MPC5xxx_FEC_IEVENT_TFINT 0x08000000
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#define MPC5xxx_FEC_IEVENT_MII 0x00800000
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#define MPC5xxx_FEC_IEVENT_LATE_COL 0x00200000
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#define MPC5xxx_FEC_IEVENT_COL_RETRY_LIM 0x00100000
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#define MPC5xxx_FEC_IEVENT_XFIFO_UN 0x00080000
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#define MPC5xxx_FEC_IEVENT_XFIFO_ERROR 0x00040000
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#define MPC5xxx_FEC_IEVENT_RFIFO_ERROR 0x00020000
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#define MPC5xxx_FEC_IMASK_HBERR 0x80000000
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#define MPC5xxx_FEC_IMASK_BABR 0x40000000
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#define MPC5xxx_FEC_IMASK_BABT 0x20000000
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#define MPC5xxx_FEC_IMASK_GRA 0x10000000
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#define MPC5xxx_FEC_IMASK_MII 0x00800000
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#define MPC5xxx_FEC_IMASK_LATE_COL 0x00200000
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#define MPC5xxx_FEC_IMASK_COL_RETRY_LIM 0x00100000
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#define MPC5xxx_FEC_IMASK_XFIFO_UN 0x00080000
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#define MPC5xxx_FEC_IMASK_XFIFO_ERROR 0x00040000
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#define MPC5xxx_FEC_IMASK_RFIFO_ERROR 0x00020000
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#define MPC5xxx_FEC_RCNTRL_MAX_FL_SHIFT 16
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#define MPC5xxx_FEC_RCNTRL_LOOP 0x01
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#define MPC5xxx_FEC_RCNTRL_DRT 0x02
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#define MPC5xxx_FEC_RCNTRL_MII_MODE 0x04
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#define MPC5xxx_FEC_RCNTRL_PROM 0x08
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#define MPC5xxx_FEC_RCNTRL_BC_REJ 0x10
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#define MPC5xxx_FEC_RCNTRL_FCE 0x20
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#define MPC5xxx_FEC_TCNTRL_GTS 0x00000001
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#define MPC5xxx_FEC_TCNTRL_HBC 0x00000002
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#define MPC5xxx_FEC_TCNTRL_FDEN 0x00000004
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#define MPC5xxx_FEC_TCNTRL_TFC_PAUSE 0x00000008
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#define MPC5xxx_FEC_TCNTRL_RFC_PAUSE 0x00000010
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#define MPC5xxx_FEC_ECNTRL_RESET 0x00000001
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#define MPC5xxx_FEC_ECNTRL_ETHER_EN 0x00000002
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#define MPC5xxx_FEC_RESET_DELAY 50 /* uS */
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/* Receive & Transmit Buffer Descriptor definitions */
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struct mpc5xxx_fec_bd {
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volatile u32 status;
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volatile u32 data;
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};
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/* Receive data buffer format */
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struct mpc5xxx_rbuf {
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u8 data[MPC5xxx_FEC_RECV_BUFFER_SIZE_BC];
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};
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struct fec_queue {
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volatile struct mpc5xxx_fec_bd *bd_base;
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struct rtskb **skb_base;
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u16 last_index;
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u16 start_index;
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u16 finish_index;
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};
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#ifdef CONFIG_XENO_DRIVERS_NET_USE_MDIO
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#define MII_ADVERTISE_HALF (ADVERTISE_100HALF | ADVERTISE_10HALF | \
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ADVERTISE_CSMA)
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#define MII_ADVERTISE_ALL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
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MII_ADVERTISE_HALF)
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#ifdef PHY_INTERRUPT
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#define MII_ADVERTISE_DEFAULT MII_ADVERTISE_ALL
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#else
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#define MII_ADVERTISE_DEFAULT MII_ADVERTISE_HALF
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#endif
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typedef struct {
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uint mii_data;
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void (*funct)(uint mii_reg, struct rtnet_device *dev, uint data);
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} phy_cmd_t;
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typedef struct {
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uint id;
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char *name;
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const phy_cmd_t *config;
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const phy_cmd_t *startup;
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const phy_cmd_t *ack_int;
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const phy_cmd_t *shutdown;
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} phy_info_t;
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#endif /* CONFIG_XENO_DRIVERS_NET_USE_MDIO */
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struct mpc5xxx_fec_priv {
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int full_duplex;
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int tx_full;
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int r_tasknum;
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int t_tasknum;
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int r_irq;
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int t_irq;
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rtdm_irq_t irq_handle;
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rtdm_irq_t r_irq_handle;
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rtdm_irq_t t_irq_handle;
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u32 last_transmit_time;
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u32 last_receive_time;
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struct mpc5xxx_fec *fec;
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struct mpc5xxx_sram_fec *sram;
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struct mpc5xxx_gpio *gpio;
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struct mpc5xxx_sdma *sdma;
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struct fec_queue r_queue;
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struct rtskb *rskb[MPC5xxx_FEC_RBD_NUM];
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struct fec_queue t_queue;
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struct rtskb *tskb[MPC5xxx_FEC_TBD_NUM];
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rtdm_lock_t lock;
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unsigned long open_time;
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struct net_device_stats stats;
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#ifdef CONFIG_XENO_DRIVERS_NET_USE_MDIO
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uint phy_id;
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uint phy_id_done;
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uint phy_status;
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uint phy_speed;
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phy_info_t *phy;
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struct tq_struct phy_task;
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volatile uint sequence_done;
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uint link;
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uint phy_addr;
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struct tq_struct link_up_task;
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int duplex_change;
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int link_up;
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struct timer_list phy_timer_list;
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u16 old_status;
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#endif /* CONFIG_XENO_DRIVERS_NET_USE_MDIO */
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};
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struct mpc5xxx_sram_fec {
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volatile struct mpc5xxx_fec_bd tbd[MPC5xxx_FEC_TBD_NUM];
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volatile struct mpc5xxx_fec_bd rbd[MPC5xxx_FEC_RBD_NUM];
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};
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#define MPC5xxx_FEC_RBD_READY 0x40000000
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#define MPC5xxx_FEC_RBD_RFD 0x08000000 /* receive frame done */
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#define MPC5xxx_FEC_RBD_INIT MPC5xxx_FEC_RBD_READY
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#define MPC5xxx_FEC_TBD_READY 0x40000000
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#define MPC5xxx_FEC_TBD_TFD 0x08000000 /* transmit frame done */
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#define MPC5xxx_FEC_TBD_INT 0x04000000 /* Interrupt */
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#define MPC5xxx_FEC_TBD_INIT (MPC5xxx_FEC_TBD_INT | MPC5xxx_FEC_TBD_TFD | \
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MPC5xxx_FEC_TBD_READY)
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/* MII-related definitions */
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#define MPC5xxx_FEC_MII_DATA_ST 0x40000000 /* Start frame */
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#define MPC5xxx_FEC_MII_DATA_OP_RD 0x20000000 /* Perform read */
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#define MPC5xxx_FEC_MII_DATA_OP_WR 0x10000000 /* Perform write */
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#define MPC5xxx_FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address mask */
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#define MPC5xxx_FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register mask */
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#define MPC5xxx_FEC_MII_DATA_TA 0x00020000 /* Turnaround */
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#define MPC5xxx_FEC_MII_DATA_DATAMSK 0x00000fff /* PHY data mask */
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#define MPC5xxx_FEC_MII_DATA_RA_SHIFT 0x12 /* MII reg addr bits */
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#define MPC5xxx_FEC_MII_DATA_PA_SHIFT 0x17 /* MII PHY addr bits */
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#define MPC5xxx_FEC_MII_SPEED (5 * 2)
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const char mpc5xxx_fec_name[] = "eth0";
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struct mibCounters {
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unsigned int byteReceived;
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unsigned int byteSent;
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unsigned int framesReceived;
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unsigned int framesSent;
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unsigned int totalByteReceived;
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unsigned int totalFramesReceived;
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unsigned int broadcastFramesReceived;
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unsigned int multicastFramesReceived;
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unsigned int cRCError;
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unsigned int oversizeFrames;
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unsigned int fragments;
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unsigned int jabber;
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unsigned int collision;
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unsigned int lateCollision;
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unsigned int frames64;
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unsigned int frames65_127;
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unsigned int frames128_255;
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unsigned int frames256_511;
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unsigned int frames512_1023;
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unsigned int frames1024_MaxSize;
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unsigned int macRxError;
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unsigned int droppedFrames;
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unsigned int outMulticastFrames;
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unsigned int outBroadcastFrames;
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unsigned int undersizeFrames;
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};
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#define MPC5xxx_FEC_WATCHDOG_TIMEOUT ((400*HZ)/1000)
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#define MPC5xxx_FEC_FRAME_LAST 0x08000000 /* Last */
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#define MPC5xxx_FEC_FRAME_M 0x01000000 /* M? */
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#define MPC5xxx_FEC_FRAME_BC 0x00800000 /* Broadcast */
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#define MPC5xxx_FEC_FRAME_MC 0x00400000 /* Multicast */
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#define MPC5xxx_FEC_FRAME_LG 0x00200000 /* Length error */
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#define MPC5xxx_FEC_FRAME_NO 0x00100000 /* Non-octet aligned frame error */
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#define MPC5xxx_FEC_FRAME_CR 0x00040000 /* CRC frame error */
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#define MPC5xxx_FEC_FRAME_OV 0x00020000 /* Overrun error */
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#define MPC5xxx_FEC_FRAME_TR 0x00010000 /* Truncated error */
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#endif /* __RT_MPC52XX_FEC_H_ */
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