/*******************************************************************************
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Intel PRO/1000 Linux driver
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Copyright(c) 1999 - 2008 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _E1000_PHY_H_
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#define _E1000_PHY_H_
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typedef enum {
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e1000_ms_hw_default = 0,
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e1000_ms_force_master,
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e1000_ms_force_slave,
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e1000_ms_auto
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} e1000_ms_type;
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typedef enum {
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e1000_smart_speed_default = 0,
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e1000_smart_speed_on,
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e1000_smart_speed_off
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} e1000_smart_speed;
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s32 e1000_check_downshift_generic(struct e1000_hw *hw);
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s32 e1000_check_polarity_m88(struct e1000_hw *hw);
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s32 e1000_check_polarity_igp(struct e1000_hw *hw);
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s32 e1000_check_reset_block_generic(struct e1000_hw *hw);
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s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
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s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
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s32 e1000_copper_link_setup_igp(struct e1000_hw *hw);
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s32 e1000_copper_link_setup_m88(struct e1000_hw *hw);
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s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
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s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
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s32 e1000_get_cable_length_m88(struct e1000_hw *hw);
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s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw);
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s32 e1000_get_cfg_done_generic(struct e1000_hw *hw);
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s32 e1000_get_phy_id(struct e1000_hw *hw);
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s32 e1000_get_phy_info_igp(struct e1000_hw *hw);
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s32 e1000_get_phy_info_m88(struct e1000_hw *hw);
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s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw);
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void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
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s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw);
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s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
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s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
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s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
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s32 e1000_setup_copper_link_generic(struct e1000_hw *hw);
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s32 e1000_wait_autoneg_generic(struct e1000_hw *hw);
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s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
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s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
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s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
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s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
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s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
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u32 usec_interval, bool *success);
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s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
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e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
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void e1000_power_up_phy_copper(struct e1000_hw *hw);
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void e1000_power_down_phy_copper(struct e1000_hw *hw);
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s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
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#define E1000_MAX_PHY_ADDR 4
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/* IGP01E1000 Specific Registers */
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#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
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#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
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#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
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#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
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#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */
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#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */
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#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
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#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
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#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
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#define IGP_PAGE_SHIFT 5
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#define PHY_REG_MASK 0x1F
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#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
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#define IGP01E1000_PHY_POLARITY_MASK 0x0078
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#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
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#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
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#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
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/* Enable flexible speed on link-up */
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#define IGP01E1000_GMII_FLEX_SPD 0x0010
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#define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */
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#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
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#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
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#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
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#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
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#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
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#define IGP01E1000_PSSR_MDIX 0x0008
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#define IGP01E1000_PSSR_SPEED_MASK 0xC000
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#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
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#define IGP02E1000_PHY_CHANNEL_NUM 4
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#define IGP02E1000_PHY_AGC_A 0x11B1
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#define IGP02E1000_PHY_AGC_B 0x12B1
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#define IGP02E1000_PHY_AGC_C 0x14B1
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#define IGP02E1000_PHY_AGC_D 0x18B1
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#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
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#define IGP02E1000_AGC_LENGTH_MASK 0x7F
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#define IGP02E1000_AGC_RANGE 15
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#define IGP03E1000_PHY_MISC_CTRL 0x1B
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#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */
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#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
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#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
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#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
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#define E1000_KMRNCTRLSTA_REN 0x00200000
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#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
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#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
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#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
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#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
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#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
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#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
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/* IFE PHY Extended Status Control */
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#define IFE_PESC_POLARITY_REVERSED 0x0100
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/* IFE PHY Special Control */
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#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
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#define IFE_PSC_FORCE_POLARITY 0x0020
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#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
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/* IFE PHY Special Control and LED Control */
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#define IFE_PSCL_PROBE_MODE 0x0020
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#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
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#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
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/* IFE PHY MDIX Control */
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#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
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#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
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#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
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#endif
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