/*
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* Copyright (C) 2006 Wolfgang Grandegger <wg@grandegger.com>
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*
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* Derived from the PCAN project file driver/src/pcan_pci.c:
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*
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* Copyright (C) 2001-2006 PEAK System-Technik GmbH
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <asm/io.h>
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#include <rtdm/driver.h>
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/* CAN device profile */
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#include <rtdm/can.h>
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#include <rtcan_dev.h>
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#include <rtcan_raw.h>
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#include <rtcan_sja1000.h>
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#include <rtcan_sja1000_regs.h>
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#define RTCAN_DEV_NAME "rtcan%d"
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#define RTCAN_DRV_NAME "PEAK-PCI-CAN"
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static char *peak_pci_board_name = "PEAK-PCI";
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MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
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MODULE_DESCRIPTION("RTCAN board driver for PEAK-PCI cards");
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MODULE_LICENSE("GPL");
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struct rtcan_peak_pci
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{
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struct pci_dev *pci_dev;
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struct rtcan_device *slave_dev;
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int channel;
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volatile void __iomem *base_addr;
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volatile void __iomem *conf_addr;
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};
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#define PEAK_PCI_CAN_SYS_CLOCK (16000000 / 2)
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#define PELICAN_SINGLE (SJA_CDR_CAN_MODE | SJA_CDR_CBP | 0x07 | SJA_CDR_CLK_OFF)
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#define PELICAN_MASTER (SJA_CDR_CAN_MODE | SJA_CDR_CBP | 0x07 )
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#define PELICAN_DEFAULT (SJA_CDR_CAN_MODE )
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#define CHANNEL_SINGLE 0 /* this is a single channel device */
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#define CHANNEL_MASTER 1 /* multi channel device, this device is master */
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#define CHANNEL_SLAVE 2 /* multi channel device, this is slave */
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// important PITA registers
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#define PITA_ICR 0x00 // interrupt control register
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#define PITA_GPIOICR 0x18 // general purpose IO interface control register
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#define PITA_MISC 0x1C // miscellanoes register
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#define PEAK_PCI_VENDOR_ID 0x001C // the PCI device and vendor IDs
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#define PEAK_PCI_DEVICE_ID 0x0001 // Device ID for PCI and older PCIe cards
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#define PEAK_PCIE_DEVICE_ID 0x0003 // Device ID for newer PCIe cards (IPEH-003027)
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#define PEAK_CPCI_DEVICE_ID 0x0004 // for nextgen cPCI slot cards
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#define PEAK_MPCI_DEVICE_ID 0x0005 // for nextgen miniPCI slot cards
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#define PEAK_PC_104P_DEVICE_ID 0x0006 // PCAN-PC/104+ cards
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#define PEAK_PCI_104E_DEVICE_ID 0x0007 // PCAN-PCI/104 Express cards
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#define PEAK_MPCIE_DEVICE_ID 0x0008 // The miniPCIe slot cards
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#define PEAK_PCIE_OEM_ID 0x0009 // PCAN-PCI Express OEM
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#define PCI_CONFIG_PORT_SIZE 0x1000 // size of the config io-memory
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#define PCI_PORT_SIZE 0x0400 // size of a channel io-memory
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static struct pci_device_id peak_pci_tbl[] = {
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{PEAK_PCI_VENDOR_ID, PEAK_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{PEAK_PCI_VENDOR_ID, PEAK_PCIE_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{PEAK_PCI_VENDOR_ID, PEAK_MPCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{PEAK_PCI_VENDOR_ID, PEAK_MPCIE_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{PEAK_PCI_VENDOR_ID, PEAK_PC_104P_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{PEAK_PCI_VENDOR_ID, PEAK_PCI_104E_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{PEAK_PCI_VENDOR_ID, PEAK_CPCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{PEAK_PCI_VENDOR_ID, PEAK_PCIE_OEM_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{ }
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};
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MODULE_DEVICE_TABLE (pci, peak_pci_tbl);
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static u8 rtcan_peak_pci_read_reg(struct rtcan_device *dev, int port)
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{
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struct rtcan_peak_pci *board = (struct rtcan_peak_pci *)dev->board_priv;
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return readb(board->base_addr + ((unsigned long)port << 2));
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}
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static void rtcan_peak_pci_write_reg(struct rtcan_device *dev, int port, u8 data)
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{
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struct rtcan_peak_pci *board = (struct rtcan_peak_pci *)dev->board_priv;
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writeb(data, board->base_addr + ((unsigned long)port << 2));
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}
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static void rtcan_peak_pci_irq_ack(struct rtcan_device *dev)
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{
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struct rtcan_peak_pci *board = (struct rtcan_peak_pci *)dev->board_priv;
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u16 pita_icr_low;
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/* Select and clear in Pita stored interrupt */
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pita_icr_low = readw(board->conf_addr + PITA_ICR);
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if (board->channel == CHANNEL_SLAVE) {
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if (pita_icr_low & 0x0001)
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writew(0x0001, board->conf_addr + PITA_ICR);
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}
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else {
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if (pita_icr_low & 0x0002)
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writew(0x0002, board->conf_addr + PITA_ICR);
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}
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}
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static void rtcan_peak_pci_del_chan(struct rtcan_device *dev,
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int init_step)
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{
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struct rtcan_peak_pci *board;
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u16 pita_icr_high;
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if (!dev)
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return;
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board = (struct rtcan_peak_pci *)dev->board_priv;
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switch (init_step) {
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case 0: /* Full cleanup */
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printk("Removing %s %s device %s\n",
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peak_pci_board_name, dev->ctrl_name, dev->name);
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rtcan_sja1000_unregister(dev);
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fallthrough;
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case 5:
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pita_icr_high = readw(board->conf_addr + PITA_ICR + 2);
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if (board->channel == CHANNEL_SLAVE) {
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pita_icr_high &= ~0x0001;
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} else {
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pita_icr_high &= ~0x0002;
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}
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writew(pita_icr_high, board->conf_addr + PITA_ICR + 2);
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fallthrough;
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case 4:
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iounmap((void *)board->base_addr);
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fallthrough;
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case 3:
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if (board->channel != CHANNEL_SLAVE)
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iounmap((void *)board->conf_addr);
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fallthrough;
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case 2:
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rtcan_dev_free(dev);
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fallthrough;
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case 1:
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break;
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}
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}
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static int rtcan_peak_pci_add_chan(struct pci_dev *pdev, int channel,
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struct rtcan_device **master_dev)
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{
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struct rtcan_device *dev;
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struct rtcan_sja1000 *chip;
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struct rtcan_peak_pci *board;
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u16 pita_icr_high;
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unsigned long addr;
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int ret, init_step = 1;
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dev = rtcan_dev_alloc(sizeof(struct rtcan_sja1000),
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sizeof(struct rtcan_peak_pci));
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if (dev == NULL)
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return -ENOMEM;
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init_step = 2;
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chip = (struct rtcan_sja1000 *)dev->priv;
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board = (struct rtcan_peak_pci *)dev->board_priv;
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board->pci_dev = pdev;
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board->channel = channel;
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if (channel != CHANNEL_SLAVE) {
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addr = pci_resource_start(pdev, 0);
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board->conf_addr = ioremap(addr, PCI_CONFIG_PORT_SIZE);
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if (board->conf_addr == 0) {
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ret = -ENODEV;
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goto failure;
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}
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init_step = 3;
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/* Set GPIO control register */
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writew(0x0005, board->conf_addr + PITA_GPIOICR + 2);
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if (channel == CHANNEL_MASTER)
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writeb(0x00, board->conf_addr + PITA_GPIOICR); /* enable both */
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else
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writeb(0x04, board->conf_addr + PITA_GPIOICR); /* enable single */
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writeb(0x05, board->conf_addr + PITA_MISC + 3); /* toggle reset */
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mdelay(5);
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writeb(0x04, board->conf_addr + PITA_MISC + 3); /* leave parport mux mode */
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} else {
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struct rtcan_peak_pci *master_board =
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(struct rtcan_peak_pci *)(*master_dev)->board_priv;
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master_board->slave_dev = dev;
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board->conf_addr = master_board->conf_addr;
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}
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addr = pci_resource_start(pdev, 1);
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if (channel == CHANNEL_SLAVE)
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addr += 0x400;
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board->base_addr = ioremap(addr, PCI_PORT_SIZE);
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if (board->base_addr == 0) {
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ret = -ENODEV;
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goto failure;
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}
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init_step = 4;
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dev->board_name = peak_pci_board_name;
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chip->read_reg = rtcan_peak_pci_read_reg;
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chip->write_reg = rtcan_peak_pci_write_reg;
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chip->irq_ack = rtcan_peak_pci_irq_ack;
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/* Clock frequency in Hz */
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dev->can_sys_clock = PEAK_PCI_CAN_SYS_CLOCK;
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/* Output control register */
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chip->ocr = SJA_OCR_MODE_NORMAL | SJA_OCR_TX0_PUSHPULL;
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/* Clock divider register */
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if (channel == CHANNEL_MASTER)
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chip->cdr = PELICAN_MASTER;
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else
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chip->cdr = PELICAN_SINGLE;
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strncpy(dev->name, RTCAN_DEV_NAME, IFNAMSIZ);
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/* Register and setup interrupt handling */
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chip->irq_flags = RTDM_IRQTYPE_SHARED;
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chip->irq_num = pdev->irq;
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pita_icr_high = readw(board->conf_addr + PITA_ICR + 2);
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if (channel == CHANNEL_SLAVE) {
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pita_icr_high |= 0x0001;
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} else {
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pita_icr_high |= 0x0002;
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}
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writew(pita_icr_high, board->conf_addr + PITA_ICR + 2);
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init_step = 5;
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printk("%s: base_addr=%p conf_addr=%p irq=%d\n", RTCAN_DRV_NAME,
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board->base_addr, board->conf_addr, chip->irq_num);
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/* Register SJA1000 device */
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ret = rtcan_sja1000_register(dev);
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if (ret) {
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printk(KERN_ERR
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"ERROR %d while trying to register SJA1000 device!\n", ret);
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goto failure;
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}
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if (channel != CHANNEL_SLAVE)
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*master_dev = dev;
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return 0;
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failure:
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rtcan_peak_pci_del_chan(dev, init_step);
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return ret;
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}
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static int peak_pci_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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int ret;
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u16 sub_sys_id;
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struct rtcan_device *master_dev = NULL;
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if (!rtdm_available())
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return -ENODEV;
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printk("%s: initializing device %04x:%04x\n",
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RTCAN_DRV_NAME, pdev->vendor, pdev->device);
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if ((ret = pci_enable_device (pdev)))
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goto failure;
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if ((ret = pci_request_regions(pdev, RTCAN_DRV_NAME)))
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goto failure;
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if ((ret = pci_read_config_word(pdev, 0x2e, &sub_sys_id)))
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goto failure_cleanup;
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/* Enable memory space */
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if ((ret = pci_write_config_word(pdev, 0x04, 2)))
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goto failure_cleanup;
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if ((ret = pci_write_config_word(pdev, 0x44, 0)))
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goto failure_cleanup;
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if (sub_sys_id > 3) {
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if ((ret = rtcan_peak_pci_add_chan(pdev, CHANNEL_MASTER,
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&master_dev)))
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goto failure_cleanup;
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if ((ret = rtcan_peak_pci_add_chan(pdev, CHANNEL_SLAVE,
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&master_dev)))
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goto failure_cleanup;
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} else {
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if ((ret = rtcan_peak_pci_add_chan(pdev, CHANNEL_SINGLE,
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&master_dev)))
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goto failure_cleanup;
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}
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pci_set_drvdata(pdev, master_dev);
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return 0;
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failure_cleanup:
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if (master_dev)
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rtcan_peak_pci_del_chan(master_dev, 0);
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pci_release_regions(pdev);
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failure:
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return ret;
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}
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static void peak_pci_remove_one(struct pci_dev *pdev)
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{
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struct rtcan_device *dev = pci_get_drvdata(pdev);
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struct rtcan_peak_pci *board = (struct rtcan_peak_pci *)dev->board_priv;
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if (board->slave_dev)
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rtcan_peak_pci_del_chan(board->slave_dev, 0);
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rtcan_peak_pci_del_chan(dev, 0);
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pci_release_regions(pdev);
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pci_disable_device(pdev);
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pci_set_drvdata(pdev, NULL);
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}
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static struct pci_driver rtcan_peak_pci_driver = {
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.name = RTCAN_DRV_NAME,
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.id_table = peak_pci_tbl,
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.probe = peak_pci_init_one,
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.remove = peak_pci_remove_one,
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};
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module_pci_driver(rtcan_peak_pci_driver);
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