// SPDX-License-Identifier: GPL-2.0-only
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/*
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* CAN driver PCI interface.
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*
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* Copyright (C) 2001-2021 PEAK System-Technik GmbH
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* Copyright (C) 2019-2021 Stephane Grosjean <s.grosjean@peak-system.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <rtdm/driver.h>
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#include <rtdm/can.h>
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#include "rtcan_dev.h"
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#include "rtcan_raw.h"
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#include "rtcan_peak_canfd_user.h"
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#ifdef CONFIG_PCI_MSI
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#define PCIEFD_USES_MSI
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#endif
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#ifndef struct_size
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#define struct_size(p, member, n) ((n)*sizeof(*(p)->member) + \
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sizeof(*(p)))
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#endif
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#define DRV_NAME "xeno_peak_pciefd"
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static char *pciefd_board_name = "PEAK-PCIe FD";
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MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>");
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MODULE_DESCRIPTION("RTCAN driver for PEAK PCAN PCIe/M.2 FD family cards");
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MODULE_LICENSE("GPL v2");
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#define PEAK_PCI_VENDOR_ID 0x001c /* The PCI device and vendor IDs */
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#define PEAK_PCIEFD_ID 0x0013 /* for PCIe slot cards */
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#define PCAN_CPCIEFD_ID 0x0014 /* for Compact-PCI Serial slot cards */
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#define PCAN_PCIE104FD_ID 0x0017 /* for PCIe-104 Express slot cards */
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#define PCAN_MINIPCIEFD_ID 0x0018 /* for mini-PCIe slot cards */
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#define PCAN_PCIEFD_OEM_ID 0x0019 /* for PCIe slot OEM cards */
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#define PCAN_M2_ID 0x001a /* for M2 slot cards */
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/* supported device ids. */
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static const struct pci_device_id peak_pciefd_tbl[] = {
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{PEAK_PCI_VENDOR_ID, PEAK_PCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{PEAK_PCI_VENDOR_ID, PCAN_CPCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{PEAK_PCI_VENDOR_ID, PCAN_PCIE104FD_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{PEAK_PCI_VENDOR_ID, PCAN_MINIPCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{PEAK_PCI_VENDOR_ID, PCAN_PCIEFD_OEM_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{PEAK_PCI_VENDOR_ID, PCAN_M2_ID, PCI_ANY_ID, PCI_ANY_ID,},
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{0,}
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};
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MODULE_DEVICE_TABLE(pci, peak_pciefd_tbl);
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/* PEAK PCIe board access description */
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#define PCIEFD_BAR0_SIZE (64 * 1024)
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#define PCIEFD_RX_DMA_SIZE (4 * 1024)
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#define PCIEFD_TX_DMA_SIZE (4 * 1024)
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#define PCIEFD_TX_PAGE_SIZE (2 * 1024)
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/* System Control Registers */
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#define PCIEFD_REG_SYS_CTL_SET 0x0000 /* set bits */
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#define PCIEFD_REG_SYS_CTL_CLR 0x0004 /* clear bits */
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/* Version info registers */
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#define PCIEFD_REG_SYS_VER1 0x0040 /* version reg #1 */
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#define PCIEFD_REG_SYS_VER2 0x0044 /* version reg #2 */
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#define PCIEFD_FW_VERSION(x, y, z) (((u32)(x) << 24) | \
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((u32)(y) << 16) | \
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((u32)(z) << 8))
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/* System Control Registers Bits */
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#define PCIEFD_SYS_CTL_TS_RST 0x00000001 /* timestamp clock */
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#define PCIEFD_SYS_CTL_CLK_EN 0x00000002 /* system clock */
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/* CAN-FD channel addresses */
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#define PCIEFD_CANX_OFF(c) (((c) + 1) * 0x1000)
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#define PCIEFD_ECHO_SKB_MAX PCANFD_ECHO_SKB_DEF
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/* CAN-FD channel registers */
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#define PCIEFD_REG_CAN_MISC 0x0000 /* Misc. control */
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#define PCIEFD_REG_CAN_CLK_SEL 0x0008 /* Clock selector */
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#define PCIEFD_REG_CAN_CMD_PORT_L 0x0010 /* 64-bits command port */
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#define PCIEFD_REG_CAN_CMD_PORT_H 0x0014
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#define PCIEFD_REG_CAN_TX_REQ_ACC 0x0020 /* Tx request accumulator */
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#define PCIEFD_REG_CAN_TX_CTL_SET 0x0030 /* Tx control set register */
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#define PCIEFD_REG_CAN_TX_CTL_CLR 0x0038 /* Tx control clear register */
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#define PCIEFD_REG_CAN_TX_DMA_ADDR_L 0x0040 /* 64-bits addr for Tx DMA */
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#define PCIEFD_REG_CAN_TX_DMA_ADDR_H 0x0044
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#define PCIEFD_REG_CAN_RX_CTL_SET 0x0050 /* Rx control set register */
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#define PCIEFD_REG_CAN_RX_CTL_CLR 0x0058 /* Rx control clear register */
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#define PCIEFD_REG_CAN_RX_CTL_WRT 0x0060 /* Rx control write register */
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#define PCIEFD_REG_CAN_RX_CTL_ACK 0x0068 /* Rx control ACK register */
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#define PCIEFD_REG_CAN_RX_DMA_ADDR_L 0x0070 /* 64-bits addr for Rx DMA */
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#define PCIEFD_REG_CAN_RX_DMA_ADDR_H 0x0074
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/* CAN-FD channel misc register bits */
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#define CANFD_MISC_TS_RST 0x00000001 /* timestamp cnt rst */
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/* CAN-FD channel Clock SELector Source & DIVider */
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#define CANFD_CLK_SEL_DIV_MASK 0x00000007
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#define CANFD_CLK_SEL_DIV_60MHZ 0x00000000 /* SRC=240MHz only */
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#define CANFD_CLK_SEL_DIV_40MHZ 0x00000001 /* SRC=240MHz only */
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#define CANFD_CLK_SEL_DIV_30MHZ 0x00000002 /* SRC=240MHz only */
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#define CANFD_CLK_SEL_DIV_24MHZ 0x00000003 /* SRC=240MHz only */
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#define CANFD_CLK_SEL_DIV_20MHZ 0x00000004 /* SRC=240MHz only */
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#define CANFD_CLK_SEL_SRC_MASK 0x00000008 /* 0=80MHz, 1=240MHz */
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#define CANFD_CLK_SEL_SRC_240MHZ 0x00000008
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#define CANFD_CLK_SEL_SRC_80MHZ (~CANFD_CLK_SEL_SRC_240MHZ & \
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CANFD_CLK_SEL_SRC_MASK)
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#define CANFD_CLK_SEL_20MHZ (CANFD_CLK_SEL_SRC_240MHZ |\
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CANFD_CLK_SEL_DIV_20MHZ)
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#define CANFD_CLK_SEL_24MHZ (CANFD_CLK_SEL_SRC_240MHZ |\
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CANFD_CLK_SEL_DIV_24MHZ)
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#define CANFD_CLK_SEL_30MHZ (CANFD_CLK_SEL_SRC_240MHZ |\
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CANFD_CLK_SEL_DIV_30MHZ)
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#define CANFD_CLK_SEL_40MHZ (CANFD_CLK_SEL_SRC_240MHZ |\
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CANFD_CLK_SEL_DIV_40MHZ)
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#define CANFD_CLK_SEL_60MHZ (CANFD_CLK_SEL_SRC_240MHZ |\
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CANFD_CLK_SEL_DIV_60MHZ)
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#define CANFD_CLK_SEL_80MHZ (CANFD_CLK_SEL_SRC_80MHZ)
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/* CAN-FD channel Rx/Tx control register bits */
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#define CANFD_CTL_UNC_BIT 0x00010000 /* Uncached DMA mem */
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#define CANFD_CTL_RST_BIT 0x00020000 /* reset DMA action */
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#define CANFD_CTL_IEN_BIT 0x00040000 /* IRQ enable */
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/* Rx IRQ Count and Time Limits */
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#define CANFD_CTL_IRQ_CL_DEF 8 /* Rx msg max nb per IRQ in Rx DMA */
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#define CANFD_CTL_IRQ_TL_DEF 5 /* Time before IRQ if < CL (x100 us) */
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#define CANFD_OPTIONS_SET (CANFD_OPTION_ERROR | CANFD_OPTION_BUSLOAD)
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/* Tx anticipation window (link logical address should be aligned on 2K
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* boundary)
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*/
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#define PCIEFD_TX_PAGE_COUNT (PCIEFD_TX_DMA_SIZE / PCIEFD_TX_PAGE_SIZE)
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#define CANFD_MSG_LNK_TX 0x1001 /* Tx msgs link */
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/* 32-bit IRQ status fields, heading Rx DMA area */
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static inline int pciefd_irq_tag(u32 irq_status)
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{
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return irq_status & 0x0000000f;
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}
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static inline int pciefd_irq_rx_cnt(u32 irq_status)
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{
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return (irq_status & 0x000007f0) >> 4;
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}
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static inline int pciefd_irq_is_lnk(u32 irq_status)
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{
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return irq_status & 0x00010000;
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}
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/* Rx record */
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struct pciefd_rx_dma {
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__le32 irq_status;
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__le32 sys_time_low;
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__le32 sys_time_high;
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struct pucan_rx_msg msg[0];
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} __packed __aligned(4);
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/* Tx Link record */
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struct pciefd_tx_link {
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__le16 size;
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__le16 type;
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__le32 laddr_lo;
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__le32 laddr_hi;
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} __packed __aligned(4);
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/* Tx page descriptor */
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struct pciefd_page {
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void *vbase; /* page virtual address */
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dma_addr_t lbase; /* page logical address */
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u32 offset;
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u32 size;
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};
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/* CAN channel object */
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struct pciefd_board;
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struct pciefd_can {
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struct peak_canfd_priv ucan; /* must be the first member */
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void __iomem *reg_base; /* channel config base addr */
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struct pciefd_board *board; /* reverse link */
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struct pucan_command pucan_cmd; /* command buffer */
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dma_addr_t rx_dma_laddr; /* DMA virtual and logical addr */
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void *rx_dma_vaddr; /* for Rx and Tx areas */
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dma_addr_t tx_dma_laddr;
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void *tx_dma_vaddr;
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struct pciefd_page tx_pages[PCIEFD_TX_PAGE_COUNT];
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u16 tx_pages_free; /* free Tx pages counter */
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u16 tx_page_index; /* current page used for Tx */
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rtdm_lock_t tx_lock;
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u32 irq_status;
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u32 irq_tag; /* next irq tag */
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int irq;
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u32 flags;
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};
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/* PEAK-PCIe FD board object */
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struct pciefd_board {
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void __iomem *reg_base;
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struct pci_dev *pci_dev;
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int can_count;
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int irq_flags; /* RTDM_IRQTYPE_SHARED or 0 */
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rtdm_lock_t cmd_lock; /* 64-bits cmds must be atomic */
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struct pciefd_can *can[0]; /* array of network devices */
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};
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#define CANFD_CTL_IRQ_CL_MIN 1
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#define CANFD_CTL_IRQ_CL_MAX 127 /* 7-bit field */
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#define CANFD_CTL_IRQ_TL_MIN 1
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#define CANFD_CTL_IRQ_TL_MAX 15 /* 4-bit field */
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static uint irqcl = CANFD_CTL_IRQ_CL_DEF;
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module_param(irqcl, uint, 0644);
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MODULE_PARM_DESC(irqcl,
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" PCIe FD IRQ Count Limit (default=" __stringify(CANFD_CTL_IRQ_CL_DEF) ")");
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static uint irqtl = CANFD_CTL_IRQ_TL_DEF;
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module_param(irqtl, uint, 0644);
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MODULE_PARM_DESC(irqtl,
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" PCIe FD IRQ Time Limit (default=" __stringify(CANFD_CTL_IRQ_TL_DEF) ")");
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#ifdef PCIEFD_USES_MSI
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#ifdef CONFIG_XENO_OPT_SHIRQ
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/* default behaviour: run as mainline driver in INTx mode */
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#define PCIEFD_USEMSI_DEFAULT 0
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#else
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/* default behaviour: run in MSI mode (one IRQ per channel) */
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#define PCIEFD_USEMSI_DEFAULT 1
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#endif
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static uint usemsi = PCIEFD_USEMSI_DEFAULT;
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module_param(usemsi, uint, 0644);
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MODULE_PARM_DESC(usemsi,
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" 0=INTA; 1=MSI (def=" __stringify(PCIEFD_USEMSI_DEFAULT) ")");
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#endif
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/* read a 32 bit value from a SYS block register */
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static inline u32 pciefd_sys_readreg(const struct pciefd_board *priv, u16 reg)
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{
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return readl(priv->reg_base + reg);
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}
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/* write a 32 bit value into a SYS block register */
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static inline void pciefd_sys_writereg(const struct pciefd_board *priv,
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u32 val, u16 reg)
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{
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writel(val, priv->reg_base + reg);
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}
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/* read a 32 bits value from CAN-FD block register */
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static inline u32 pciefd_can_readreg(const struct pciefd_can *priv, u16 reg)
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{
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return readl(priv->reg_base + reg);
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}
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/* write a 32 bits value into a CAN-FD block register */
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static inline void pciefd_can_writereg(const struct pciefd_can *priv,
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u32 val, u16 reg)
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{
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writel(val, priv->reg_base + reg);
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}
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/* give a channel logical Rx DMA address to the board */
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static void pciefd_can_setup_rx_dma(struct pciefd_can *priv)
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{
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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const u32 dma_addr_h = (u32)(priv->rx_dma_laddr >> 32);
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#else
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const u32 dma_addr_h = 0;
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#endif
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/* (DMA must be reset for Rx) */
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pciefd_can_writereg(priv, CANFD_CTL_RST_BIT,
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PCIEFD_REG_CAN_RX_CTL_SET);
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/* write the logical address of the Rx DMA area for this channel */
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pciefd_can_writereg(priv, (u32)priv->rx_dma_laddr,
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PCIEFD_REG_CAN_RX_DMA_ADDR_L);
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pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_RX_DMA_ADDR_H);
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/* also indicates that Rx DMA is cacheable */
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pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT,
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PCIEFD_REG_CAN_RX_CTL_CLR);
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}
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/* clear channel logical Rx DMA address from the board */
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static void pciefd_can_clear_rx_dma(struct pciefd_can *priv)
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{
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/* DMA must be reset for Rx */
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pciefd_can_writereg(priv, CANFD_CTL_RST_BIT,
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PCIEFD_REG_CAN_RX_CTL_SET);
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/* clear the logical address of the Rx DMA area for this channel */
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pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_L);
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pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_H);
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}
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/* give a channel logical Tx DMA address to the board */
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static void pciefd_can_setup_tx_dma(struct pciefd_can *priv)
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{
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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const u32 dma_addr_h = (u32)(priv->tx_dma_laddr >> 32);
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#else
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const u32 dma_addr_h = 0;
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#endif
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/* (DMA must be reset for Tx) */
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pciefd_can_writereg(priv, CANFD_CTL_RST_BIT,
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PCIEFD_REG_CAN_TX_CTL_SET);
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/* write the logical address of the Tx DMA area for this channel */
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pciefd_can_writereg(priv, (u32)priv->tx_dma_laddr,
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PCIEFD_REG_CAN_TX_DMA_ADDR_L);
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pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_TX_DMA_ADDR_H);
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/* also indicates that Tx DMA is cacheable */
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pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT,
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PCIEFD_REG_CAN_TX_CTL_CLR);
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}
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/* clear channel logical Tx DMA address from the board */
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static void pciefd_can_clear_tx_dma(struct pciefd_can *priv)
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{
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/* DMA must be reset for Tx */
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pciefd_can_writereg(priv, CANFD_CTL_RST_BIT,
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PCIEFD_REG_CAN_TX_CTL_SET);
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/* clear the logical address of the Tx DMA area for this channel */
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pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_L);
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pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_H);
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}
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/* acknowledge interrupt to the device */
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static void pciefd_can_ack_rx_dma(struct pciefd_can *priv)
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{
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/* read value of current IRQ tag and inc it for next one */
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priv->irq_tag = le32_to_cpu(*(__le32 *)priv->rx_dma_vaddr);
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priv->irq_tag++;
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priv->irq_tag &= 0xf;
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/* write the next IRQ tag for this CAN */
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pciefd_can_writereg(priv, priv->irq_tag, PCIEFD_REG_CAN_RX_CTL_ACK);
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}
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/* IRQ handler */
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static int pciefd_irq_handler(rtdm_irq_t *irq_handle)
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{
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struct pciefd_can *priv = rtdm_irq_get_arg(irq_handle, void);
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struct pciefd_rx_dma *rx_dma = priv->rx_dma_vaddr;
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/* INTA mode only, dummy read to sync with PCIe transaction */
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if (!pci_dev_msi_enabled(priv->board->pci_dev))
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(void)pciefd_sys_readreg(priv->board, PCIEFD_REG_SYS_VER1);
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/* read IRQ status from the first 32-bit of the Rx DMA area */
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priv->irq_status = le32_to_cpu(rx_dma->irq_status);
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/* check if this (shared) IRQ is for this CAN */
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if (pciefd_irq_tag(priv->irq_status) != priv->irq_tag)
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return RTDM_IRQ_NONE;
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/* handle rx messages (if any) */
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peak_canfd_handle_msgs_list(&priv->ucan,
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rx_dma->msg,
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pciefd_irq_rx_cnt(priv->irq_status));
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/* handle tx link interrupt (if any) */
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if (pciefd_irq_is_lnk(priv->irq_status)) {
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rtdm_lock_get(&priv->tx_lock);
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priv->tx_pages_free++;
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rtdm_lock_put(&priv->tx_lock);
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/* Wake up a sender */
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rtdm_sem_up(&priv->ucan.rdev->tx_sem);
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}
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/* re-enable Rx DMA transfer for this CAN */
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pciefd_can_ack_rx_dma(priv);
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return RTDM_IRQ_HANDLED;
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}
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/* initialize structures used for sending CAN frames */
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static int pciefd_enable_tx_path(struct peak_canfd_priv *ucan)
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{
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struct pciefd_can *priv = (struct pciefd_can *)ucan;
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int i;
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/* initialize the Tx pages descriptors */
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priv->tx_pages_free = PCIEFD_TX_PAGE_COUNT - 1;
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priv->tx_page_index = 0;
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priv->tx_pages[0].vbase = priv->tx_dma_vaddr;
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priv->tx_pages[0].lbase = priv->tx_dma_laddr;
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for (i = 0; i < PCIEFD_TX_PAGE_COUNT; i++) {
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priv->tx_pages[i].offset = 0;
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priv->tx_pages[i].size = PCIEFD_TX_PAGE_SIZE -
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sizeof(struct pciefd_tx_link);
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if (i) {
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priv->tx_pages[i].vbase =
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priv->tx_pages[i - 1].vbase +
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PCIEFD_TX_PAGE_SIZE;
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priv->tx_pages[i].lbase =
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priv->tx_pages[i - 1].lbase +
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PCIEFD_TX_PAGE_SIZE;
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}
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}
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/* setup Tx DMA addresses into IP core */
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pciefd_can_setup_tx_dma(priv);
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/* start (TX_RST=0) Tx Path */
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pciefd_can_writereg(priv, CANFD_CTL_RST_BIT,
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PCIEFD_REG_CAN_TX_CTL_CLR);
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return 0;
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}
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/* board specific command pre-processing */
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static int pciefd_pre_cmd(struct peak_canfd_priv *ucan)
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{
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struct pciefd_can *priv = (struct pciefd_can *)ucan;
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u16 cmd = pucan_cmd_get_opcode(&priv->pucan_cmd);
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/* pre-process command */
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switch (cmd) {
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case PUCAN_CMD_NORMAL_MODE:
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case PUCAN_CMD_LISTEN_ONLY_MODE:
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if (ucan->rdev->state == CAN_STATE_BUS_OFF)
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break;
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/* setup Rx DMA address */
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pciefd_can_setup_rx_dma(priv);
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/* setup max count of msgs per IRQ */
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pciefd_can_writereg(priv, (irqtl << 8) | irqcl,
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PCIEFD_REG_CAN_RX_CTL_WRT);
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/* clear DMA RST for Rx (Rx start) */
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pciefd_can_writereg(priv, CANFD_CTL_RST_BIT,
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PCIEFD_REG_CAN_RX_CTL_CLR);
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/* reset timestamps */
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pciefd_can_writereg(priv, !CANFD_MISC_TS_RST,
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PCIEFD_REG_CAN_MISC);
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/* do an initial ACK */
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pciefd_can_ack_rx_dma(priv);
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/* enable IRQ for this CAN after having set next irq_tag */
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pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT,
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PCIEFD_REG_CAN_RX_CTL_SET);
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/* Tx path will be setup as soon as RX_BARRIER is received */
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break;
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default:
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break;
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}
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return 0;
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}
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/* write a command */
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static int pciefd_write_cmd(struct peak_canfd_priv *ucan)
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{
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struct pciefd_can *priv = (struct pciefd_can *)ucan;
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unsigned long flags;
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/* 64-bit command must be atomic */
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rtdm_lock_get_irqsave(&priv->board->cmd_lock, flags);
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pciefd_can_writereg(priv, *(u32 *)ucan->cmd_buffer,
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PCIEFD_REG_CAN_CMD_PORT_L);
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pciefd_can_writereg(priv, *(u32 *)(ucan->cmd_buffer + 4),
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PCIEFD_REG_CAN_CMD_PORT_H);
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rtdm_lock_put_irqrestore(&priv->board->cmd_lock, flags);
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return 0;
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}
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/* board specific command post-processing */
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static int pciefd_post_cmd(struct peak_canfd_priv *ucan)
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{
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struct pciefd_can *priv = (struct pciefd_can *)ucan;
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u16 cmd = pucan_cmd_get_opcode(&priv->pucan_cmd);
|
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switch (cmd) {
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case PUCAN_CMD_RESET_MODE:
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if (ucan->rdev->state == CAN_STATE_STOPPED)
|
break;
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/* controller now in reset mode: disable IRQ for this CAN */
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pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT,
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PCIEFD_REG_CAN_RX_CTL_CLR);
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|
/* stop and reset DMA addresses in Tx/Rx engines */
|
pciefd_can_clear_tx_dma(priv);
|
pciefd_can_clear_rx_dma(priv);
|
|
/* wait for above commands to complete (read cycle) */
|
(void)pciefd_sys_readreg(priv->board, PCIEFD_REG_SYS_VER1);
|
|
ucan->rdev->state = CAN_STATE_STOPPED;
|
|
break;
|
}
|
|
return 0;
|
}
|
|
/* allocate enough room into the Tx dma area to store a CAN message */
|
static void *pciefd_alloc_tx_msg(struct peak_canfd_priv *ucan, u16 msg_size,
|
int *room_left)
|
{
|
struct pciefd_can *priv = (struct pciefd_can *)ucan;
|
struct pciefd_page *page = priv->tx_pages + priv->tx_page_index;
|
unsigned long flags;
|
void *msg;
|
|
rtdm_lock_get_irqsave(&priv->tx_lock, flags);
|
|
if (page->offset + msg_size > page->size) {
|
struct pciefd_tx_link *lk;
|
|
/* not enough space in this page: try another one */
|
if (!priv->tx_pages_free) {
|
rtdm_lock_put_irqrestore(&priv->tx_lock, flags);
|
|
/* Tx overflow */
|
return NULL;
|
}
|
|
priv->tx_pages_free--;
|
|
/* keep address of the very last free slot of current page */
|
lk = page->vbase + page->offset;
|
|
/* next, move on a new free page */
|
priv->tx_page_index = (priv->tx_page_index + 1) %
|
PCIEFD_TX_PAGE_COUNT;
|
page = priv->tx_pages + priv->tx_page_index;
|
|
/* put link record to this new page at the end of prev one */
|
lk->size = cpu_to_le16(sizeof(*lk));
|
lk->type = cpu_to_le16(CANFD_MSG_LNK_TX);
|
lk->laddr_lo = cpu_to_le32(page->lbase);
|
|
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
|
lk->laddr_hi = cpu_to_le32(page->lbase >> 32);
|
#else
|
lk->laddr_hi = 0;
|
#endif
|
/* next msgs will be put from the begininng of this new page */
|
page->offset = 0;
|
}
|
|
*room_left = priv->tx_pages_free * page->size;
|
|
rtdm_lock_put_irqrestore(&priv->tx_lock, flags);
|
|
msg = page->vbase + page->offset;
|
|
/* give back room left in the tx ring */
|
*room_left += page->size - (page->offset + msg_size);
|
|
return msg;
|
}
|
|
/* tell the IP core tha a frame has been written into the Tx DMA area */
|
static int pciefd_write_tx_msg(struct peak_canfd_priv *ucan,
|
struct pucan_tx_msg *msg)
|
{
|
struct pciefd_can *priv = (struct pciefd_can *)ucan;
|
struct pciefd_page *page = priv->tx_pages + priv->tx_page_index;
|
|
/* this slot is now reserved for writing the frame */
|
page->offset += le16_to_cpu(msg->size);
|
|
/* tell the board a frame has been written in Tx DMA area */
|
pciefd_can_writereg(priv, 1, PCIEFD_REG_CAN_TX_REQ_ACC);
|
|
return 0;
|
}
|
|
/* probe for CAN channel number #pciefd_board->can_count */
|
static int pciefd_can_probe(struct pciefd_board *pciefd)
|
{
|
struct rtcan_device *rdev;
|
struct pciefd_can *priv;
|
u32 clk;
|
int err;
|
|
/* allocate the RTCAN object */
|
rdev = alloc_peak_canfd_dev(sizeof(*priv), pciefd->can_count);
|
if (!rdev) {
|
dev_err(&pciefd->pci_dev->dev,
|
"failed to alloc RTCAN device object\n");
|
goto failure;
|
}
|
|
/* fill-in board specific parts */
|
rdev->board_name = pciefd_board_name;
|
|
/* fill-in rtcan private object */
|
priv = rdev->priv;
|
|
/* setup PCIe-FD own callbacks */
|
priv->ucan.pre_cmd = pciefd_pre_cmd;
|
priv->ucan.write_cmd = pciefd_write_cmd;
|
priv->ucan.post_cmd = pciefd_post_cmd;
|
priv->ucan.enable_tx_path = pciefd_enable_tx_path;
|
priv->ucan.alloc_tx_msg = pciefd_alloc_tx_msg;
|
priv->ucan.write_tx_msg = pciefd_write_tx_msg;
|
|
/* setup PCIe-FD own command buffer */
|
priv->ucan.cmd_buffer = &priv->pucan_cmd;
|
priv->ucan.cmd_maxlen = sizeof(priv->pucan_cmd);
|
|
priv->board = pciefd;
|
|
/* CAN config regs block address */
|
priv->reg_base = pciefd->reg_base + PCIEFD_CANX_OFF(priv->ucan.index);
|
rdev->base_addr = (unsigned long)priv->reg_base;
|
|
/* allocate non-cacheable DMA'able 4KB memory area for Rx */
|
priv->rx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev,
|
PCIEFD_RX_DMA_SIZE,
|
&priv->rx_dma_laddr,
|
GFP_KERNEL);
|
if (!priv->rx_dma_vaddr) {
|
dev_err(&pciefd->pci_dev->dev,
|
"Rx dmam_alloc_coherent(%u) failure\n",
|
PCIEFD_RX_DMA_SIZE);
|
goto err_free_rtdev;
|
}
|
|
/* allocate non-cacheable DMA'able 4KB memory area for Tx */
|
priv->tx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev,
|
PCIEFD_TX_DMA_SIZE,
|
&priv->tx_dma_laddr,
|
GFP_KERNEL);
|
if (!priv->tx_dma_vaddr) {
|
dev_err(&pciefd->pci_dev->dev,
|
"Tx dmam_alloc_coherent(%u) failure\n",
|
PCIEFD_TX_DMA_SIZE);
|
goto err_free_rtdev;
|
}
|
|
/* CAN clock in RST mode */
|
pciefd_can_writereg(priv, CANFD_MISC_TS_RST, PCIEFD_REG_CAN_MISC);
|
|
/* read current clock value */
|
clk = pciefd_can_readreg(priv, PCIEFD_REG_CAN_CLK_SEL);
|
switch (clk) {
|
case CANFD_CLK_SEL_20MHZ:
|
priv->ucan.rdev->can_sys_clock = 20 * 1000 * 1000;
|
break;
|
case CANFD_CLK_SEL_24MHZ:
|
priv->ucan.rdev->can_sys_clock = 24 * 1000 * 1000;
|
break;
|
case CANFD_CLK_SEL_30MHZ:
|
priv->ucan.rdev->can_sys_clock = 30 * 1000 * 1000;
|
break;
|
case CANFD_CLK_SEL_40MHZ:
|
priv->ucan.rdev->can_sys_clock = 40 * 1000 * 1000;
|
break;
|
case CANFD_CLK_SEL_60MHZ:
|
priv->ucan.rdev->can_sys_clock = 60 * 1000 * 1000;
|
break;
|
default:
|
pciefd_can_writereg(priv, CANFD_CLK_SEL_80MHZ,
|
PCIEFD_REG_CAN_CLK_SEL);
|
|
fallthrough;
|
case CANFD_CLK_SEL_80MHZ:
|
priv->ucan.rdev->can_sys_clock = 80 * 1000 * 1000;
|
break;
|
}
|
|
#ifdef PCIEFD_USES_MSI
|
priv->irq = (pciefd->irq_flags & RTDM_IRQTYPE_SHARED) ?
|
pciefd->pci_dev->irq :
|
pci_irq_vector(pciefd->pci_dev, priv->ucan.index);
|
#else
|
priv->irq = pciefd->pci_dev->irq;
|
#endif
|
|
/* setup irq handler */
|
err = rtdm_irq_request(&rdev->irq_handle,
|
priv->irq,
|
pciefd_irq_handler,
|
pciefd->irq_flags,
|
DRV_NAME,
|
priv);
|
if (err) {
|
dev_err(&pciefd->pci_dev->dev,
|
"rtdm_irq_request(IRQ%u) failure err %d\n",
|
priv->irq, err);
|
goto err_free_rtdev;
|
}
|
|
err = rtcan_dev_register(rdev);
|
if (err) {
|
dev_err(&pciefd->pci_dev->dev,
|
"couldn't register RTCAN device: %d\n", err);
|
goto err_free_irq;
|
}
|
|
rtdm_lock_init(&priv->tx_lock);
|
|
/* save the object address in the board structure */
|
pciefd->can[pciefd->can_count] = priv;
|
|
dev_info(&pciefd->pci_dev->dev, "%s at reg_base=0x%p irq=%d\n",
|
rdev->name, priv->reg_base, priv->irq);
|
|
return 0;
|
|
err_free_irq:
|
rtdm_irq_free(&rdev->irq_handle);
|
|
err_free_rtdev:
|
rtcan_dev_free(rdev);
|
|
failure:
|
return -ENOMEM;
|
}
|
|
/* wakeup all RT tasks that are blocked on read */
|
static void pciefd_can_unlock_recv_tasks(struct rtcan_device *rdev)
|
{
|
struct rtcan_recv *recv_listener = rdev->recv_list;
|
|
while (recv_listener) {
|
struct rtcan_socket *sock = recv_listener->sock;
|
|
/* wakeup any rx task */
|
rtdm_sem_destroy(&sock->recv_sem);
|
|
recv_listener = recv_listener->next;
|
}
|
}
|
|
/* remove a CAN-FD channel by releasing all of its resources */
|
static void pciefd_can_remove(struct pciefd_can *priv)
|
{
|
struct rtcan_device *rdev = priv->ucan.rdev;
|
|
/* unlock any tasks that wait for read on a socket bound to this CAN */
|
pciefd_can_unlock_recv_tasks(rdev);
|
|
/* in case the driver is removed when the interface is UP
|
* (device MUST be closed before being unregistered)
|
*/
|
rdev->do_set_mode(rdev, CAN_MODE_STOP, NULL);
|
|
rtcan_dev_unregister(rdev);
|
rtdm_irq_disable(&rdev->irq_handle);
|
rtdm_irq_free(&rdev->irq_handle);
|
rtcan_dev_free(rdev);
|
}
|
|
/* remove all CAN-FD channels by releasing their own resources */
|
static void pciefd_can_remove_all(struct pciefd_board *pciefd)
|
{
|
while (pciefd->can_count > 0)
|
pciefd_can_remove(pciefd->can[--pciefd->can_count]);
|
}
|
|
/* probe for the entire device */
|
static int peak_pciefd_probe(struct pci_dev *pdev,
|
const struct pci_device_id *ent)
|
{
|
struct pciefd_board *pciefd;
|
int err, can_count;
|
u16 sub_sys_id;
|
u8 hw_ver_major;
|
u8 hw_ver_minor;
|
u8 hw_ver_sub;
|
u32 v2;
|
|
err = pci_enable_device(pdev);
|
if (err)
|
return err;
|
|
err = pci_request_regions(pdev, DRV_NAME);
|
if (err)
|
goto err_disable_pci;
|
|
/* the number of channels depends on sub-system id */
|
err = pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sub_sys_id);
|
if (err)
|
goto err_release_regions;
|
|
dev_dbg(&pdev->dev, "probing device %04x:%04x:%04x\n",
|
pdev->vendor, pdev->device, sub_sys_id);
|
|
if (sub_sys_id >= 0x0012)
|
can_count = 4;
|
else if (sub_sys_id >= 0x0010)
|
can_count = 3;
|
else if (sub_sys_id >= 0x0004)
|
can_count = 2;
|
else
|
can_count = 1;
|
|
/* allocate board structure object */
|
pciefd = devm_kzalloc(&pdev->dev, struct_size(pciefd, can, can_count),
|
GFP_KERNEL);
|
if (!pciefd) {
|
err = -ENOMEM;
|
goto err_release_regions;
|
}
|
|
/* initialize the board structure */
|
pciefd->pci_dev = pdev;
|
rtdm_lock_init(&pciefd->cmd_lock);
|
|
/* save the PCI BAR0 virtual address for further system regs access */
|
pciefd->reg_base = pci_iomap(pdev, 0, PCIEFD_BAR0_SIZE);
|
if (!pciefd->reg_base) {
|
dev_err(&pdev->dev, "failed to map PCI resource #0\n");
|
err = -ENOMEM;
|
goto err_release_regions;
|
}
|
|
/* read the firmware version number */
|
v2 = pciefd_sys_readreg(pciefd, PCIEFD_REG_SYS_VER2);
|
|
hw_ver_major = (v2 & 0x0000f000) >> 12;
|
hw_ver_minor = (v2 & 0x00000f00) >> 8;
|
hw_ver_sub = (v2 & 0x000000f0) >> 4;
|
|
dev_info(&pdev->dev,
|
"%ux CAN-FD PCAN-PCIe FPGA v%u.%u.%u:\n", can_count,
|
hw_ver_major, hw_ver_minor, hw_ver_sub);
|
|
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
|
/* DMA logic doesn't handle mix of 32-bit and 64-bit logical addresses
|
* in fw <= 3.2.x
|
*/
|
if (PCIEFD_FW_VERSION(hw_ver_major, hw_ver_minor, hw_ver_sub) <
|
PCIEFD_FW_VERSION(3, 3, 0)) {
|
err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
if (err)
|
dev_warn(&pdev->dev,
|
"warning: can't set DMA mask %llxh (err %d)\n",
|
DMA_BIT_MASK(32), err);
|
}
|
#endif
|
|
/* default interrupt mode is: shared INTx */
|
pciefd->irq_flags = RTDM_IRQTYPE_SHARED;
|
|
#ifdef PCIEFD_USES_MSI
|
if (usemsi) {
|
err = pci_msi_vec_count(pdev);
|
if (err > 0) {
|
int msi_maxvec = err;
|
|
err = pci_alloc_irq_vectors_affinity(pdev, can_count,
|
msi_maxvec,
|
PCI_IRQ_MSI,
|
NULL);
|
dev_info(&pdev->dev,
|
"MSI[%u..%u] enabling status: %d\n",
|
can_count, msi_maxvec, err);
|
|
/* if didn't get the requested count of MSI, fall back
|
* to INTx
|
*/
|
if (err >= can_count)
|
pciefd->irq_flags &= ~RTDM_IRQTYPE_SHARED;
|
else if (err >= 0)
|
pci_free_irq_vectors(pdev);
|
}
|
}
|
#endif
|
|
/* stop system clock */
|
pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_CLK_EN,
|
PCIEFD_REG_SYS_CTL_CLR);
|
|
pci_set_master(pdev);
|
|
/* create now the corresponding channels objects */
|
while (pciefd->can_count < can_count) {
|
err = pciefd_can_probe(pciefd);
|
if (err)
|
goto err_free_canfd;
|
|
pciefd->can_count++;
|
}
|
|
/* set system timestamps counter in RST mode */
|
pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_TS_RST,
|
PCIEFD_REG_SYS_CTL_SET);
|
|
/* wait a bit (read cycle) */
|
(void)pciefd_sys_readreg(pciefd, PCIEFD_REG_SYS_VER1);
|
|
/* free all clocks */
|
pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_TS_RST,
|
PCIEFD_REG_SYS_CTL_CLR);
|
|
/* start system clock */
|
pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_CLK_EN,
|
PCIEFD_REG_SYS_CTL_SET);
|
|
/* remember the board structure address in the device user data */
|
pci_set_drvdata(pdev, pciefd);
|
|
return 0;
|
|
err_free_canfd:
|
pciefd_can_remove_all(pciefd);
|
|
#ifdef PCIEFD_USES_MSI
|
pci_free_irq_vectors(pdev);
|
#endif
|
pci_iounmap(pdev, pciefd->reg_base);
|
|
err_release_regions:
|
pci_release_regions(pdev);
|
|
err_disable_pci:
|
pci_disable_device(pdev);
|
|
/* pci_xxx_config_word() return positive PCIBIOS_xxx error codes while
|
* the probe() function must return a negative errno in case of failure
|
* (err is unchanged if negative)
|
*/
|
return pcibios_err_to_errno(err);
|
}
|
|
/* free the board structure object, as well as its resources: */
|
static void peak_pciefd_remove(struct pci_dev *pdev)
|
{
|
struct pciefd_board *pciefd = pci_get_drvdata(pdev);
|
|
/* release CAN-FD channels resources */
|
pciefd_can_remove_all(pciefd);
|
|
#ifdef PCIEFD_USES_MSI
|
pci_free_irq_vectors(pdev);
|
#endif
|
pci_iounmap(pdev, pciefd->reg_base);
|
|
pci_release_regions(pdev);
|
pci_disable_device(pdev);
|
}
|
|
static struct pci_driver rtcan_peak_pciefd_driver = {
|
.name = DRV_NAME,
|
.id_table = peak_pciefd_tbl,
|
.probe = peak_pciefd_probe,
|
.remove = peak_pciefd_remove,
|
};
|
|
static int __init rtcan_peak_pciefd_init(void)
|
{
|
if (!realtime_core_enabled())
|
return 0;
|
|
return pci_register_driver(&rtcan_peak_pciefd_driver);
|
}
|
|
static void __exit rtcan_peak_pciefd_exit(void)
|
{
|
if (realtime_core_enabled())
|
pci_unregister_driver(&rtcan_peak_pciefd_driver);
|
}
|
|
module_init(rtcan_peak_pciefd_init);
|
module_exit(rtcan_peak_pciefd_exit);
|
