/*
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* Copyright (C) 2006 Wolfgang Grandegger <wg@grandegger.com>
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*
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* Based on linux-2.4.25/include/asm-ppc/mpc5xxx.h
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* Prototypes, etc. for the Motorola MPC5xxx embedded cpu chips
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*
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* Author: Dale Farnsworth <dfarnsworth@mvista.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef __RTCAN_MSCAN_REGS_H_
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#define __RTCAN_MSCAN_REGS_H_
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#include <linux/version.h>
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#include <linux/of_platform.h>
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#include <asm/mpc52xx.h>
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static inline void __iomem *mpc5xxx_gpio_find_and_map(void)
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{
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struct device_node *ofn;
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ofn = of_find_compatible_node(NULL, NULL, "mpc5200-gpio");
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if (!ofn)
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ofn = of_find_compatible_node(NULL, NULL, "fsl,mpc5200-gpio");
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return ofn ? of_iomap(ofn, 0) : NULL;
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}
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#define MPC5xxx_GPIO mpc5xxx_gpio_find_and_map()
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#define mpc5xxx_gpio mpc52xx_gpio
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#define mpc5xxx_get_of_node(ofdev) (ofdev)->dev.of_node
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#define MSCAN_CAN1_ADDR (MSCAN_MBAR + 0x0900) /* MSCAN Module 1 */
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#define MSCAN_CAN2_ADDR (MSCAN_MBAR + 0x0980) /* MSCAN Module 2 */
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#define MSCAN_SIZE 0x80
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/* MSCAN control register 0 (CANCTL0) bits */
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#define MSCAN_RXFRM 0x80
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#define MSCAN_RXACT 0x40
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#define MSCAN_CSWAI 0x20
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#define MSCAN_SYNCH 0x10
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#define MSCAN_TIME 0x08
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#define MSCAN_WUPE 0x04
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#define MSCAN_SLPRQ 0x02
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#define MSCAN_INITRQ 0x01
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/* MSCAN control register 1 (CANCTL1) bits */
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#define MSCAN_CANE 0x80
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#define MSCAN_CLKSRC 0x40
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#define MSCAN_LOOPB 0x20
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#define MSCAN_LISTEN 0x10
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#define MSCAN_WUPM 0x04
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#define MSCAN_SLPAK 0x02
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#define MSCAN_INITAK 0x01
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/* MSCAN receiver flag register (CANRFLG) bits */
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#define MSCAN_WUPIF 0x80
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#define MSCAN_CSCIF 0x40
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#define MSCAN_RSTAT1 0x20
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#define MSCAN_RSTAT0 0x10
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#define MSCAN_TSTAT1 0x08
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#define MSCAN_TSTAT0 0x04
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#define MSCAN_OVRIF 0x02
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#define MSCAN_RXF 0x01
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/* MSCAN receiver interrupt enable register (CANRIER) bits */
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#define MSCAN_WUPIE 0x80
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#define MSCAN_CSCIE 0x40
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#define MSCAN_RSTATE1 0x20
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#define MSCAN_RSTATE0 0x10
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#define MSCAN_TSTATE1 0x08
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#define MSCAN_TSTATE0 0x04
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#define MSCAN_OVRIE 0x02
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#define MSCAN_RXFIE 0x01
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/* MSCAN transmitter flag register (CANTFLG) bits */
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#define MSCAN_TXE2 0x04
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#define MSCAN_TXE1 0x02
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#define MSCAN_TXE0 0x01
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#define MSCAN_TXE (MSCAN_TXE2 | MSCAN_TXE1 | MSCAN_TXE0)
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/* MSCAN transmitter interrupt enable register (CANTIER) bits */
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#define MSCAN_TXIE2 0x04
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#define MSCAN_TXIE1 0x02
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#define MSCAN_TXIE0 0x01
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#define MSCAN_TXIE (MSCAN_TXIE2 | MSCAN_TXIE1 | MSCAN_TXIE0)
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/* MSCAN transmitter message abort request (CANTARQ) bits */
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#define MSCAN_ABTRQ2 0x04
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#define MSCAN_ABTRQ1 0x02
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#define MSCAN_ABTRQ0 0x01
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/* MSCAN transmitter message abort ack (CANTAAK) bits */
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#define MSCAN_ABTAK2 0x04
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#define MSCAN_ABTAK1 0x02
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#define MSCAN_ABTAK0 0x01
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/* MSCAN transmit buffer selection (CANTBSEL) bits */
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#define MSCAN_TX2 0x04
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#define MSCAN_TX1 0x02
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#define MSCAN_TX0 0x01
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/* MSCAN ID acceptance control register (CANIDAC) bits */
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#define MSCAN_IDAM1 0x20
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#define MSCAN_IDAM0 0x10
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#define MSCAN_IDHIT2 0x04
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#define MSCAN_IDHIT1 0x02
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#define MSCAN_IDHIT0 0x01
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struct mscan_msgbuf {
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volatile u8 idr[0x8]; /* 0x00 */
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volatile u8 dsr[0x10]; /* 0x08 */
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volatile u8 dlr; /* 0x18 */
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volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */
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volatile u16 rsrv1; /* 0x1A */
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volatile u8 tsrh; /* 0x1C */
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volatile u8 tsrl; /* 0x1D */
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volatile u16 rsrv2; /* 0x1E */
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};
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struct mscan_regs {
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volatile u8 canctl0; /* MSCAN + 0x00 */
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volatile u8 canctl1; /* MSCAN + 0x01 */
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volatile u16 rsrv1; /* MSCAN + 0x02 */
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volatile u8 canbtr0; /* MSCAN + 0x04 */
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volatile u8 canbtr1; /* MSCAN + 0x05 */
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volatile u16 rsrv2; /* MSCAN + 0x06 */
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volatile u8 canrflg; /* MSCAN + 0x08 */
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volatile u8 canrier; /* MSCAN + 0x09 */
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volatile u16 rsrv3; /* MSCAN + 0x0A */
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volatile u8 cantflg; /* MSCAN + 0x0C */
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volatile u8 cantier; /* MSCAN + 0x0D */
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volatile u16 rsrv4; /* MSCAN + 0x0E */
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volatile u8 cantarq; /* MSCAN + 0x10 */
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volatile u8 cantaak; /* MSCAN + 0x11 */
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volatile u16 rsrv5; /* MSCAN + 0x12 */
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volatile u8 cantbsel; /* MSCAN + 0x14 */
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volatile u8 canidac; /* MSCAN + 0x15 */
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volatile u16 rsrv6[3]; /* MSCAN + 0x16 */
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volatile u8 canrxerr; /* MSCAN + 0x1C */
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volatile u8 cantxerr; /* MSCAN + 0x1D */
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volatile u16 rsrv7; /* MSCAN + 0x1E */
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volatile u8 canidar0; /* MSCAN + 0x20 */
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volatile u8 canidar1; /* MSCAN + 0x21 */
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volatile u16 rsrv8; /* MSCAN + 0x22 */
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volatile u8 canidar2; /* MSCAN + 0x24 */
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volatile u8 canidar3; /* MSCAN + 0x25 */
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volatile u16 rsrv9; /* MSCAN + 0x26 */
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volatile u8 canidmr0; /* MSCAN + 0x28 */
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volatile u8 canidmr1; /* MSCAN + 0x29 */
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volatile u16 rsrv10; /* MSCAN + 0x2A */
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volatile u8 canidmr2; /* MSCAN + 0x2C */
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volatile u8 canidmr3; /* MSCAN + 0x2D */
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volatile u16 rsrv11; /* MSCAN + 0x2E */
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volatile u8 canidar4; /* MSCAN + 0x30 */
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volatile u8 canidar5; /* MSCAN + 0x31 */
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volatile u16 rsrv12; /* MSCAN + 0x32 */
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volatile u8 canidar6; /* MSCAN + 0x34 */
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volatile u8 canidar7; /* MSCAN + 0x35 */
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volatile u16 rsrv13; /* MSCAN + 0x36 */
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volatile u8 canidmr4; /* MSCAN + 0x38 */
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volatile u8 canidmr5; /* MSCAN + 0x39 */
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volatile u16 rsrv14; /* MSCAN + 0x3A */
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volatile u8 canidmr6; /* MSCAN + 0x3C */
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volatile u8 canidmr7; /* MSCAN + 0x3D */
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volatile u16 rsrv15; /* MSCAN + 0x3E */
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struct mscan_msgbuf canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */
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struct mscan_msgbuf cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */
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};
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/* Clock source selection
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*/
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#define MSCAN_CLKSRC_BUS 0
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#define MSCAN_CLKSRC_XTAL MSCAN_CLKSRC
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#define MSCAN_CLKSRC_IPS MSCAN_CLKSRC
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/* Message type access macros.
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*/
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#define MSCAN_BUF_STD_RTR 0x10
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#define MSCAN_BUF_EXT_RTR 0x01
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#define MSCAN_BUF_EXTENDED 0x08
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#define MSCAN_IDAM1 0x20
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/* Value for the interrupt enable register */
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#define MSCAN_RIER (MSCAN_OVRIE | \
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MSCAN_RXFIE | \
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MSCAN_WUPIF | \
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MSCAN_CSCIE | \
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MSCAN_RSTATE0 | \
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MSCAN_RSTATE1 | \
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MSCAN_TSTATE0 | \
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MSCAN_TSTATE1)
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#define BTR0_BRP_MASK 0x3f
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#define BTR0_SJW_SHIFT 6
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#define BTR0_SJW_MASK (0x3 << BTR0_SJW_SHIFT)
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#define BTR1_TSEG1_MASK 0xf
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#define BTR1_TSEG2_SHIFT 4
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#define BTR1_TSEG2_MASK (0x7 << BTR1_TSEG2_SHIFT)
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#define BTR1_SAM_SHIFT 7
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#define BTR0_SET_BRP(brp) (((brp) - 1) & BTR0_BRP_MASK)
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#define BTR0_SET_SJW(sjw) ((((sjw) - 1) << BTR0_SJW_SHIFT) & \
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BTR0_SJW_MASK)
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#define BTR1_SET_TSEG1(tseg1) (((tseg1) - 1) & BTR1_TSEG1_MASK)
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#define BTR1_SET_TSEG2(tseg2) ((((tseg2) - 1) << BTR1_TSEG2_SHIFT) & \
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BTR1_TSEG2_MASK)
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#define BTR1_SET_SAM(sam) (((sam) & 1) << BTR1_SAM_SHIFT)
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#endif /* __RTCAN_MSCAN_REGS_H_ */
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