/*
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* CAN bus driver for the Freescale MPC5xxx embedded CPU.
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*
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* Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
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* Varma Electronics Oy
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* Copyright (C) 2008-2010 Wolfgang Grandegger <wg@grandegger.com>
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* Copyright (C) 2009 Wolfram Sang, Pengutronix <w.sang@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the version 2 of the GNU General Public License
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* as published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/netdevice.h>
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#include <linux/of_platform.h>
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#include <sysdev/fsl_soc.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/mpc52xx.h>
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#include "rtcan_dev.h"
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#include "rtcan_mscan_regs.h"
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#include "rtcan_mscan.h"
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#define of_device platform_device
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#define of_platform_driver platform_driver
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#define of_register_platform_driver platform_driver_register
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#define of_unregister_platform_driver platform_driver_unregister
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static char mscan_ctrl_name_mpc5200[] = "MSCAN-MPC5200";
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static char mscan_ctrl_name_mpc512x[] = "MSCAN-MPC512x";
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static char mscan_board_name[] = "unkown";
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struct mpc5xxx_can_data {
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unsigned int type;
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u32 (*get_clock)(struct of_device *ofdev, const char *clock_name,
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int *mscan_clksrc);
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};
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#ifdef CONFIG_PPC_MPC52xx
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static struct of_device_id mpc52xx_cdm_ids[] = {
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{ .compatible = "fsl,mpc5200-cdm", },
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{}
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};
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static u32 mpc52xx_can_get_clock(struct of_device *ofdev,
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const char *clock_name,
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int *mscan_clksrc)
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{
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unsigned int pvr;
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struct mpc52xx_cdm __iomem *cdm;
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struct device_node *np_cdm;
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unsigned int freq;
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u32 val;
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pvr = mfspr(SPRN_PVR);
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/*
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* Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
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* (IP_CLK) can be selected as MSCAN clock source. According to
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* the MPC5200 user's manual, the oscillator clock is the better
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* choice as it has less jitter. For this reason, it is selected
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* by default. Unfortunately, it can not be selected for the old
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* MPC5200 Rev. A chips due to a hardware bug (check errata).
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*/
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if (clock_name && strcmp(clock_name, "ip") == 0)
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*mscan_clksrc = MSCAN_CLKSRC_BUS;
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else
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*mscan_clksrc = MSCAN_CLKSRC_XTAL;
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freq = mpc5xxx_get_bus_frequency(mpc5xxx_get_of_node(ofdev));
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if (!freq)
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return 0;
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if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011)
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return freq;
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/* Determine SYS_XTAL_IN frequency from the clock domain settings */
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np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids);
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if (!np_cdm) {
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dev_err(&ofdev->dev, "can't get clock node!\n");
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return 0;
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}
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cdm = of_iomap(np_cdm, 0);
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if (in_8(&cdm->ipb_clk_sel) & 0x1)
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freq *= 2;
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val = in_be32(&cdm->rstcfg);
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freq *= (val & (1 << 5)) ? 8 : 4;
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freq /= (val & (1 << 6)) ? 12 : 16;
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of_node_put(np_cdm);
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iounmap(cdm);
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return freq;
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}
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#else /* !CONFIG_PPC_MPC5200 */
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static u32 mpc52xx_can_get_clock(struct of_device *ofdev,
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const char *clock_name,
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int *mscan_clksrc)
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{
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return 0;
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}
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#endif /* CONFIG_PPC_MPC52xx */
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#ifdef CONFIG_PPC_MPC512x
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struct mpc512x_clockctl {
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u32 spmr; /* System PLL Mode Reg */
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u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
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u32 scfr1; /* System Clk Freq Reg 1 */
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u32 scfr2; /* System Clk Freq Reg 2 */
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u32 reserved;
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u32 bcr; /* Bread Crumb Reg */
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u32 pccr[12]; /* PSC Clk Ctrl Reg 0-11 */
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u32 spccr; /* SPDIF Clk Ctrl Reg */
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u32 cccr; /* CFM Clk Ctrl Reg */
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u32 dccr; /* DIU Clk Cnfg Reg */
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u32 mccr[4]; /* MSCAN Clk Ctrl Reg 1-3 */
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};
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static struct of_device_id mpc512x_clock_ids[] = {
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{ .compatible = "fsl,mpc5121-clock", },
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{}
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};
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static u32 mpc512x_can_get_clock(struct of_device *ofdev,
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const char *clock_name,
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int *mscan_clksrc)
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{
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struct mpc512x_clockctl __iomem *clockctl;
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struct device_node *np_clock;
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struct clk *sys_clk, *ref_clk;
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int plen, clockidx, clocksrc = -1;
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u32 sys_freq, val, clockdiv = 1, freq = 0;
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const u32 *pval;
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np_clock = of_find_matching_node(NULL, mpc512x_clock_ids);
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if (!np_clock) {
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dev_err(&ofdev->dev, "couldn't find clock node\n");
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return -ENODEV;
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}
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clockctl = of_iomap(np_clock, 0);
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if (!clockctl) {
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dev_err(&ofdev->dev, "couldn't map clock registers\n");
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return 0;
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}
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/* Determine the MSCAN device index from the physical address */
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pval = of_get_property(mpc5xxx_get_of_node(ofdev), "reg", &plen);
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BUG_ON(!pval || plen < sizeof(*pval));
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clockidx = (*pval & 0x80) ? 1 : 0;
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if (*pval & 0x2000)
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clockidx += 2;
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/*
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* Clock source and divider selection: 3 different clock sources
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* can be selected: "ip", "ref" or "sys". For the latter two, a
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* clock divider can be defined as well. If the clock source is
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* not specified by the device tree, we first try to find an
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* optimal CAN source clock based on the system clock. If that
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* is not posslible, the reference clock will be used.
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*/
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if (clock_name && !strcmp(clock_name, "ip")) {
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*mscan_clksrc = MSCAN_CLKSRC_IPS;
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freq = mpc5xxx_get_bus_frequency(mpc5xxx_get_of_node(ofdev));
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} else {
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*mscan_clksrc = MSCAN_CLKSRC_BUS;
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pval = of_get_property(mpc5xxx_get_of_node(ofdev),
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"fsl,mscan-clock-divider", &plen);
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if (pval && plen == sizeof(*pval))
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clockdiv = *pval;
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if (!clockdiv)
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clockdiv = 1;
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if (!clock_name || !strcmp(clock_name, "sys")) {
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sys_clk = clk_get(&ofdev->dev, "sys_clk");
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if (!sys_clk) {
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dev_err(&ofdev->dev, "couldn't get sys_clk\n");
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goto exit_unmap;
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}
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/* Get and round up/down sys clock rate */
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sys_freq = 1000000 *
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((clk_get_rate(sys_clk) + 499999) / 1000000);
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if (!clock_name) {
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/* A multiple of 16 MHz would be optimal */
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if ((sys_freq % 16000000) == 0) {
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clocksrc = 0;
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clockdiv = sys_freq / 16000000;
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freq = sys_freq / clockdiv;
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}
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} else {
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clocksrc = 0;
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freq = sys_freq / clockdiv;
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}
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}
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if (clocksrc < 0) {
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ref_clk = clk_get(&ofdev->dev, "ref_clk");
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if (!ref_clk) {
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dev_err(&ofdev->dev, "couldn't get ref_clk\n");
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goto exit_unmap;
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}
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clocksrc = 1;
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freq = clk_get_rate(ref_clk) / clockdiv;
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}
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}
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/* Disable clock */
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out_be32(&clockctl->mccr[clockidx], 0x0);
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if (clocksrc >= 0) {
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/* Set source and divider */
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val = (clocksrc << 14) | ((clockdiv - 1) << 17);
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out_be32(&clockctl->mccr[clockidx], val);
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/* Enable clock */
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out_be32(&clockctl->mccr[clockidx], val | 0x10000);
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}
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/* Enable MSCAN clock domain */
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val = in_be32(&clockctl->sccr[1]);
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if (!(val & (1 << 25)))
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out_be32(&clockctl->sccr[1], val | (1 << 25));
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dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n",
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*mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" :
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clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv);
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exit_unmap:
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of_node_put(np_clock);
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iounmap(clockctl);
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return freq;
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}
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#else /* !CONFIG_PPC_MPC512x */
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static u32 mpc512x_can_get_clock(struct of_device *ofdev,
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const char *clock_name,
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int *mscan_clksrc)
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{
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return 0;
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}
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#endif /* CONFIG_PPC_MPC512x */
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static struct of_device_id mpc5xxx_can_table[];
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static int mpc5xxx_can_probe(struct of_device *ofdev)
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{
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struct device_node *np = mpc5xxx_get_of_node(ofdev);
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struct mpc5xxx_can_data *data;
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struct rtcan_device *dev;
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void __iomem *base;
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const char *clock_name = NULL;
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int irq, mscan_clksrc = 0;
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int err = -ENOMEM;
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const struct of_device_id *id;
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id = of_match_device(mpc5xxx_can_table, &ofdev->dev);
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if (!id)
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return -EINVAL;
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data = (struct mpc5xxx_can_data *)id->data;
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base = of_iomap(np, 0);
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if (!base) {
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dev_err(&ofdev->dev, "couldn't ioremap\n");
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return err;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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dev_err(&ofdev->dev, "no irq found\n");
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err = -ENODEV;
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goto exit_unmap_mem;
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}
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dev = rtcan_dev_alloc(0, 0);
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if (!dev)
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goto exit_dispose_irq;
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clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL);
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BUG_ON(!data);
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dev->can_sys_clock = data->get_clock(ofdev, clock_name,
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&mscan_clksrc);
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if (!dev->can_sys_clock) {
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dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n");
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goto exit_free_mscan;
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}
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if (data->type == MSCAN_TYPE_MPC5121)
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dev->ctrl_name = mscan_ctrl_name_mpc512x;
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else
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dev->ctrl_name = mscan_ctrl_name_mpc5200;
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dev->board_name = mscan_board_name;
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dev->base_addr = (unsigned long)base;
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err = rtcan_mscan_register(dev, irq, mscan_clksrc);
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if (err) {
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dev_err(&ofdev->dev, "registering %s failed (err=%d)\n",
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RTCAN_DRV_NAME, err);
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goto exit_free_mscan;
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}
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dev_set_drvdata(&ofdev->dev, dev);
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dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n",
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base, irq, dev->can_sys_clock);
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return 0;
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exit_free_mscan:
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rtcan_dev_free(dev);
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exit_dispose_irq:
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irq_dispose_mapping(irq);
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exit_unmap_mem:
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iounmap(base);
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return err;
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}
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static int mpc5xxx_can_remove(struct of_device *ofdev)
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{
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struct rtcan_device *dev = dev_get_drvdata(&ofdev->dev);
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dev_set_drvdata(&ofdev->dev, NULL);
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rtcan_mscan_unregister(dev);
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iounmap((void *)dev->base_addr);
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rtcan_dev_free(dev);
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return 0;
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}
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static struct mpc5xxx_can_data mpc5200_can_data = {
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.type = MSCAN_TYPE_MPC5200,
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.get_clock = mpc52xx_can_get_clock,
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};
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static struct mpc5xxx_can_data mpc5121_can_data = {
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.type = MSCAN_TYPE_MPC5121,
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.get_clock = mpc512x_can_get_clock,
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};
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static struct of_device_id mpc5xxx_can_table[] = {
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{ .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, },
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/* Note that only MPC5121 Rev. 2 (and later) is supported */
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{ .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, },
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{},
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};
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static struct of_platform_driver mpc5xxx_can_driver = {
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.driver = {
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.owner = THIS_MODULE,
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.name = RTCAN_DRV_NAME,
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.of_match_table = mpc5xxx_can_table,
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},
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.probe = mpc5xxx_can_probe,
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.remove = mpc5xxx_can_remove,
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};
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static int __init mpc5xxx_can_init(void)
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{
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if (!rtdm_available())
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return -ENOSYS;
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return of_register_platform_driver(&mpc5xxx_can_driver);
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}
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module_init(mpc5xxx_can_init);
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static void __exit mpc5xxx_can_exit(void)
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{
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return of_unregister_platform_driver(&mpc5xxx_can_driver);
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};
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module_exit(mpc5xxx_can_exit);
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MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
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MODULE_DESCRIPTION("RT-Socket-CAN driver for MPC5200 and MPC521x");
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MODULE_LICENSE("GPL v2");
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